From: Scott Wood Date: Mon, 20 Mar 2017 02:37:22 +0000 (+0800) Subject: dt-bindings: qoriq-clock: Add coreclk X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=3d362b1fab97dffaf3f6ef55a03c7dcccfa97fd3;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git dt-bindings: qoriq-clock: Add coreclk ls1012a has separate input root clocks for core PLLs versus the platform PLL, with the latter described as sysclk in the hw docs. Update the qoriq-clock binding to allow a second input clock, named "coreclk". If present, this clock will be used for the core PLLs. Signed-off-by: Scott Wood Signed-off-by: Tang Yuantian Acked-by: Rob Herring Signed-off-by: Stephen Boyd --- diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt index 6ed469c66b32..6498e1fdbb33 100644 --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt @@ -57,6 +57,11 @@ Optional properties: - clocks: If clock-frequency is not specified, sysclk may be provided as an input clock. Either clock-frequency or clocks must be provided. + A second input clock, called "coreclk", may be provided if + core PLLs are based on a different input clock from the + platform PLL. +- clock-names: Required if a coreclk is present. Valid names are + "sysclk" and "coreclk". 2. Clock Provider @@ -73,6 +78,7 @@ second cell is the clock index for the specified type. 2 hwaccel index (n in CLKCGnHWACSR) 3 fman 0 for fm1, 1 for fm2 4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4 + 5 coreclk must be 0 3. Example