From: Caleb Crome Date: Mon, 25 Apr 2016 18:36:18 +0000 (-0700) Subject: ASoC: fsl_ssi: add CCSR_SSI_SOR to volatile register list X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=3cc6185bcccff32df41faa97d592a99d258db185;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git ASoC: fsl_ssi: add CCSR_SSI_SOR to volatile register list The CCSR_SSI_SOR is a register that clears the TX and/or the RX fifo on the i.MX SSI port. The fsl_ssi_trigger writes this register in order to clear the fifo at trigger time. However, since the CCSR_SSI_SOR register is not in the volatile list, the caching mechanism prevented the register write in the trigger function. This caused the fifo to not be cleared (because the value was unchanged from the last time the register was written), and thus causes the channels in both TDM or simple I2S mode to slip and be in the wrong time slots on SSI restart. This has gone unnoticed for so long because with simple stereo mode, the consequence is that left and right are swapped, which isn't that noticeable. However, it's catestrophic in some systems that require the channels to be in the right slots. Signed-off-by: Caleb Crome Suggested-by: Arnaud Mouiche Reviewed-by: Fabio Estevam Acked-by: Nicolin Chen Signed-off-by: Mark Brown --- diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c index ed8de1035cda..08dcbbf60adb 100644 --- a/sound/soc/fsl/fsl_ssi.c +++ b/sound/soc/fsl/fsl_ssi.c @@ -137,6 +137,7 @@ static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg) case CCSR_SSI_SACDAT: case CCSR_SSI_SATAG: case CCSR_SSI_SACCST: + case CCSR_SSI_SOR: return true; default: return false;