From: Krzysztof Helt <krzysztof.h1@wp.pl>
Date: Thu, 16 Oct 2008 05:03:41 +0000 (-0700)
Subject: cirrusfb: fix 16bpp modes
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=3b921832d483a2b9d6fabdbb5f871a4f18cb9b65;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

cirrusfb: fix 16bpp modes

The 16bpp mode did not work on the Cirrus cards as the visual type was set
to DIRECTCOLOR instead of TRUECOLOR.  The Alpine family used one incorrect
register setting so this 16bpp modes generated wrong horizontal frequency.

Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
---

diff --git a/drivers/video/cirrusfb.c b/drivers/video/cirrusfb.c
index 245005e61e40..9e0a1c58fde4 100644
--- a/drivers/video/cirrusfb.c
+++ b/drivers/video/cirrusfb.c
@@ -657,7 +657,7 @@ static int cirrusfb_decode_var(const struct fb_var_screeninfo *var,
 	case 16:
 	case 32:
 		info->fix.line_length = var->xres_virtual * maxclockidx;
-		info->fix.visual = FB_VISUAL_DIRECTCOLOR;
+		info->fix.visual = FB_VISUAL_TRUECOLOR;
 		break;
 
 	default:
@@ -1178,10 +1178,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
 
 		case BT_ALPINE:
 			DPRINTK(" (for GD543x)\n");
-			if (var->xres >= 1024)
-				vga_wseq(regbase, CL_SEQR7, 0xa7);
-			else
-				vga_wseq(regbase, CL_SEQR7, 0xa3);
+			vga_wseq(regbase, CL_SEQR7, 0xa7);
 			cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
 			break;