From: Michel Dänzer <michel.daenzer@amd.com>
Date: Tue, 6 Dec 2016 09:33:03 +0000 (+0900)
Subject: drm/amdgpu/dce6: Set MASTER_UPDATE_MODE to 0 in resume_mc_access as well
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=32859f7335d838ee373c40ee0b3c0c6ebc87a488;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

drm/amdgpu/dce6: Set MASTER_UPDATE_MODE to 0 in resume_mc_access as well

Looks like this was missed when dce_v6_0.c was added.

Fixes: e2cdf640cbb5 ("drm/amdgpu: add display controller implementation for si v10")
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
---

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 18cb295c0f38..e564442b6393 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -460,9 +460,8 @@ static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev,
 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
 		if (save->crtc_enabled[i]) {
 			tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
-			if ((tmp & 0x7) != 3) {
+			if ((tmp & 0x7) != 0) {
 				tmp &= ~0x7;
-				tmp |= 0x3;
 				WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
 			}
 			tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);