From: Kyle McMartin Date: Mon, 14 Aug 2006 00:37:26 +0000 (-0400) Subject: [PARISC] PA7200 also supports prefetch for read X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=32104b29cdf93f78ac37e681bd4547413466d13c;p=GitHub%2Fmt8127%2Fandroid_kernel_alcatel_ttab.git [PARISC] PA7200 also supports prefetch for read It seems PA7200 processors also suppress traps on loads to %r0. This means we can prefetch for read on these cpus. Of course, we can't support prefetch for write, since that requires LOAD DOUBLEWORD which was added with PA2.0 Signed-off-by: Kyle McMartin --- diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig index 6dd0ea8f88e0..d2101237442e 100644 --- a/arch/parisc/Kconfig +++ b/arch/parisc/Kconfig @@ -127,7 +127,7 @@ config PA11 config PREFETCH def_bool y - depends on PA8X00 + depends on PA8X00 || PA7200 config 64BIT bool "64-bit kernel" diff --git a/include/asm-parisc/prefetch.h b/include/asm-parisc/prefetch.h index f5a2e7ae2662..5d021726fa33 100644 --- a/include/asm-parisc/prefetch.h +++ b/include/asm-parisc/prefetch.h @@ -24,11 +24,14 @@ extern inline void prefetch(const void *addr) __asm__("ldw 0(%0), %%r0" : : "r" (addr)); } +/* LDD is a PA2.0 addition. */ +#ifdef CONFIG_PA20 #define ARCH_HAS_PREFETCHW extern inline void prefetchw(const void *addr) { __asm__("ldd 0(%0), %%r0" : : "r" (addr)); } +#endif /* CONFIG_PA20 */ #endif /* CONFIG_PREFETCH */ #endif /* __ASSEMBLY__ */