From: Mike Frysinger Date: Mon, 21 May 2007 10:09:23 +0000 (+0800) Subject: Blackfin arch: dont clear status register bits in SWRST so we can actually use it X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=30870b93cd76bdfa7385f8d471345f5f6269fb00;p=GitHub%2Fmt8127%2Fandroid_kernel_alcatel_ttab.git Blackfin arch: dont clear status register bits in SWRST so we can actually use it Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu Signed-off-by: Linus Torvalds --- diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S index 4808edb0680f..7cb8258841d4 100644 --- a/arch/blackfin/mach-bf533/head.S +++ b/arch/blackfin/mach-bf533/head.S @@ -468,12 +468,6 @@ ENTRY(_bfin_reset) w[p0] = r0.l; #endif - /* Clear the bits 13-15 in SWRST if they werent cleared */ - p0.h = hi(SWRST); - p0.l = lo(SWRST); - csync; - r0.l = w[p0]; - /* Clear the IMASK register */ p0.h = hi(IMASK); p0.l = lo(IMASK); diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S index d104e1d8e07a..de78e4281aef 100644 --- a/arch/blackfin/mach-bf537/head.S +++ b/arch/blackfin/mach-bf537/head.S @@ -504,12 +504,6 @@ _delay_lab1_end: nop; #endif - /* Clear the bits 13-15 in SWRST if they werent cleared */ - p0.h = hi(SWRST); - p0.l = lo(SWRST); - csync; - r0.l = w[p0]; - /* Clear the IMASK register */ p0.h = hi(IMASK); p0.l = lo(IMASK); diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S index 7bca478526b9..462c39ed8ec5 100644 --- a/arch/blackfin/mach-bf561/head.S +++ b/arch/blackfin/mach-bf561/head.S @@ -414,12 +414,6 @@ ENTRY(_bfin_reset) w[p0] = r0.l; #endif - /* Clear the bits 13-15 in SWRST if they werent cleared */ - p0.h = hi(SICA_SWRST); - p0.l = lo(SICA_SWRST); - csync; - r0.l = w[p0]; - /* Clear the IMASK register */ p0.h = hi(IMASK); p0.l = lo(IMASK);