From: Paulo Zanoni Date: Wed, 31 Oct 2012 20:12:23 +0000 (-0200) Subject: drm/i915: remove Haswell/LPT bits from ironlake_pch_enable X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=303b81e040c14ba6b2d885d051d2c18390d1eeca;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git drm/i915: remove Haswell/LPT bits from ironlake_pch_enable Since now we have lpt_pch_enable for them. Signed-off-by: Paulo Zanoni Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index ac65d1aaf3c2..298fd73f481b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3086,10 +3086,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) * enable sequence. */ intel_enable_pch_pll(intel_crtc); - if (HAS_PCH_LPT(dev)) { - DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n"); - lpt_program_iclkip(crtc); - } else if (HAS_PCH_CPT(dev)) { + if (HAS_PCH_CPT(dev)) { u32 sel; temp = I915_READ(PCH_DPLL_SEL); @@ -3126,8 +3123,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe))); - if (!IS_HASWELL(dev)) - intel_fdi_normal_train(crtc); + intel_fdi_normal_train(crtc); /* For PCH DP, enable TRANS_DP_CTL */ if (HAS_PCH_CPT(dev) &&