From: Ben Skeggs Date: Thu, 11 Oct 2012 05:13:10 +0000 (+1000) Subject: drm/nv40/fb: enable z compression X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=2f1cb96d656418815f8f83ce027f5d96095ba717;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git drm/nv40/fb: enable z compression Signed-off-by: Ben Skeggs --- diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/fb.h b/drivers/gpu/drm/nouveau/core/include/subdev/fb.h index aa13f6b2d8eb..eb5cbbf7d444 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/fb.h +++ b/drivers/gpu/drm/nouveau/core/include/subdev/fb.h @@ -151,6 +151,9 @@ int nv30_fb_init(struct nouveau_object *); void nv30_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size, u32 pitch, u32 flags, struct nouveau_fb_tile *); +void nv40_fb_tile_comp(struct nouveau_fb *, int i, u32 size, u32 flags, + struct nouveau_fb_tile *); + int nv41_fb_vram_init(struct nouveau_fb *); int nv41_fb_init(struct nouveau_object *); void nv41_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *); diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c index 37c5e4c2c3f7..fe7e29841aa5 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c @@ -41,15 +41,26 @@ nv40_fb_vram_init(struct nouveau_fb *pfb) case 0x00000300: pfb->ram.type = NV_MEM_TYPE_DDR2; break; } - pfb->ram.size = nv_rd32(pfb, 0x10020c) & 0xff000000; + pfb->ram.size = nv_rd32(pfb, 0x10020c) & 0xff000000; + pfb->ram.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1; return nv_rd32(pfb, 0x100320); } -static void +void nv40_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, struct nouveau_fb_tile *tile) { - tile->zcomp = 0x00000000; + u32 tiles = DIV_ROUND_UP(size, 0x80); + u32 tags = round_up(tiles / pfb->ram.parts, 0x100); + if ( (flags & 2) && + !nouveau_mm_head(&pfb->tags, 1, tags, tags, 1, &tile->tag)) { + tile->zcomp = 0x24000000; /* Z24S8_SPLIT */ + tile->zcomp |= ((tile->tag->offset ) >> 8); + tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13; +#ifdef __BIG_ENDIAN + tile->zcomp |= 0x40000000; +#endif + } } static int diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv41.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv41.c index cc2cff65fcc9..e9e5a08c41a1 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv41.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv41.c @@ -41,7 +41,8 @@ nv41_fb_vram_init(struct nouveau_fb *pfb) if (pfb474 & 0x00000001) pfb->ram.type = NV_MEM_TYPE_DDR1; - pfb->ram.size = nv_rd32(pfb, 0x10020c) & 0xff000000; + pfb->ram.size = nv_rd32(pfb, 0x10020c) & 0xff000000; + pfb->ram.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1; return nv_rd32(pfb, 0x100320); } @@ -86,6 +87,7 @@ nv41_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->base.ram.init = nv41_fb_vram_init; priv->base.tile.regions = 12; priv->base.tile.init = nv30_fb_tile_init; + priv->base.tile.comp = nv40_fb_tile_comp; priv->base.tile.fini = nv20_fb_tile_fini; priv->base.tile.prog = nv41_fb_tile_prog; return nouveau_fb_preinit(&priv->base); diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv47.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv47.c index a2ca3c8e4007..818bba35b368 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv47.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv47.c @@ -47,6 +47,7 @@ nv47_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->base.ram.init = nv41_fb_vram_init; priv->base.tile.regions = 15; priv->base.tile.init = nv30_fb_tile_init; + priv->base.tile.comp = nv40_fb_tile_comp; priv->base.tile.fini = nv20_fb_tile_fini; priv->base.tile.prog = nv41_fb_tile_prog; return nouveau_fb_preinit(&priv->base); diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv49.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv49.c index aaec1e3e1d98..84a31af16ab4 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv49.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv49.c @@ -42,7 +42,8 @@ nv49_fb_vram_init(struct nouveau_fb *pfb) case 0x00000003: break; } - pfb->ram.size = nv_rd32(pfb, 0x10020c) & 0xff000000; + pfb->ram.size = nv_rd32(pfb, 0x10020c) & 0xff000000; + pfb->ram.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1; return nv_rd32(pfb, 0x100320); } @@ -63,6 +64,7 @@ nv49_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->base.ram.init = nv49_fb_vram_init; priv->base.tile.regions = 15; priv->base.tile.init = nv30_fb_tile_init; + priv->base.tile.comp = nv40_fb_tile_comp; priv->base.tile.fini = nv20_fb_tile_fini; priv->base.tile.prog = nv41_fb_tile_prog;