From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Wed, 28 Mar 2012 21:35:31 +0000 (-0700)
Subject: Merge branch 'kvm-updates/3.4' of git://git.kernel.org/pub/scm/virt/kvm/kvm
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=2e7580b0e75d771d93e24e681031a165b1d31071;p=GitHub%2FLineageOS%2FG12%2Fandroid_kernel_amlogic_linux-4.9.git

Merge branch 'kvm-updates/3.4' of git://git./virt/kvm/kvm

Pull kvm updates from Avi Kivity:
 "Changes include timekeeping improvements, support for assigning host
  PCI devices that share interrupt lines, s390 user-controlled guests, a
  large ppc update, and random fixes."

This is with the sign-off's fixed, hopefully next merge window we won't
have rebased commits.

* 'kvm-updates/3.4' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (130 commits)
  KVM: Convert intx_mask_lock to spin lock
  KVM: x86: fix kvm_write_tsc() TSC matching thinko
  x86: kvmclock: abstract save/restore sched_clock_state
  KVM: nVMX: Fix erroneous exception bitmap check
  KVM: Ignore the writes to MSR_K7_HWCR(3)
  KVM: MMU: make use of ->root_level in reset_rsvds_bits_mask
  KVM: PMU: add proper support for fixed counter 2
  KVM: PMU: Fix raw event check
  KVM: PMU: warn when pin control is set in eventsel msr
  KVM: VMX: Fix delayed load of shared MSRs
  KVM: use correct tlbs dirty type in cmpxchg
  KVM: Allow host IRQ sharing for assigned PCI 2.3 devices
  KVM: Ensure all vcpus are consistent with in-kernel irqchip settings
  KVM: x86 emulator: Allow PM/VM86 switch during task switch
  KVM: SVM: Fix CPL updates
  KVM: x86 emulator: VM86 segments must have DPL 3
  KVM: x86 emulator: Fix task switch privilege checks
  arch/powerpc/kvm/book3s_hv.c: included linux/sched.h twice
  KVM: x86 emulator: correctly mask pmc index bits in RDPMC instruction emulation
  KVM: mmu_notifier: Flush TLBs before releasing mmu_lock
  ...
---

2e7580b0e75d771d93e24e681031a165b1d31071
diff --cc arch/x86/kvm/svm.c
index e385214711cb,53efd597f39e..e334389e1c75
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@@ -623,10 -649,38 +652,40 @@@ static int svm_hardware_enable(void *ga
  		__get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT;
  	}
  
+ 
+ 	/*
+ 	 * Get OSVW bits.
+ 	 *
+ 	 * Note that it is possible to have a system with mixed processor
+ 	 * revisions and therefore different OSVW bits. If bits are not the same
+ 	 * on different processors then choose the worst case (i.e. if erratum
+ 	 * is present on one processor and not on another then assume that the
+ 	 * erratum is present everywhere).
+ 	 */
+ 	if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
+ 		uint64_t len, status = 0;
+ 		int err;
+ 
+ 		len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
+ 		if (!err)
+ 			status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
+ 						      &err);
+ 
+ 		if (err)
+ 			osvw_status = osvw_len = 0;
+ 		else {
+ 			if (len < osvw_len)
+ 				osvw_len = len;
+ 			osvw_status |= status;
+ 			osvw_status &= (1ULL << osvw_len) - 1;
+ 		}
+ 	} else
+ 		osvw_status = osvw_len = 0;
+ 
  	svm_init_erratum_383();
  
 +	amd_pmu_enable_virt();
 +
  	return 0;
  }