From: Dinh Nguyen <dinguyen@opensource.altera.com>
Date: Sat, 25 Jul 2015 03:10:59 +0000 (-0500)
Subject: ARM: socfpga: dts: add osc1 as a possible parent for dbg_base_clk
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=2e4c7588f6c1d24ae991a85140e05139e953c9b5;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

ARM: socfpga: dts: add osc1 as a possible parent for dbg_base_clk

The dbg_base_clk can also have osc1 has a parent.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 86e0fb6fff9c..01bdaaa50854 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -164,7 +164,7 @@
 						dbg_base_clk: dbg_base_clk {
 							#clock-cells = <0>;
 							compatible = "altr,socfpga-perip-clk";
-							clocks = <&main_pll>;
+							clocks = <&main_pll>, <&osc1>;
 							div-reg = <0xe8 0 9>;
 							reg = <0x50>;
 						};