From: Florian Fainelli Date: Tue, 9 Feb 2016 20:55:52 +0000 (-0800) Subject: MIPS: Move RIXI exception enabling after vendor-specific cpu_probe X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=2e274768e4dd9565a31cd1979ed6d534cd4e656f;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git MIPS: Move RIXI exception enabling after vendor-specific cpu_probe Some processors may not have the RIXI bit advertised in the Config3 register, not being a MIPS32R2 or R6 core, yet, they might be supporting it through a different way, which is overriden during vendor-specific cpu_probe(). Move the RIXI exceptions enabling after the vendor-specific cpu_probe() function has had a change to run and override the current CPU's options with MIPS_CPU_RIXI. Signed-off-by: Florian Fainelli Cc: john@phrozen.org Cc: cernekee@gmail.com Cc: jon.fraser@broadcom.com Cc: pgynther@google.com Cc: paul.burton@imgtec.com Cc: ddaney.cavm@gmail.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12506/ Signed-off-by: Ralf Baechle --- diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 8eda42a9ca59..4bcbf002a8f7 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -862,15 +862,6 @@ static void decode_configs(struct cpuinfo_mips *c) mips_probe_watch_registers(c); - if (cpu_has_rixi) { - /* Enable the RIXI exceptions */ - set_c0_pagegrain(PG_IEC); - back_to_back_c0_hazard(); - /* Verify the IEC bit is set */ - if (read_c0_pagegrain() & PG_IEC) - c->options |= MIPS_CPU_RIXIEX; - } - #ifndef CONFIG_MIPS_CPS if (cpu_has_mips_r2_r6) { c->core = get_ebase_cpunum(); @@ -1733,6 +1724,15 @@ void cpu_probe(void) */ BUG_ON(current_cpu_type() != c->cputype); + if (cpu_has_rixi) { + /* Enable the RIXI exceptions */ + set_c0_pagegrain(PG_IEC); + back_to_back_c0_hazard(); + /* Verify the IEC bit is set */ + if (read_c0_pagegrain() & PG_IEC) + c->options |= MIPS_CPU_RIXIEX; + } + if (mips_fpu_disabled) c->options &= ~MIPS_CPU_FPU;