From: Sunyoung Kang Date: Mon, 9 Jul 2018 06:16:43 +0000 (+0900) Subject: [COMMON] media: mfc: DRV4.0: clean up mfc_cmd X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=2aa7eaa7a5fcd0e0573a21fbe832daf1dcf30388;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git [COMMON] media: mfc: DRV4.0: clean up mfc_cmd This clean up the mfc_cmd like below. - change to void type when no return value - rename mfc_cmd_init_decode to mfc_cmd_dec_seq_header() - rename mfc_cmd_init_encode to mfc_cmd_enc_seq_header() Change-Id: I77448111d687102681de2ca955c53c57a92732f5 Signed-off-by: Sunyoung Kang --- diff --git a/drivers/media/platform/exynos/mfc/mfc_cmd.c b/drivers/media/platform/exynos/mfc/mfc_cmd.c index 9f4076ebac54..6fcf7ae22bd0 100644 --- a/drivers/media/platform/exynos/mfc/mfc_cmd.c +++ b/drivers/media/platform/exynos/mfc/mfc_cmd.c @@ -23,7 +23,7 @@ #include "mfc_utils.h" #include "mfc_buf.h" -int mfc_cmd_sys_init(struct mfc_dev *dev, +void mfc_cmd_sys_init(struct mfc_dev *dev, enum mfc_buf_usage_type buf_type) { struct mfc_ctx_buf_size *buf_size; @@ -45,8 +45,6 @@ int mfc_cmd_sys_init(struct mfc_dev *dev, mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_SYS_INIT); mfc_debug_leave(); - - return 0; } void mfc_cmd_sleep(struct mfc_dev *dev) @@ -70,7 +68,7 @@ void mfc_cmd_wakeup(struct mfc_dev *dev) } /* Open a new instance and get its number */ -int mfc_cmd_open_inst(struct mfc_ctx *ctx) +void mfc_cmd_open_inst(struct mfc_ctx *ctx) { struct mfc_dev *dev = ctx->dev; unsigned int reg; @@ -106,8 +104,6 @@ int mfc_cmd_open_inst(struct mfc_ctx *ctx) mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_OPEN_INSTANCE); mfc_debug_leave(); - - return 0; } /* Close instance */ @@ -134,7 +130,7 @@ int mfc_cmd_close_inst(struct mfc_ctx *ctx) return 0; } -int mfc_cmd_abort_inst(struct mfc_ctx *ctx) +void mfc_cmd_abort_inst(struct mfc_ctx *ctx) { struct mfc_dev *dev = ctx->dev; @@ -142,11 +138,9 @@ int mfc_cmd_abort_inst(struct mfc_ctx *ctx) MFC_WRITEL(ctx->inst_no, MFC_REG_INSTANCE_ID); mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_NAL_ABORT); - - return 0; } -int mfc_cmd_dpb_flush(struct mfc_ctx *ctx) +void mfc_cmd_dpb_flush(struct mfc_ctx *ctx) { struct mfc_dev *dev = ctx->dev; @@ -157,14 +151,119 @@ int mfc_cmd_dpb_flush(struct mfc_ctx *ctx) MFC_WRITEL(ctx->inst_no, MFC_REG_INSTANCE_ID); mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_DPB_FLUSH); - - return 0; } -int mfc_cmd_cache_flush(struct mfc_dev *dev) +void mfc_cmd_cache_flush(struct mfc_dev *dev) { mfc_clean_dev_int_flags(dev); mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_CACHE_FLUSH); +} + +/* Initialize decoding */ +void mfc_cmd_dec_seq_header(struct mfc_ctx *ctx) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_dec *dec = ctx->dec_priv; + unsigned int reg = 0; + int fmo_aso_ctrl = 0; + + mfc_debug_enter(); + + mfc_debug(2, "InstNo: %d/%d\n", ctx->inst_no, MFC_REG_H2R_CMD_SEQ_HEADER); + mfc_debug(2, "BUFs: %08x\n", MFC_READL(MFC_REG_D_CPB_BUFFER_ADDR)); + + /* + * When user sets desplay_delay to 0, + * It works as "display_delay enable" and delay set to 0. + * If user wants display_delay disable, It should be + * set to negative value. + */ + if (dec->display_delay >= 0) { + reg |= (0x1 << MFC_REG_D_DEC_OPT_DISPLAY_DELAY_EN_SHIFT); + MFC_WRITEL(dec->display_delay, MFC_REG_D_DISPLAY_DELAY); + } + + /* FMO_ASO_CTRL - 0: Enable, 1: Disable */ + reg |= ((fmo_aso_ctrl & MFC_REG_D_DEC_OPT_FMO_ASO_CTRL_MASK) + << MFC_REG_D_DEC_OPT_FMO_ASO_CTRL_SHIFT); + + reg |= ((dec->idr_decoding & MFC_REG_D_DEC_OPT_IDR_DECODING_MASK) + << MFC_REG_D_DEC_OPT_IDR_DECODING_SHIFT); + + /* VC1 RCV: Discard to parse additional header as default */ + if (IS_VC1_RCV_DEC(ctx)) + reg |= (0x1 << MFC_REG_D_DEC_OPT_DISCARD_RCV_HEADER_SHIFT); + + /* conceal control to specific color */ + reg |= (0x4 << MFC_REG_D_DEC_OPT_CONCEAL_CONTROL_SHIFT); + + /* Disable parallel processing if nal_q_parallel_disable was set */ + if (nal_q_parallel_disable) + reg |= (0x2 << MFC_REG_D_DEC_OPT_PARALLEL_DISABLE_SHIFT); + + /* Realloc buffer for resolution decrease case in NAL QUEUE mode */ + reg |= (0x1 << MFC_REG_D_DEC_OPT_REALLOC_CONTROL_SHIFT); + + /* Parsing all including PPS */ + reg |= (0x1 << MFC_REG_D_DEC_OPT_SPECIAL_PARSING_SHIFT); + + MFC_WRITEL(reg, MFC_REG_D_DEC_OPTIONS); + + MFC_WRITEL(MFC_CONCEAL_COLOR, MFC_REG_D_FORCE_PIXEL_VAL); + + if (IS_FIMV1_DEC(ctx)) { + mfc_debug(2, "Setting FIMV1 resolution to %dx%d\n", + ctx->img_width, ctx->img_height); + MFC_WRITEL(ctx->img_width, MFC_REG_D_SET_FRAME_WIDTH); + MFC_WRITEL(ctx->img_height, MFC_REG_D_SET_FRAME_HEIGHT); + } + + mfc_set_pixel_format(dev, ctx->dst_fmt->fourcc); + + reg = 0; + /* Enable realloc interface if SEI is enabled */ + if (dec->sei_parse) + reg |= (0x1 << MFC_REG_D_SEI_ENABLE_NEED_INIT_BUFFER_SHIFT); + if (MFC_FEATURE_SUPPORT(dev, dev->pdata->static_info_dec)) { + reg |= (0x1 << MFC_REG_D_SEI_ENABLE_CONTENT_LIGHT_SHIFT); + reg |= (0x1 << MFC_REG_D_SEI_ENABLE_MASTERING_DISPLAY_SHIFT); + } + reg |= (0x1 << MFC_REG_D_SEI_ENABLE_RECOVERY_PARSING_SHIFT); + + MFC_WRITEL(reg, MFC_REG_D_SEI_ENABLE); + mfc_debug(2, "SEI enable was set, 0x%x\n", MFC_READL(MFC_REG_D_SEI_ENABLE)); + + MFC_WRITEL(ctx->inst_no, MFC_REG_INSTANCE_ID); + + if (sfr_dump & MFC_DUMP_DEC_SEQ_START) + call_dop(dev, dump_regs, dev); + + mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_SEQ_HEADER); + + mfc_debug_leave(); +} + +int mfc_cmd_enc_seq_header(struct mfc_ctx *ctx) +{ + struct mfc_dev *dev = ctx->dev; + int ret; + + mfc_debug(2, "++\n"); + + ret = mfc_set_enc_params(ctx); + if (ret) { + mfc_debug(2, "fail to set enc params\n"); + return ret; + } + + MFC_WRITEL(ctx->inst_no, MFC_REG_INSTANCE_ID); + + if (sfr_dump & MFC_DUMP_ENC_SEQ_START) + call_dop(dev, dump_regs, dev); + + mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_SEQ_HEADER); + + mfc_debug(2, "--\n"); return 0; } @@ -294,93 +393,8 @@ int mfc_cmd_enc_init_buffers(struct mfc_ctx *ctx) return ret; } -/* Initialize decoding */ -int mfc_cmd_init_decode(struct mfc_ctx *ctx) -{ - struct mfc_dev *dev = ctx->dev; - struct mfc_dec *dec = ctx->dec_priv; - unsigned int reg = 0; - int fmo_aso_ctrl = 0; - - mfc_debug_enter(); - - mfc_debug(2, "InstNo: %d/%d\n", ctx->inst_no, MFC_REG_H2R_CMD_SEQ_HEADER); - mfc_debug(2, "BUFs: %08x\n", MFC_READL(MFC_REG_D_CPB_BUFFER_ADDR)); - - /* - * When user sets desplay_delay to 0, - * It works as "display_delay enable" and delay set to 0. - * If user wants display_delay disable, It should be - * set to negative value. - */ - if (dec->display_delay >= 0) { - reg |= (0x1 << MFC_REG_D_DEC_OPT_DISPLAY_DELAY_EN_SHIFT); - MFC_WRITEL(dec->display_delay, MFC_REG_D_DISPLAY_DELAY); - } - - /* FMO_ASO_CTRL - 0: Enable, 1: Disable */ - reg |= ((fmo_aso_ctrl & MFC_REG_D_DEC_OPT_FMO_ASO_CTRL_MASK) - << MFC_REG_D_DEC_OPT_FMO_ASO_CTRL_SHIFT); - - reg |= ((dec->idr_decoding & MFC_REG_D_DEC_OPT_IDR_DECODING_MASK) - << MFC_REG_D_DEC_OPT_IDR_DECODING_SHIFT); - - /* VC1 RCV: Discard to parse additional header as default */ - if (IS_VC1_RCV_DEC(ctx)) - reg |= (0x1 << MFC_REG_D_DEC_OPT_DISCARD_RCV_HEADER_SHIFT); - - /* conceal control to specific color */ - reg |= (0x4 << MFC_REG_D_DEC_OPT_CONCEAL_CONTROL_SHIFT); - - /* Disable parallel processing if nal_q_parallel_disable was set */ - if (nal_q_parallel_disable) - reg |= (0x2 << MFC_REG_D_DEC_OPT_PARALLEL_DISABLE_SHIFT); - - /* Realloc buffer for resolution decrease case in NAL QUEUE mode */ - reg |= (0x1 << MFC_REG_D_DEC_OPT_REALLOC_CONTROL_SHIFT); - - /* Parsing all including PPS */ - reg |= (0x1 << MFC_REG_D_DEC_OPT_SPECIAL_PARSING_SHIFT); - - MFC_WRITEL(reg, MFC_REG_D_DEC_OPTIONS); - - MFC_WRITEL(MFC_CONCEAL_COLOR, MFC_REG_D_FORCE_PIXEL_VAL); - - if (IS_FIMV1_DEC(ctx)) { - mfc_debug(2, "Setting FIMV1 resolution to %dx%d\n", - ctx->img_width, ctx->img_height); - MFC_WRITEL(ctx->img_width, MFC_REG_D_SET_FRAME_WIDTH); - MFC_WRITEL(ctx->img_height, MFC_REG_D_SET_FRAME_HEIGHT); - } - - mfc_set_pixel_format(dev, ctx->dst_fmt->fourcc); - - reg = 0; - /* Enable realloc interface if SEI is enabled */ - if (dec->sei_parse) - reg |= (0x1 << MFC_REG_D_SEI_ENABLE_NEED_INIT_BUFFER_SHIFT); - if (MFC_FEATURE_SUPPORT(dev, dev->pdata->static_info_dec)) { - reg |= (0x1 << MFC_REG_D_SEI_ENABLE_CONTENT_LIGHT_SHIFT); - reg |= (0x1 << MFC_REG_D_SEI_ENABLE_MASTERING_DISPLAY_SHIFT); - } - reg |= (0x1 << MFC_REG_D_SEI_ENABLE_RECOVERY_PARSING_SHIFT); - - MFC_WRITEL(reg, MFC_REG_D_SEI_ENABLE); - mfc_debug(2, "[HDR] SEI enable was set, 0x%x\n", MFC_READL(MFC_REG_D_SEI_ENABLE)); - - MFC_WRITEL(ctx->inst_no, MFC_REG_INSTANCE_ID); - - if (sfr_dump & MFC_DUMP_DEC_SEQ_START) - call_dop(dev, dump_regs, dev); - - mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_SEQ_HEADER); - - mfc_debug_leave(); - return 0; -} - /* Decode a single frame */ -int mfc_cmd_dec_one_frame(struct mfc_ctx *ctx, int last_frame) +void mfc_cmd_dec_one_frame(struct mfc_ctx *ctx, int last_frame) { struct mfc_dev *dev = ctx->dev; struct mfc_dec *dec = ctx->dec_priv; @@ -425,36 +439,10 @@ int mfc_cmd_dec_one_frame(struct mfc_ctx *ctx, int last_frame) } mfc_debug(2, "Decoding a usual frame\n"); - return 0; -} - -int mfc_cmd_init_encode(struct mfc_ctx *ctx) -{ - struct mfc_dev *dev = ctx->dev; - int ret; - - mfc_debug(2, "++\n"); - - ret = mfc_set_enc_params(ctx); - if (ret) { - mfc_debug(2, "fail to set enc params\n"); - return ret; - } - - MFC_WRITEL(ctx->inst_no, MFC_REG_INSTANCE_ID); - - if (sfr_dump & MFC_DUMP_ENC_SEQ_START) - call_dop(dev, dump_regs, dev); - - mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_SEQ_HEADER); - - mfc_debug(2, "--\n"); - - return 0; } /* Encode a single frame */ -int mfc_cmd_enc_one_frame(struct mfc_ctx *ctx, int last_frame) +void mfc_cmd_enc_one_frame(struct mfc_ctx *ctx, int last_frame) { struct mfc_dev *dev = ctx->dev; @@ -483,6 +471,4 @@ int mfc_cmd_enc_one_frame(struct mfc_ctx *ctx, int last_frame) } mfc_debug(2, "--\n"); - - return 0; } diff --git a/drivers/media/platform/exynos/mfc/mfc_cmd.h b/drivers/media/platform/exynos/mfc/mfc_cmd.h index 64407284a65f..7ed85ab7e0a6 100644 --- a/drivers/media/platform/exynos/mfc/mfc_cmd.h +++ b/drivers/media/platform/exynos/mfc/mfc_cmd.h @@ -15,25 +15,25 @@ #include "mfc_common.h" -int mfc_cmd_sys_init(struct mfc_dev *dev, +void mfc_cmd_sys_init(struct mfc_dev *dev, enum mfc_buf_usage_type buf_type); void mfc_cmd_sleep(struct mfc_dev *dev); void mfc_cmd_wakeup(struct mfc_dev *dev); -int mfc_cmd_open_inst(struct mfc_ctx *ctx); +void mfc_cmd_open_inst(struct mfc_ctx *ctx); int mfc_cmd_close_inst(struct mfc_ctx *ctx); -int mfc_cmd_abort_inst(struct mfc_ctx *ctx); +void mfc_cmd_abort_inst(struct mfc_ctx *ctx); -int mfc_cmd_dpb_flush(struct mfc_ctx *ctx); -int mfc_cmd_cache_flush(struct mfc_dev *dev); +void mfc_cmd_dpb_flush(struct mfc_ctx *ctx); +void mfc_cmd_cache_flush(struct mfc_dev *dev); + +void mfc_cmd_dec_seq_header(struct mfc_ctx *ctx); +int mfc_cmd_enc_seq_header(struct mfc_ctx *ctx); int mfc_cmd_dec_init_buffers(struct mfc_ctx *ctx); int mfc_cmd_enc_init_buffers(struct mfc_ctx *ctx); -int mfc_cmd_init_decode(struct mfc_ctx *ctx); -int mfc_cmd_dec_one_frame(struct mfc_ctx *ctx, int last_frame); - -int mfc_cmd_init_encode(struct mfc_ctx *ctx); -int mfc_cmd_enc_one_frame(struct mfc_ctx *ctx, int last_frame); +void mfc_cmd_dec_one_frame(struct mfc_ctx *ctx, int last_frame); +void mfc_cmd_enc_one_frame(struct mfc_ctx *ctx, int last_frame); #endif /* __MFC_CMD_H */ diff --git a/drivers/media/platform/exynos/mfc/mfc_hwlock.c b/drivers/media/platform/exynos/mfc/mfc_hwlock.c index 44a1fc999197..be90ff61076f 100644 --- a/drivers/media/platform/exynos/mfc/mfc_hwlock.c +++ b/drivers/media/platform/exynos/mfc/mfc_hwlock.c @@ -617,7 +617,7 @@ static int __mfc_just_run_dec(struct mfc_ctx *ctx) ret = mfc_run_dec_frame(ctx); break; case MFCINST_INIT: - ret = mfc_cmd_open_inst(ctx); + mfc_cmd_open_inst(ctx); break; case MFCINST_RETURN_INST: ret = mfc_cmd_close_inst(ctx); @@ -648,7 +648,7 @@ static int __mfc_just_run_dec(struct mfc_ctx *ctx) ret = mfc_run_dec_init(ctx); break; case MFCINST_DPB_FLUSHING: - ret = mfc_cmd_dpb_flush(ctx); + mfc_cmd_dpb_flush(ctx); break; default: mfc_info_ctx("can't try command(decoder just_run), state : %d\n", ctx->state); @@ -674,7 +674,7 @@ static int __mfc_just_run_enc(struct mfc_ctx *ctx) ret = mfc_run_enc_frame(ctx); break; case MFCINST_INIT: - ret = mfc_cmd_open_inst(ctx); + mfc_cmd_open_inst(ctx); break; case MFCINST_RETURN_INST: ret = mfc_cmd_close_inst(ctx); @@ -690,7 +690,7 @@ static int __mfc_just_run_enc(struct mfc_ctx *ctx) ret = mfc_cmd_enc_init_buffers(ctx); break; case MFCINST_ABORT_INST: - ret = mfc_cmd_abort_inst(ctx); + mfc_cmd_abort_inst(ctx); break; default: mfc_info_ctx("can't try command(encoder just_run), state : %d\n", ctx->state); diff --git a/drivers/media/platform/exynos/mfc/mfc_otf.c b/drivers/media/platform/exynos/mfc/mfc_otf.c index 033dc38fb253..29530f5dc25b 100644 --- a/drivers/media/platform/exynos/mfc/mfc_otf.c +++ b/drivers/media/platform/exynos/mfc/mfc_otf.c @@ -392,7 +392,7 @@ int mfc_otf_run_enc_init(struct mfc_ctx *ctx) mfc_set_enc_stride(ctx); mfc_clean_ctx_int_flags(ctx); - ret = mfc_cmd_init_encode(ctx); + ret = mfc_cmd_enc_seq_header(ctx); mfc_debug_leave(); diff --git a/drivers/media/platform/exynos/mfc/mfc_run.c b/drivers/media/platform/exynos/mfc/mfc_run.c index a882999473a5..cc1eb8f26f01 100644 --- a/drivers/media/platform/exynos/mfc/mfc_run.c +++ b/drivers/media/platform/exynos/mfc/mfc_run.c @@ -74,11 +74,7 @@ static int __mfc_init_hw(struct mfc_dev *dev, enum mfc_buf_usage_type buf_type) } /* 3. Initialize firmware */ - ret = mfc_cmd_sys_init(dev, buf_type); - if (ret) { - mfc_err_dev("Failed to send command to MFC - timeout\n"); - goto err_init_hw; - } + mfc_cmd_sys_init(dev, buf_type); mfc_debug(2, "Ok, now will write a command to init the system\n"); if (mfc_wait_for_done_dev(dev, MFC_REG_R2H_CMD_SYS_INIT_RET)) { @@ -349,7 +345,7 @@ int mfc_run_dec_init(struct mfc_ctx *ctx) mfc_debug(2, "[BUFINFO] Header addr: 0x%08llx\n", src_mb->addr[0][0]); mfc_clean_ctx_int_flags(ctx); - mfc_cmd_init_decode(ctx); + mfc_cmd_dec_seq_header(ctx); return 0; } @@ -495,7 +491,7 @@ int mfc_run_enc_init(struct mfc_ctx *ctx) mfc_debug(2, "[BUFINFO] Header addr: 0x%08llx\n", dst_mb->addr[0][0]); mfc_clean_ctx_int_flags(ctx); - ret = mfc_cmd_init_encode(ctx); + ret = mfc_cmd_enc_seq_header(ctx); return ret; }