From: David S. Miller Date: Wed, 29 Mar 2017 00:11:56 +0000 (-0700) Subject: Merge branch 'net-dpipe' X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=2a69ca71488bc77315575007ab2ab2d0cbc774f3;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git Merge branch 'net-dpipe' Jiri Pirko says: ==================== Add support for pipeline debug (dpipe) Arkadi says: While doing the hardware offloading process much of the hardware specifics cannot be presented. An example for such is the routing LPM algorithm which differ in hardware implementation from the kernel software implementation. The only information the user receives is whether specific route is offloaded or not, but he cannot really understand the underlying implementation nor get the specific statistics related to that process. Another example is ACL offload using TC which is commonly implemented using TCAM memory. Currently there is no capability to gain visibility into the TCAM structure and to debug suboptimal resource allocation. This patchset introduces capability for exporting the ASICs pipeline abstraction via devlink infrastructure, which should serve as an complementary tool. This infrastructure allows the user to get visibility into the ASIC by modeling it as a set of match/action tables. The main objects defined: Table - abstraction for a single pipeline stage. Contains the available match/actions and counter availability. Entry - entry in a specific table with specific matches/actions values and dedicated counter. Header/field - tuples which describes the tables behavior. As an example one of the ASIC's L3 blocks will be modeled. The egress rif (router interface) table is the final step in the L3 pipeline processing which does match on the internal rif index which was determined before by the routing logic. The erif table determines whether to forward or drop the packet and updates the corresponding rif L3 statistics. To expose this internal resources a special metadata header will be introduced that describes the internal information gathered by the ASIC's pipeline and contains the following fields: rif_port_index, forward and drop. Some internal hardware resources have direct mapping to kernel objects. For example the rif_port_index is mapped to the net-devices ifindex. By providing this mapping the users gains visibility into the offloading process. Follow-up work will include exporting more L3 tables which will give visibility into the routing process. First stage is adding support for dpipe in devlink. Next add support in spectrum driver. Finally implement egress router interface (erif) table for spectrum ASIC as an example. --- v1->v2: Please see individual patches ==================== Signed-off-by: David S. Miller --- 2a69ca71488bc77315575007ab2ab2d0cbc774f3