From: Matt Roper Date: Tue, 5 Apr 2016 21:37:19 +0000 (-0700) Subject: drm/i915/bxt: Set max cdclk frequency properly X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=281c114f8e80d3a86f18ccf7cb93460bad48fcbe;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git drm/i915/bxt: Set max cdclk frequency properly intel_update_max_cdclk() doesn't have a switch case for Broxton, so dev_priv->max_cdclk_freq gets set to whatever clock frequency we're currently running at (e.g., 144 MHz) rather than the true maximum. This causes our max dotclock to also be set too low and in turn leads mode verification to reject perfectly valid modes while loading EDID firmware blobs. Cc: Imre Deak Signed-off-by: Matt Roper Reviewed-by: Imre Deak Link: http://patchwork.freedesktop.org/patch/msgid/1459892239-14041-1-git-send-email-matthew.d.roper@intel.com --- diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index cb2d6af7a839..7635025af73e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5268,6 +5268,8 @@ static void intel_update_max_cdclk(struct drm_device *dev) dev_priv->max_cdclk_freq = 450000; else dev_priv->max_cdclk_freq = 337500; + } else if (IS_BROXTON(dev)) { + dev_priv->max_cdclk_freq = 624000; } else if (IS_BROADWELL(dev)) { /* * FIXME with extra cooling we can allow