From: Sunyoung Kang Date: Tue, 26 Jun 2018 04:44:45 +0000 (+0900) Subject: [COMMON] media: mfc: DRV4.0: remove "s5p" prefix in all files. X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=27e6823df73ac17e654c913e3927755cfa9d6c84;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git [COMMON] media: mfc: DRV4.0: remove "s5p" prefix in all files. The "s5p" prefix is no longer meaningful and removed. The function and register names have been modified as shown below. - normal function name: s5p_mfc_xxx => mfc_xxx - static function name: mfc_xxx => __mfc_xxx - register definition: S5P_FIMV_xxx => MFC_REG_xxx - structure name: s5p_mfc_xxx => mfc_xxx - macro name: S5P_MFC_xxx => MFC_xxx Change-Id: I0e8726af7c0f2d244c49e0166fcdbe1617b0a7c8 Signed-off-by: Sunyoung Kang --- diff --git a/drivers/media/platform/exynos/mfc/mfc.c b/drivers/media/platform/exynos/mfc/mfc.c index 7d1adfbf3c87..5aef071bd3eb 100644 --- a/drivers/media/platform/exynos/mfc/mfc.c +++ b/drivers/media/platform/exynos/mfc/mfc.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc.c + * drivers/media/platform/exynos/mfc/mfc.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -52,17 +52,17 @@ #define CREATE_TRACE_POINTS #include -#define S5P_MFC_NAME "s5p-mfc" -#define S5P_MFC_DEC_NAME "s5p-mfc-dec" -#define S5P_MFC_ENC_NAME "s5p-mfc-enc" -#define S5P_MFC_DEC_DRM_NAME "s5p-mfc-dec-secure" -#define S5P_MFC_ENC_DRM_NAME "s5p-mfc-enc-secure" -#define S5P_MFC_ENC_OTF_NAME "s5p-mfc-enc-otf" -#define S5P_MFC_ENC_OTF_DRM_NAME "s5p-mfc-enc-otf-secure" +#define MFC_NAME "s5p-mfc" +#define MFC_DEC_NAME "s5p-mfc-dec" +#define MFC_ENC_NAME "s5p-mfc-enc" +#define MFC_DEC_DRM_NAME "s5p-mfc-dec-secure" +#define MFC_ENC_DRM_NAME "s5p-mfc-enc-secure" +#define MFC_ENC_OTF_NAME "s5p-mfc-enc-otf" +#define MFC_ENC_OTF_DRM_NAME "s5p-mfc-enc-otf-secure" struct _mfc_trace g_mfc_trace[MFC_TRACE_COUNT_MAX]; struct _mfc_trace g_mfc_trace_hwlock[MFC_TRACE_COUNT_MAX]; -struct s5p_mfc_dev *g_mfc_dev; +struct mfc_dev *g_mfc_dev; #ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION static struct proc_dir_entry *mfc_proc_entry; @@ -79,41 +79,41 @@ static struct proc_dir_entry *mfc_proc_entry; #define DEF_ENC_SRC_FMT 5 #define DEF_ENC_DST_FMT 13 -void s5p_mfc_butler_worker(struct work_struct *work) +void mfc_butler_worker(struct work_struct *work) { - struct s5p_mfc_dev *dev; + struct mfc_dev *dev; - dev = container_of(work, struct s5p_mfc_dev, butler_work); + dev = container_of(work, struct mfc_dev, butler_work); - s5p_mfc_try_run(dev); + mfc_try_run(dev); } -extern struct s5p_mfc_ctrls_ops decoder_ctrls_ops; -extern struct vb2_ops s5p_mfc_dec_qops; -extern struct s5p_mfc_fmt dec_formats[]; +extern struct mfc_ctrls_ops decoder_ctrls_ops; +extern struct vb2_ops mfc_dec_qops; +extern struct mfc_fmt dec_formats[]; -static void mfc_deinit_dec_ctx(struct s5p_mfc_ctx *ctx) +static void __mfc_deinit_dec_ctx(struct mfc_ctx *ctx) { - struct s5p_mfc_dec *dec = ctx->dec_priv; + struct mfc_dec *dec = ctx->dec_priv; - s5p_mfc_delete_queue(&ctx->src_buf_queue); - s5p_mfc_delete_queue(&ctx->dst_buf_queue); - s5p_mfc_delete_queue(&ctx->src_buf_nal_queue); - s5p_mfc_delete_queue(&ctx->dst_buf_nal_queue); - s5p_mfc_delete_queue(&ctx->ref_buf_queue); + mfc_delete_queue(&ctx->src_buf_queue); + mfc_delete_queue(&ctx->dst_buf_queue); + mfc_delete_queue(&ctx->src_buf_nal_queue); + mfc_delete_queue(&ctx->dst_buf_nal_queue); + mfc_delete_queue(&ctx->ref_buf_queue); - s5p_mfc_mem_cleanup_user_shared_handle(ctx, &dec->sh_handle); + mfc_mem_cleanup_user_shared_handle(ctx, &dec->sh_handle); kfree(dec->ref_info); kfree(dec); } -static int mfc_init_dec_ctx(struct s5p_mfc_ctx *ctx) +static int __mfc_init_dec_ctx(struct mfc_ctx *ctx) { - struct s5p_mfc_dec *dec; + struct mfc_dec *dec; int ret = 0; int i; - dec = kzalloc(sizeof(struct s5p_mfc_dec), GFP_KERNEL); + dec = kzalloc(sizeof(struct mfc_dec), GFP_KERNEL); if (!dec) { mfc_err_dev("failed to allocate decoder private data\n"); return -ENOMEM; @@ -122,11 +122,11 @@ static int mfc_init_dec_ctx(struct s5p_mfc_ctx *ctx) ctx->inst_no = MFC_NO_INSTANCE_SET; - s5p_mfc_create_queue(&ctx->src_buf_queue); - s5p_mfc_create_queue(&ctx->dst_buf_queue); - s5p_mfc_create_queue(&ctx->src_buf_nal_queue); - s5p_mfc_create_queue(&ctx->dst_buf_nal_queue); - s5p_mfc_create_queue(&ctx->ref_buf_queue); + mfc_create_queue(&ctx->src_buf_queue); + mfc_create_queue(&ctx->dst_buf_queue); + mfc_create_queue(&ctx->src_buf_nal_queue); + mfc_create_queue(&ctx->dst_buf_nal_queue); + mfc_create_queue(&ctx->ref_buf_queue); for (i = 0; i < MFC_MAX_BUFFERS; i++) { INIT_LIST_HEAD(&ctx->src_ctrls[i]); @@ -138,13 +138,13 @@ static int mfc_init_dec_ctx(struct s5p_mfc_ctx *ctx) ctx->capture_state = QUEUE_FREE; ctx->output_state = QUEUE_FREE; - s5p_mfc_change_state(ctx, MFCINST_INIT); + mfc_change_state(ctx, MFCINST_INIT); ctx->type = MFCINST_DECODER; ctx->c_ops = &decoder_ctrls_ops; ctx->src_fmt = &dec_formats[DEF_DEC_SRC_FMT]; ctx->dst_fmt = &dec_formats[DEF_DEC_DST_FMT]; - s5p_mfc_qos_reset_framerate(ctx); + mfc_qos_reset_framerate(ctx); ctx->qos_ratio = 100; #ifdef CONFIG_MFC_USE_BUS_DEVFREQ @@ -162,8 +162,8 @@ static int mfc_init_dec_ctx(struct s5p_mfc_ctx *ctx) dec->is_dynamic_dpb = 1; dec->dynamic_used = 0; dec->is_dpb_full = 0; - s5p_mfc_cleanup_assigned_fd(ctx); - s5p_mfc_clear_assigned_dpb(ctx); + mfc_cleanup_assigned_fd(ctx); + mfc_clear_assigned_dpb(ctx); dec->sh_handle.fd = -1; dec->ref_info = kzalloc( (sizeof(struct dec_dpb_ref_info) * MFC_MAX_DPBS), GFP_KERNEL); @@ -178,10 +178,10 @@ static int mfc_init_dec_ctx(struct s5p_mfc_ctx *ctx) /* Init videobuf2 queue for OUTPUT */ ctx->vq_src.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; ctx->vq_src.drv_priv = ctx; - ctx->vq_src.buf_struct_size = sizeof(struct s5p_mfc_buf); + ctx->vq_src.buf_struct_size = sizeof(struct mfc_buf); ctx->vq_src.io_modes = VB2_USERPTR | VB2_DMABUF; - ctx->vq_src.ops = &s5p_mfc_dec_qops; - ctx->vq_src.mem_ops = s5p_mfc_mem_ops(); + ctx->vq_src.ops = &mfc_dec_qops; + ctx->vq_src.mem_ops = mfc_mem_ops(); ctx->vq_src.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ret = vb2_queue_init(&ctx->vq_src); if (ret) { @@ -191,10 +191,10 @@ static int mfc_init_dec_ctx(struct s5p_mfc_ctx *ctx) /* Init videobuf2 queue for CAPTURE */ ctx->vq_dst.type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; ctx->vq_dst.drv_priv = ctx; - ctx->vq_dst.buf_struct_size = sizeof(struct s5p_mfc_buf); + ctx->vq_dst.buf_struct_size = sizeof(struct mfc_buf); ctx->vq_dst.io_modes = VB2_USERPTR | VB2_DMABUF; - ctx->vq_dst.ops = &s5p_mfc_dec_qops; - ctx->vq_dst.mem_ops = s5p_mfc_mem_ops(); + ctx->vq_dst.ops = &mfc_dec_qops; + ctx->vq_dst.mem_ops = mfc_mem_ops(); ctx->vq_dst.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ret = vb2_queue_init(&ctx->vq_dst); if (ret) { @@ -205,38 +205,38 @@ static int mfc_init_dec_ctx(struct s5p_mfc_ctx *ctx) return ret; fail_dec_init: - mfc_deinit_dec_ctx(ctx); + __mfc_deinit_dec_ctx(ctx); return ret; } -extern struct s5p_mfc_ctrls_ops encoder_ctrls_ops; -extern struct vb2_ops s5p_mfc_enc_qops; -extern struct s5p_mfc_fmt enc_formats[]; +extern struct mfc_ctrls_ops encoder_ctrls_ops; +extern struct vb2_ops mfc_enc_qops; +extern struct mfc_fmt enc_formats[]; -static void mfc_deinit_enc_ctx(struct s5p_mfc_ctx *ctx) +static void __mfc_deinit_enc_ctx(struct mfc_ctx *ctx) { - struct s5p_mfc_enc *enc = ctx->enc_priv; + struct mfc_enc *enc = ctx->enc_priv; - s5p_mfc_delete_queue(&ctx->src_buf_queue); - s5p_mfc_delete_queue(&ctx->dst_buf_queue); - s5p_mfc_delete_queue(&ctx->src_buf_nal_queue); - s5p_mfc_delete_queue(&ctx->dst_buf_nal_queue); - s5p_mfc_delete_queue(&ctx->ref_buf_queue); + mfc_delete_queue(&ctx->src_buf_queue); + mfc_delete_queue(&ctx->dst_buf_queue); + mfc_delete_queue(&ctx->src_buf_nal_queue); + mfc_delete_queue(&ctx->dst_buf_nal_queue); + mfc_delete_queue(&ctx->ref_buf_queue); - s5p_mfc_mem_cleanup_user_shared_handle(ctx, &enc->sh_handle_svc); - s5p_mfc_mem_cleanup_user_shared_handle(ctx, &enc->sh_handle_roi); - s5p_mfc_release_enc_roi_buffer(ctx); + mfc_mem_cleanup_user_shared_handle(ctx, &enc->sh_handle_svc); + mfc_mem_cleanup_user_shared_handle(ctx, &enc->sh_handle_roi); + mfc_release_enc_roi_buffer(ctx); kfree(enc); } -static int mfc_init_enc_ctx(struct s5p_mfc_ctx *ctx) +static int __mfc_init_enc_ctx(struct mfc_ctx *ctx) { - struct s5p_mfc_enc *enc; - struct s5p_mfc_enc_params *p; + struct mfc_enc *enc; + struct mfc_enc_params *p; int ret = 0; int i; - enc = kzalloc(sizeof(struct s5p_mfc_enc), GFP_KERNEL); + enc = kzalloc(sizeof(struct mfc_enc), GFP_KERNEL); if (!enc) { mfc_err_dev("failed to allocate encoder private data\n"); return -ENOMEM; @@ -245,11 +245,11 @@ static int mfc_init_enc_ctx(struct s5p_mfc_ctx *ctx) ctx->inst_no = MFC_NO_INSTANCE_SET; - s5p_mfc_create_queue(&ctx->src_buf_queue); - s5p_mfc_create_queue(&ctx->dst_buf_queue); - s5p_mfc_create_queue(&ctx->src_buf_nal_queue); - s5p_mfc_create_queue(&ctx->dst_buf_nal_queue); - s5p_mfc_create_queue(&ctx->ref_buf_queue); + mfc_create_queue(&ctx->src_buf_queue); + mfc_create_queue(&ctx->dst_buf_queue); + mfc_create_queue(&ctx->src_buf_nal_queue); + mfc_create_queue(&ctx->dst_buf_nal_queue); + mfc_create_queue(&ctx->ref_buf_queue); for (i = 0; i < MFC_MAX_BUFFERS; i++) { INIT_LIST_HEAD(&ctx->src_ctrls[i]); @@ -263,7 +263,7 @@ static int mfc_init_enc_ctx(struct s5p_mfc_ctx *ctx) ctx->src_fmt = &enc_formats[DEF_ENC_SRC_FMT]; ctx->dst_fmt = &enc_formats[DEF_ENC_DST_FMT]; - s5p_mfc_qos_reset_framerate(ctx); + mfc_qos_reset_framerate(ctx); ctx->qos_ratio = 100; @@ -282,10 +282,10 @@ static int mfc_init_enc_ctx(struct s5p_mfc_ctx *ctx) /* Init videobuf2 queue for OUTPUT */ ctx->vq_src.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; ctx->vq_src.drv_priv = ctx; - ctx->vq_src.buf_struct_size = sizeof(struct s5p_mfc_buf); + ctx->vq_src.buf_struct_size = sizeof(struct mfc_buf); ctx->vq_src.io_modes = VB2_USERPTR | VB2_DMABUF; - ctx->vq_src.ops = &s5p_mfc_enc_qops; - ctx->vq_src.mem_ops = s5p_mfc_mem_ops(); + ctx->vq_src.ops = &mfc_enc_qops; + ctx->vq_src.mem_ops = mfc_mem_ops(); ctx->vq_src.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ret = vb2_queue_init(&ctx->vq_src); if (ret) { @@ -296,10 +296,10 @@ static int mfc_init_enc_ctx(struct s5p_mfc_ctx *ctx) /* Init videobuf2 queue for CAPTURE */ ctx->vq_dst.type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; ctx->vq_dst.drv_priv = ctx; - ctx->vq_dst.buf_struct_size = sizeof(struct s5p_mfc_buf); + ctx->vq_dst.buf_struct_size = sizeof(struct mfc_buf); ctx->vq_dst.io_modes = VB2_USERPTR | VB2_DMABUF; - ctx->vq_dst.ops = &s5p_mfc_enc_qops; - ctx->vq_dst.mem_ops = s5p_mfc_mem_ops(); + ctx->vq_dst.ops = &mfc_enc_qops; + ctx->vq_dst.mem_ops = mfc_mem_ops(); ctx->vq_dst.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ret = vb2_queue_init(&ctx->vq_dst); if (ret) { @@ -310,11 +310,11 @@ static int mfc_init_enc_ctx(struct s5p_mfc_ctx *ctx) return 0; fail_enc_init: - mfc_deinit_enc_ctx(ctx); + __mfc_deinit_enc_ctx(ctx); return 0; } -static int mfc_init_instance(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx) +static int __mfc_init_instance(struct mfc_dev *dev, struct mfc_ctx *ctx) { int ret = 0; @@ -324,13 +324,13 @@ static int mfc_init_instance(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx) /* Load the FW */ if (!dev->fw.status) { - ret = s5p_mfc_alloc_firmware(dev); + ret = mfc_alloc_firmware(dev); if (ret) goto err_fw_alloc; dev->fw.status = 1; } - ret = s5p_mfc_load_firmware(dev); + ret = mfc_load_firmware(dev); if (ret) goto err_fw_load; @@ -354,15 +354,15 @@ static int mfc_init_instance(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx) #endif trace_mfc_dcpp_end(ctx->num, 1, dev->fw.drm_status); - ret = s5p_mfc_alloc_common_context(dev); + ret = mfc_alloc_common_context(dev); if (ret) goto err_context_alloc; if (dbg_enable) - s5p_mfc_alloc_dbg_info_buffer(dev); + mfc_alloc_dbg_info_buffer(dev); MFC_TRACE_DEV_HWLOCK("**open\n"); - ret = s5p_mfc_get_hwlock_dev(dev); + ret = mfc_get_hwlock_dev(dev); if (ret < 0) { mfc_err_dev("Failed to get hwlock\n"); mfc_err_dev("dev.hwlock.dev = 0x%lx, bits = 0x%lx, owned_by_irq = %d, wl_count = %d, transfer_owner = %d\n", @@ -372,7 +372,7 @@ static int mfc_init_instance(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx) } mfc_debug(2, "power on\n"); - ret = s5p_mfc_pm_power_on(dev); + ret = mfc_pm_power_on(dev); if (ret < 0) { mfc_err_ctx("power on failed\n"); goto err_pwr_enable; @@ -382,20 +382,20 @@ static int mfc_init_instance(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx) dev->preempt_ctx = MFC_NO_INSTANCE_SET; dev->curr_ctx_is_drm = ctx->is_drm; - ret = s5p_mfc_init_hw(dev); + ret = mfc_init_hw(dev); if (ret) { mfc_err_ctx("Failed to init mfc h/w\n"); goto err_hw_init; } if (dev->has_mmcache && (dev->mmcache.is_on_status == 0)) - s5p_mfc_mmcache_enable(dev); + mfc_mmcache_enable(dev); - s5p_mfc_release_hwlock_dev(dev); + mfc_release_hwlock_dev(dev); if (MFC_FEATURE_SUPPORT(dev, dev->pdata->nal_q)) { - dev->nal_q_handle = s5p_mfc_nal_q_create(dev); + dev->nal_q_handle = mfc_nal_q_create(dev); if (dev->nal_q_handle == NULL) mfc_err_dev("[NALQ] Can't create nal q\n"); } @@ -403,13 +403,13 @@ static int mfc_init_instance(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx) return ret; err_hw_init: - s5p_mfc_pm_power_off(dev); + mfc_pm_power_off(dev); err_pwr_enable: - s5p_mfc_release_hwlock_dev(dev); + mfc_release_hwlock_dev(dev); err_hw_lock: - s5p_mfc_release_common_context(dev); + mfc_release_common_context(dev); err_context_alloc: #ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION @@ -435,12 +435,12 @@ err_fw_alloc: } /* Open an MFC node */ -static int s5p_mfc_open(struct file *file) +static int mfc_open(struct file *file) { - struct s5p_mfc_ctx *ctx = NULL; - struct s5p_mfc_dev *dev = video_drvdata(file); + struct mfc_ctx *ctx = NULL; + struct mfc_dev *dev = video_drvdata(file); int ret = 0; - enum s5p_mfc_node_type node; + enum mfc_node_type node; struct video_device *vdev = NULL; mfc_debug(2, "mfc driver open called\n"); @@ -453,7 +453,7 @@ static int s5p_mfc_open(struct file *file) if (mutex_lock_interruptible(&dev->mfc_mutex)) return -ERESTARTSYS; - node = s5p_mfc_get_node_type(file); + node = mfc_get_node_type(file); if (node == MFCNODE_INVALID) { mfc_err_dev("cannot specify node type\n"); ret = -ENOENT; @@ -515,13 +515,13 @@ static int s5p_mfc_open(struct file *file) } init_waitqueue_head(&ctx->cmd_wq); - s5p_mfc_init_listable_wq_ctx(ctx); + mfc_init_listable_wq_ctx(ctx); spin_lock_init(&ctx->buf_queue_lock); - if (s5p_mfc_is_decoder_node(node)) - ret = mfc_init_dec_ctx(ctx); + if (mfc_is_decoder_node(node)) + ret = __mfc_init_dec_ctx(ctx); else - ret = mfc_init_enc_ctx(ctx); + ret = __mfc_init_enc_ctx(ctx); if (ret) goto err_ctx_init; @@ -532,7 +532,7 @@ static int s5p_mfc_open(struct file *file) } #ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION - if (s5p_mfc_is_drm_node(node)) { + if (mfc_is_drm_node(node)) { if (dev->num_drm_inst < MFC_MAX_DRM_CTX) { if (ctx->raw_protect_flag || ctx->stream_protect_flag) { mfc_err_ctx("protect_flag(%#lx/%#lx) remained\n", @@ -558,28 +558,28 @@ static int s5p_mfc_open(struct file *file) #endif /* Mark context as idle */ - s5p_mfc_clear_bit(ctx->num, &dev->work_bits); + mfc_clear_bit(ctx->num, &dev->work_bits); dev->ctx[ctx->num] = ctx; /* Load firmware if this is the first instance */ if (dev->num_inst == 1) { - ret = mfc_init_instance(dev, ctx); + ret = __mfc_init_instance(dev, ctx); if (ret) goto err_init_inst; if (perf_boost_mode) - s5p_mfc_perf_boost_enable(dev); + mfc_perf_boost_enable(dev); } #ifdef CONFIG_VIDEO_EXYNOS_REPEATER - if (s5p_mfc_is_encoder_otf_node(node)) { - ret = s5p_mfc_otf_create(ctx); + if (mfc_is_encoder_otf_node(node)) { + ret = mfc_otf_create(ctx); if (ret) mfc_err_ctx("[OTF] otf_create failed\n"); } #endif - s5p_mfc_perf_init(dev); + mfc_perf_init(dev); trace_mfc_node_open(ctx->num, dev->num_inst, ctx->type, ctx->is_drm); mfc_info_ctx("MFC open completed [%d:%d] dev = 0x%p, ctx = 0x%p, version = %d\n", dev->num_drm_inst, dev->num_inst, dev, ctx, MFC_DRIVER_INFO); @@ -620,7 +620,7 @@ err_no_device: return ret; } -static int mfc_wait_close_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx) +static int __mfc_wait_close_inst(struct mfc_dev *dev, struct mfc_ctx *ctx) { if (atomic_read(&dev->watchdog_run)) { mfc_err_ctx("watchdog already running!\n"); @@ -632,22 +632,22 @@ static int mfc_wait_close_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx) return 0; } - s5p_mfc_clean_ctx_int_flags(ctx); - s5p_mfc_change_state(ctx, MFCINST_RETURN_INST); - s5p_mfc_set_bit(ctx->num, &dev->work_bits); + mfc_clean_ctx_int_flags(ctx); + mfc_change_state(ctx, MFCINST_RETURN_INST); + mfc_set_bit(ctx->num, &dev->work_bits); /* To issue the command 'CLOSE_INSTANCE' */ - if (s5p_mfc_just_run(dev, ctx->num)) { + if (mfc_just_run(dev, ctx->num)) { mfc_err_ctx("Failed to run MFC\n"); return -EIO; } /* Wait until instance is returned or timeout occured */ - if (s5p_mfc_wait_for_done_ctx(ctx, - S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET) == 1) { + if (mfc_wait_for_done_ctx(ctx, + MFC_REG_R2H_CMD_CLOSE_INSTANCE_RET) == 1) { mfc_err_ctx("Waiting for CLOSE_INSTANCE timed out\n"); - if (s5p_mfc_wait_for_done_ctx(ctx, - S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET)) { + if (mfc_wait_for_done_ctx(ctx, + MFC_REG_R2H_CMD_CLOSE_INSTANCE_RET)) { mfc_err_ctx("waiting once more but timed out\n"); dev->logging_data->cause |= (1 << MFC_CAUSE_FAIL_CLOSE_INST); call_dop(dev, dump_and_stop_always, dev); @@ -660,10 +660,10 @@ static int mfc_wait_close_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx) } /* Release MFC context */ -static int s5p_mfc_release(struct file *file) +static int mfc_release(struct file *file) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); - struct s5p_mfc_dev *dev = NULL; + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_dev *dev = NULL; int ret = 0; dev = ctx->dev; @@ -677,17 +677,17 @@ static int s5p_mfc_release(struct file *file) mfc_info_ctx("MFC driver release is called [%d:%d], is_drm(%d)\n", dev->num_drm_inst, dev->num_inst, ctx->is_drm); - s5p_mfc_clear_bit(ctx->num, &dev->work_bits); + mfc_clear_bit(ctx->num, &dev->work_bits); /* If a H/W operation is in progress, wait for it complete */ if (need_to_wait_nal_abort(ctx)) { - if (s5p_mfc_wait_for_done_ctx(ctx, S5P_FIMV_R2H_CMD_NAL_ABORT_RET)) { + if (mfc_wait_for_done_ctx(ctx, MFC_REG_R2H_CMD_NAL_ABORT_RET)) { mfc_err_ctx("Failed to wait nal abort\n"); - s5p_mfc_cleanup_work_bit_and_try_run(ctx); + mfc_cleanup_work_bit_and_try_run(ctx); } } MFC_TRACE_CTX_HWLOCK("**release\n"); - ret = s5p_mfc_get_hwlock_ctx(ctx); + ret = mfc_get_hwlock_ctx(ctx); if (ret < 0) { mfc_err_dev("Failed to get hwlock\n"); mutex_unlock(&dev->mfc_mutex); @@ -701,11 +701,11 @@ static int s5p_mfc_release(struct file *file) v4l2_fh_exit(&ctx->fh); /* Mark context as idle */ - s5p_mfc_clear_bit(ctx->num, &dev->work_bits); + mfc_clear_bit(ctx->num, &dev->work_bits); /* If instance was initialised then * return instance and free reosurces */ - ret = mfc_wait_close_inst(dev, ctx); + ret = __mfc_wait_close_inst(dev, ctx); if (ret) goto err_release_try; @@ -714,22 +714,22 @@ static int s5p_mfc_release(struct file *file) dev->num_inst--; if (dev->num_inst == 0) { - s5p_mfc_deinit_hw(dev); + mfc_deinit_hw(dev); if (perf_boost_mode) - s5p_mfc_perf_boost_disable(dev); + mfc_perf_boost_disable(dev); del_timer_sync(&dev->watchdog_timer); flush_workqueue(dev->butler_wq); mfc_debug(2, "power off\n"); - s5p_mfc_pm_power_off(dev); + mfc_pm_power_off(dev); if (dbg_enable) - s5p_mfc_release_dbg_info_buffer(dev); + mfc_release_dbg_info_buffer(dev); - s5p_mfc_release_common_context(dev); + mfc_release_common_context(dev); #ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION if (dev->fw.drm_status) { @@ -746,7 +746,7 @@ static int s5p_mfc_release(struct file *file) #endif if (dev->nal_q_handle) { - ret = s5p_mfc_nal_q_destroy(dev, dev->nal_q_handle); + ret = mfc_nal_q_destroy(dev, dev->nal_q_handle); if (ret) { mfc_err_ctx("failed nal_q destroy\n"); goto err_release; @@ -754,71 +754,71 @@ static int s5p_mfc_release(struct file *file) } } - s5p_mfc_qos_off(ctx); + mfc_qos_off(ctx); if (dev->has_mmcache && dev->mmcache.is_on_status) { - s5p_mfc_invalidate_mmcache(dev); + mfc_invalidate_mmcache(dev); if (dev->num_inst == 0) - s5p_mfc_mmcache_disable(dev); + mfc_mmcache_disable(dev); } - s5p_mfc_release_codec_buffers(ctx); - s5p_mfc_release_instance_context(ctx); + mfc_release_codec_buffers(ctx); + mfc_release_instance_context(ctx); - s5p_mfc_release_hwlock_ctx(ctx); + mfc_release_hwlock_ctx(ctx); /* Free resources */ vb2_queue_release(&ctx->vq_src); vb2_queue_release(&ctx->vq_dst); if (ctx->type == MFCINST_DECODER) - mfc_deinit_dec_ctx(ctx); + __mfc_deinit_dec_ctx(ctx); else if (ctx->type == MFCINST_ENCODER) - mfc_deinit_enc_ctx(ctx); + __mfc_deinit_enc_ctx(ctx); #ifdef CONFIG_VIDEO_EXYNOS_REPEATER if (ctx->otf_handle) { - s5p_mfc_otf_deinit(ctx); - s5p_mfc_otf_destroy(ctx); + mfc_otf_deinit(ctx); + mfc_otf_destroy(ctx); } #endif - s5p_mfc_destroy_listable_wq_ctx(ctx); + mfc_destroy_listable_wq_ctx(ctx); trace_mfc_node_close(ctx->num, dev->num_inst, ctx->type, ctx->is_drm); dev->ctx[ctx->num] = 0; kfree(ctx); - s5p_mfc_perf_print(); + mfc_perf_print(); mfc_info_dev("mfc driver release finished [%d:%d], dev = 0x%p\n", dev->num_drm_inst, dev->num_inst, dev); - if (s5p_mfc_is_work_to_do(dev)) + if (mfc_is_work_to_do(dev)) queue_work(dev->butler_wq, &dev->butler_work); mutex_unlock(&dev->mfc_mutex); return ret; err_release: - s5p_mfc_release_hwlock_ctx(ctx); + mfc_release_hwlock_ctx(ctx); mutex_unlock(&dev->mfc_mutex); return ret; err_release_try: - s5p_mfc_release_hwlock_ctx(ctx); - s5p_mfc_cleanup_work_bit_and_try_run(ctx); + mfc_release_hwlock_ctx(ctx); + mfc_cleanup_work_bit_and_try_run(ctx); mutex_unlock(&dev->mfc_mutex); return ret; } /* Poll */ -static unsigned int s5p_mfc_poll(struct file *file, +static unsigned int mfc_poll(struct file *file, struct poll_table_struct *wait) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); unsigned long req_events = poll_requested_events(wait); unsigned int ret = 0; @@ -837,9 +837,9 @@ static unsigned int s5p_mfc_poll(struct file *file, } /* Mmap */ -static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma) +static int mfc_mmap(struct file *file, struct vm_area_struct *vma) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; int ret; @@ -858,18 +858,18 @@ static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma) } /* v4l2 ops */ -static const struct v4l2_file_operations s5p_mfc_fops = { +static const struct v4l2_file_operations mfc_fops = { .owner = THIS_MODULE, - .open = s5p_mfc_open, - .release = s5p_mfc_release, - .poll = s5p_mfc_poll, + .open = mfc_open, + .release = mfc_release, + .poll = mfc_poll, .unlocked_ioctl = video_ioctl2, - .mmap = s5p_mfc_mmap, + .mmap = mfc_mmap, }; #ifdef CONFIG_MFC_USE_BUS_DEVFREQ -static int mfc_parse_mfc_qos_platdata(struct device_node *np, char *node_name, - struct s5p_mfc_qos *qosdata) +static int __mfc_parse_mfc_qos_platdata(struct device_node *np, char *node_name, + struct mfc_qos *qosdata) { int ret = 0; struct device_node *np_qos; @@ -894,12 +894,12 @@ static int mfc_parse_mfc_qos_platdata(struct device_node *np, char *node_name, } #endif -int s5p_mfc_sysmmu_fault_handler(struct iommu_domain *iodmn, struct device *device, +int mfc_sysmmu_fault_handler(struct iommu_domain *iodmn, struct device *device, unsigned long addr, int id, void *param) { - struct s5p_mfc_dev *dev; + struct mfc_dev *dev; - dev = (struct s5p_mfc_dev *)param; + dev = (struct mfc_dev *)param; /* [OTF] If AxID is 1 in SYSMMU1 fault info, it is TS-MUX fault */ if (dev->has_hwfc && dev->has_2sysmmu) { @@ -946,9 +946,9 @@ int s5p_mfc_sysmmu_fault_handler(struct iommu_domain *iodmn, struct device *devi return 0; } -static void mfc_parse_dt(struct device_node *np, struct s5p_mfc_dev *mfc) +static void __mfc_parse_dt(struct device_node *np, struct mfc_dev *mfc) { - struct s5p_mfc_platdata *pdata = mfc->pdata; + struct mfc_platdata *pdata = mfc->pdata; #ifdef CONFIG_MFC_USE_BUS_DEVFREQ struct device_node *np_qos; char node_name[50]; @@ -1005,16 +1005,16 @@ static void mfc_parse_dt(struct device_node *np, struct s5p_mfc_dev *mfc) of_property_read_u32(np, "bw_control", &pdata->bw_control); pdata->qos_table = devm_kzalloc(mfc->device, - sizeof(struct s5p_mfc_qos) * pdata->max_qos_steps, GFP_KERNEL); + sizeof(struct mfc_qos) * pdata->max_qos_steps, GFP_KERNEL); for (i = 0; i < pdata->max_qos_steps; i++) { snprintf(node_name, sizeof(node_name), "mfc_qos_variant_%d", i); - mfc_parse_mfc_qos_platdata(np, node_name, &pdata->qos_table[i]); + __mfc_parse_mfc_qos_platdata(np, node_name, &pdata->qos_table[i]); } /* performance boost mode */ pdata->qos_boost_table = devm_kzalloc(mfc->device, - sizeof(struct s5p_mfc_qos_boost), GFP_KERNEL); + sizeof(struct mfc_qos_boost), GFP_KERNEL); np_qos = of_find_node_by_name(np, "mfc_perf_boost_table"); if (!np_qos) { pr_err("%s:[QoS] could not find mfc_perf_boost_table node\n", node_name); @@ -1029,9 +1029,9 @@ static void mfc_parse_dt(struct device_node *np, struct s5p_mfc_dev *mfc) #endif } -static void *mfc_get_drv_data(struct platform_device *pdev); +static void *__mfc_get_drv_data(struct platform_device *pdev); -static struct video_device *mfc_video_device_register(struct s5p_mfc_dev *dev, +static struct video_device *__mfc_video_device_register(struct mfc_dev *dev, char *name, int node_num) { struct video_device *vfd; @@ -1043,14 +1043,14 @@ static struct video_device *mfc_video_device_register(struct s5p_mfc_dev *dev, return NULL; } strncpy(vfd->name, name, sizeof(vfd->name) - 1); - vfd->fops = &s5p_mfc_fops; + vfd->fops = &mfc_fops; vfd->minor = -1; vfd->release = video_device_release; if (IS_DEC_NODE(node_num)) - vfd->ioctl_ops = s5p_mfc_get_dec_v4l2_ioctl_ops(); + vfd->ioctl_ops = mfc_get_dec_v4l2_ioctl_ops(); else if(IS_ENC_NODE(node_num)) - vfd->ioctl_ops = s5p_mfc_get_enc_v4l2_ioctl_ops(); + vfd->ioctl_ops = mfc_get_enc_v4l2_ioctl_ops(); vfd->lock = &dev->mfc_mutex; vfd->v4l2_dev = &dev->v4l2_dev; @@ -1071,7 +1071,7 @@ static struct video_device *mfc_video_device_register(struct s5p_mfc_dev *dev, return vfd; } -static int mfc_register_resource(struct platform_device *pdev, struct s5p_mfc_dev *dev) +static int __mfc_register_resource(struct platform_device *pdev, struct mfc_dev *dev) { struct device_node *np = dev->device->of_node; struct device_node *iommu; @@ -1080,7 +1080,7 @@ static int mfc_register_resource(struct platform_device *pdev, struct s5p_mfc_de struct resource *res; int ret; - s5p_mfc_perf_register(dev); + mfc_perf_register(dev); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (res == NULL) { @@ -1147,7 +1147,7 @@ static int mfc_register_resource(struct platform_device *pdev, struct s5p_mfc_de goto err_res_irq; } dev->irq = res->start; - ret = request_threaded_irq(dev->irq, s5p_mfc_top_half_irq, s5p_mfc_irq, + ret = request_threaded_irq(dev->irq, mfc_top_half_irq, mfc_irq, IRQF_ONESHOT, pdev->name, dev); if (ret != 0) { dev_err(&pdev->dev, "failed to install irq (%d)\n", ret); @@ -1174,13 +1174,13 @@ err_ioremap: } #ifdef CONFIG_EXYNOS_ITMON -static int mfc_itmon_notifier(struct notifier_block *nb, unsigned long action, void *nb_data) +static int __mfc_itmon_notifier(struct notifier_block *nb, unsigned long action, void *nb_data) { - struct s5p_mfc_dev *dev; + struct mfc_dev *dev; struct itmon_notifier *itmon_info = nb_data; int is_mfc_itmon = 0, is_master = 0; - dev = container_of(nb, struct s5p_mfc_dev, itmon_nb); + dev = container_of(nb, struct mfc_dev, itmon_nb); if (IS_ERR_OR_NULL(itmon_info)) return NOTIFY_DONE; @@ -1218,16 +1218,16 @@ static int mfc_itmon_notifier(struct notifier_block *nb, unsigned long action, v #endif /* MFC probe function */ -static int s5p_mfc_probe(struct platform_device *pdev) +static int mfc_probe(struct platform_device *pdev) { - struct s5p_mfc_dev *dev; + struct mfc_dev *dev; int ret = -ENOENT; #ifdef CONFIG_MFC_USE_BUS_DEVFREQ int i; #endif dev_dbg(&pdev->dev, "%s()\n", __func__); - dev = devm_kzalloc(&pdev->dev, sizeof(struct s5p_mfc_dev), GFP_KERNEL); + dev = devm_kzalloc(&pdev->dev, sizeof(struct mfc_dev), GFP_KERNEL); if (!dev) { dev_err(&pdev->dev, "Not enough memory for MFC device\n"); return -ENOMEM; @@ -1236,7 +1236,7 @@ static int s5p_mfc_probe(struct platform_device *pdev) dev->device = &pdev->dev; dev->pdata = pdev->dev.platform_data; - dev->variant = mfc_get_drv_data(pdev); + dev->variant = __mfc_get_drv_data(pdev); if (dev->device->of_node) dev->id = of_alias_get_id(pdev->dev.of_node, "mfc"); @@ -1249,14 +1249,14 @@ static int s5p_mfc_probe(struct platform_device *pdev) goto err_pm; } - dev->pdata = devm_kzalloc(&pdev->dev, sizeof(struct s5p_mfc_platdata), GFP_KERNEL); + dev->pdata = devm_kzalloc(&pdev->dev, sizeof(struct mfc_platdata), GFP_KERNEL); if (!dev->pdata) { dev_err(&pdev->dev, "no memory for state\n"); ret = -ENOMEM; goto err_pm; } - mfc_parse_dt(dev->device->of_node, dev); + __mfc_parse_dt(dev->device->of_node, dev); atomic_set(&dev->trace_ref, 0); atomic_set(&dev->trace_ref_hwlock, 0); @@ -1265,8 +1265,8 @@ static int s5p_mfc_probe(struct platform_device *pdev) dma_set_mask(&pdev->dev, DMA_BIT_MASK(36)); - s5p_mfc_pm_init(dev); - ret = mfc_register_resource(pdev, dev); + mfc_pm_init(dev); + ret = __mfc_register_resource(pdev, dev); if (ret) goto err_res_mem; @@ -1277,10 +1277,10 @@ static int s5p_mfc_probe(struct platform_device *pdev) goto err_v4l2_dev; init_waitqueue_head(&dev->cmd_wq); - s5p_mfc_init_listable_wq_dev(dev); + mfc_init_listable_wq_dev(dev); /* decoder */ - dev->vfd_dec = mfc_video_device_register(dev, S5P_MFC_DEC_NAME, + dev->vfd_dec = __mfc_video_device_register(dev, MFC_DEC_NAME, EXYNOS_VIDEONODE_MFC_DEC); if (!dev->vfd_dec) { ret = -ENOMEM; @@ -1288,7 +1288,7 @@ static int s5p_mfc_probe(struct platform_device *pdev) } /* encoder */ - dev->vfd_enc = mfc_video_device_register(dev, S5P_MFC_ENC_NAME, + dev->vfd_enc = __mfc_video_device_register(dev, MFC_ENC_NAME, EXYNOS_VIDEONODE_MFC_ENC); if (!dev->vfd_enc) { ret = -ENOMEM; @@ -1296,7 +1296,7 @@ static int s5p_mfc_probe(struct platform_device *pdev) } /* secure decoder */ - dev->vfd_dec_drm = mfc_video_device_register(dev, S5P_MFC_DEC_DRM_NAME, + dev->vfd_dec_drm = __mfc_video_device_register(dev, MFC_DEC_DRM_NAME, EXYNOS_VIDEONODE_MFC_DEC_DRM); if (!dev->vfd_dec_drm) { ret = -ENOMEM; @@ -1304,7 +1304,7 @@ static int s5p_mfc_probe(struct platform_device *pdev) } /* secure encoder */ - dev->vfd_enc_drm = mfc_video_device_register(dev, S5P_MFC_ENC_DRM_NAME, + dev->vfd_enc_drm = __mfc_video_device_register(dev, MFC_ENC_DRM_NAME, EXYNOS_VIDEONODE_MFC_ENC_DRM); if (!dev->vfd_enc_drm) { ret = -ENOMEM; @@ -1312,7 +1312,7 @@ static int s5p_mfc_probe(struct platform_device *pdev) } /* OTF encoder */ - dev->vfd_enc_otf = mfc_video_device_register(dev, S5P_MFC_ENC_OTF_NAME, + dev->vfd_enc_otf = __mfc_video_device_register(dev, MFC_ENC_OTF_NAME, EXYNOS_VIDEONODE_MFC_ENC_OTF); if (!dev->vfd_enc_otf) { ret = -ENOMEM; @@ -1320,7 +1320,7 @@ static int s5p_mfc_probe(struct platform_device *pdev) } /* OTF secure encoder */ - dev->vfd_enc_otf_drm = mfc_video_device_register(dev, S5P_MFC_ENC_OTF_DRM_NAME, + dev->vfd_enc_otf_drm = __mfc_video_device_register(dev, MFC_ENC_OTF_DRM_NAME, EXYNOS_VIDEONODE_MFC_ENC_OTF_DRM); if (!dev->vfd_enc_otf_drm) { ret = -ENOMEM; @@ -1330,35 +1330,35 @@ static int s5p_mfc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, dev); - s5p_mfc_init_hwlock(dev); - s5p_mfc_create_bits(&dev->work_bits); + mfc_init_hwlock(dev); + mfc_create_bits(&dev->work_bits); dev->watchdog_wq = - create_singlethread_workqueue("s5p_mfc/watchdog"); + create_singlethread_workqueue("mfc/watchdog"); if (!dev->watchdog_wq) { dev_err(&pdev->dev, "failed to create workqueue for watchdog\n"); goto err_wq_watchdog; } - INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker); + INIT_WORK(&dev->watchdog_work, mfc_watchdog_worker); atomic_set(&dev->watchdog_tick_running, 0); atomic_set(&dev->watchdog_tick_cnt, 0); atomic_set(&dev->watchdog_run, 0); init_timer(&dev->watchdog_timer); dev->watchdog_timer.data = (unsigned long)dev; - dev->watchdog_timer.function = s5p_mfc_watchdog_tick; + dev->watchdog_timer.function = mfc_watchdog_tick; #ifdef CONFIG_MFC_USE_BUS_DEVFREQ INIT_LIST_HEAD(&dev->qos_queue); #endif /* default FW alloc is added */ - dev->butler_wq = alloc_workqueue("s5p_mfc/butler", WQ_UNBOUND + dev->butler_wq = alloc_workqueue("mfc/butler", WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI, 1); if (dev->butler_wq == NULL) { dev_err(&pdev->dev, "failed to create workqueue for butler\n"); goto err_butler_wq; } - INIT_WORK(&dev->butler_work, s5p_mfc_butler_worker); + INIT_WORK(&dev->butler_work, mfc_butler_worker); /* dump information call-back function */ dev->dump_ops = &mfc_dump_ops; @@ -1378,7 +1378,7 @@ static int s5p_mfc_probe(struct platform_device *pdev) #endif iovmm_set_fault_handler(dev->device, - s5p_mfc_sysmmu_fault_handler, dev); + mfc_sysmmu_fault_handler, dev); g_mfc_dev = dev; @@ -1388,7 +1388,7 @@ static int s5p_mfc_probe(struct platform_device *pdev) goto err_iovmm_active; } - dev->logging_data = devm_kzalloc(&pdev->dev, sizeof(struct s5p_mfc_debug), GFP_KERNEL); + dev->logging_data = devm_kzalloc(&pdev->dev, sizeof(struct mfc_debug), GFP_KERNEL); if (!dev->logging_data) { dev_err(&pdev->dev, "no memory for logging data\n"); ret = -ENOMEM; @@ -1396,11 +1396,11 @@ static int s5p_mfc_probe(struct platform_device *pdev) } #ifdef CONFIG_EXYNOS_ITMON - dev->itmon_nb.notifier_call = mfc_itmon_notifier; + dev->itmon_nb.notifier_call = __mfc_itmon_notifier; itmon_notifier_chain_register(&dev->itmon_nb); #endif - s5p_mfc_init_debugfs(dev); + mfc_init_debugfs(dev); pr_debug("%s--\n", __func__); return 0; @@ -1439,15 +1439,15 @@ err_v4l2_dev: iounmap(dev->regs_base); release_mem_region(dev->mfc_mem->start, resource_size(dev->mfc_mem)); err_res_mem: - s5p_mfc_pm_final(dev); + mfc_pm_final(dev); err_pm: return ret; } /* Remove the driver */ -static int s5p_mfc_remove(struct platform_device *pdev) +static int mfc_remove(struct platform_device *pdev) { - struct s5p_mfc_dev *dev = platform_get_drvdata(pdev); + struct mfc_dev *dev = platform_get_drvdata(pdev); dev_dbg(&pdev->dev, "%s++\n", __func__); v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name); @@ -1467,10 +1467,10 @@ static int s5p_mfc_remove(struct platform_device *pdev) remove_proc_entry(MFC_PROC_INSTANCE_NUMBER, mfc_proc_entry); remove_proc_entry(MFC_PROC_ROOT, NULL); #endif - s5p_mfc_destroy_listable_wq_dev(dev); + mfc_destroy_listable_wq_dev(dev); iovmm_deactivate(&pdev->dev); mfc_debug(2, "Will now deinit HW\n"); - s5p_mfc_deinit_hw(dev); + mfc_deinit_hw(dev); free_irq(dev->irq, dev); if (dev->has_mmcache) iounmap(dev->mmcache.base); @@ -1481,44 +1481,44 @@ static int s5p_mfc_remove(struct platform_device *pdev) iounmap(dev->sysmmu0_base); iounmap(dev->regs_base); release_mem_region(dev->mfc_mem->start, resource_size(dev->mfc_mem)); - s5p_mfc_pm_final(dev); + mfc_pm_final(dev); kfree(dev); dev_dbg(&pdev->dev, "%s--\n", __func__); return 0; } -static void s5p_mfc_shutdown(struct platform_device *pdev) +static void mfc_shutdown(struct platform_device *pdev) { - struct s5p_mfc_dev *dev = platform_get_drvdata(pdev); + struct mfc_dev *dev = platform_get_drvdata(pdev); int ret; mfc_info_dev("MFC shutdown is called\n"); MFC_TRACE_DEV_HWLOCK("**shutdown \n"); - if (!s5p_mfc_pm_get_pwr_ref_cnt(dev)) { + if (!mfc_pm_get_pwr_ref_cnt(dev)) { dev->shutdown = 1; mfc_info_dev("MFC is not running\n"); return; } - ret = s5p_mfc_get_hwlock_dev(dev); + ret = mfc_get_hwlock_dev(dev); if (ret < 0) mfc_err_dev("Failed to get hwlock\n"); if (!dev->shutdown) { - s5p_mfc_risc_off(dev); + mfc_risc_off(dev); dev->shutdown = 1; - s5p_mfc_clear_all_bits(&dev->work_bits); + mfc_clear_all_bits(&dev->work_bits); iovmm_deactivate(&pdev->dev); } - s5p_mfc_release_hwlock_dev(dev); + mfc_release_hwlock_dev(dev); mfc_info_dev("MFC shutdown completed\n"); } #ifdef CONFIG_PM_SLEEP -static int s5p_mfc_suspend(struct device *dev) +static int mfc_suspend(struct device *dev) { - struct s5p_mfc_dev *m_dev = platform_get_drvdata(to_platform_device(dev)); + struct mfc_dev *m_dev = platform_get_drvdata(to_platform_device(dev)); int ret; if (!m_dev) { @@ -1529,14 +1529,14 @@ static int s5p_mfc_suspend(struct device *dev) if (m_dev->num_inst == 0) return 0; - ret = s5p_mfc_sleep(m_dev); + ret = mfc_sleep(m_dev); return ret; } -static int s5p_mfc_resume(struct device *dev) +static int mfc_resume(struct device *dev) { - struct s5p_mfc_dev *m_dev = platform_get_drvdata(to_platform_device(dev)); + struct mfc_dev *m_dev = platform_get_drvdata(to_platform_device(dev)); int ret; if (!m_dev) { @@ -1547,26 +1547,26 @@ static int s5p_mfc_resume(struct device *dev) if (m_dev->num_inst == 0) return 0; - ret = s5p_mfc_wakeup(m_dev); + ret = mfc_wakeup(m_dev); return ret; } #endif #ifdef CONFIG_PM -static int s5p_mfc_runtime_suspend(struct device *dev) +static int mfc_runtime_suspend(struct device *dev) { mfc_debug(3, "mfc runtime suspend\n"); return 0; } -static int s5p_mfc_runtime_idle(struct device *dev) +static int mfc_runtime_idle(struct device *dev) { return 0; } -static int s5p_mfc_runtime_resume(struct device *dev) +static int mfc_runtime_resume(struct device *dev) { mfc_debug(3, "mfc runtime resume\n"); @@ -1575,16 +1575,16 @@ static int s5p_mfc_runtime_resume(struct device *dev) #endif /* Power management */ -static const struct dev_pm_ops s5p_mfc_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume) +static const struct dev_pm_ops mfc_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(mfc_suspend, mfc_resume) SET_RUNTIME_PM_OPS( - s5p_mfc_runtime_suspend, - s5p_mfc_runtime_resume, - s5p_mfc_runtime_idle + mfc_runtime_suspend, + mfc_runtime_resume, + mfc_runtime_idle ) }; -struct s5p_mfc_ctx_buf_size mfc_ctx_buf_size = { +struct mfc_ctx_buf_size mfc_ctx_buf_size = { .dev_ctx = PAGE_ALIGN(0x7800), /* 30KB */ .h264_dec_ctx = PAGE_ALIGN(0x200000), /* 1.6MB */ .other_dec_ctx = PAGE_ALIGN(0x7800), /* 30KB */ @@ -1595,13 +1595,13 @@ struct s5p_mfc_ctx_buf_size mfc_ctx_buf_size = { .dbg_info_buf = PAGE_ALIGN(0x1000), /* 4KB for DEBUG INFO */ }; -struct s5p_mfc_buf_size mfc_buf_size = { +struct mfc_buf_size mfc_buf_size = { .firmware_code = PAGE_ALIGN(0x100000), /* 1MB */ .cpb_buf = PAGE_ALIGN(0x300000), /* 3MB */ .ctx_buf = &mfc_ctx_buf_size, }; -static struct s5p_mfc_variant mfc_drvdata = { +static struct mfc_variant mfc_drvdata = { .buf_size = &mfc_buf_size, .num_entities = 2, }; @@ -1615,37 +1615,37 @@ static const struct of_device_id exynos_mfc_match[] = { }; MODULE_DEVICE_TABLE(of, exynos_mfc_match); -static void *mfc_get_drv_data(struct platform_device *pdev) +static void *__mfc_get_drv_data(struct platform_device *pdev) { - struct s5p_mfc_variant *driver_data = NULL; + struct mfc_variant *driver_data = NULL; if (pdev->dev.of_node) { const struct of_device_id *match; match = of_match_node(of_match_ptr(exynos_mfc_match), pdev->dev.of_node); if (match) - driver_data = (struct s5p_mfc_variant *)match->data; + driver_data = (struct mfc_variant *)match->data; } else { - driver_data = (struct s5p_mfc_variant *) + driver_data = (struct mfc_variant *) platform_get_device_id(pdev)->driver_data; } return driver_data; } -static struct platform_driver s5p_mfc_driver = { - .probe = s5p_mfc_probe, - .remove = s5p_mfc_remove, - .shutdown = s5p_mfc_shutdown, +static struct platform_driver mfc_driver = { + .probe = mfc_probe, + .remove = mfc_remove, + .shutdown = mfc_shutdown, .driver = { - .name = S5P_MFC_NAME, + .name = MFC_NAME, .owner = THIS_MODULE, - .pm = &s5p_mfc_pm_ops, + .pm = &mfc_pm_ops, .of_match_table = exynos_mfc_match, .suppress_bind_attrs = true, }, }; -module_platform_driver(s5p_mfc_driver); +module_platform_driver(mfc_driver); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Kamil Debski "); diff --git a/drivers/media/platform/exynos/mfc/mfc_buf.c b/drivers/media/platform/exynos/mfc/mfc_buf.c index d93489f2afe2..17c10e470679 100644 --- a/drivers/media/platform/exynos/mfc/mfc_buf.c +++ b/drivers/media/platform/exynos/mfc/mfc_buf.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_buf.c + * drivers/media/platform/exynos/mfc/mfc_buf.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -18,10 +18,10 @@ #include "mfc_mem.h" -static int mfc_alloc_common_context(struct s5p_mfc_dev *dev, +static int __mfc_alloc_common_context(struct mfc_dev *dev, enum mfc_buf_usage_type buf_type) { - struct s5p_mfc_special_buf *ctx_buf; + struct mfc_special_buf *ctx_buf; int firmware_size; unsigned long fw_daddr; @@ -53,16 +53,16 @@ static int mfc_alloc_common_context(struct s5p_mfc_dev *dev, } /* Wrapper : allocate context buffers for SYS_INIT */ -int s5p_mfc_alloc_common_context(struct s5p_mfc_dev *dev) +int mfc_alloc_common_context(struct mfc_dev *dev) { int ret = 0; - ret = mfc_alloc_common_context(dev, MFCBUF_NORMAL); + ret = __mfc_alloc_common_context(dev, MFCBUF_NORMAL); if (ret) return ret; #ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION if (dev->fw.drm_status) { - ret = mfc_alloc_common_context(dev, MFCBUF_DRM); + ret = __mfc_alloc_common_context(dev, MFCBUF_DRM); if (ret) return ret; } @@ -72,10 +72,10 @@ int s5p_mfc_alloc_common_context(struct s5p_mfc_dev *dev) } /* Release context buffers for SYS_INIT */ -static void mfc_release_common_context(struct s5p_mfc_dev *dev, +static void __mfc_release_common_context(struct mfc_dev *dev, enum mfc_buf_usage_type buf_type) { - struct s5p_mfc_special_buf *ctx_buf; + struct mfc_special_buf *ctx_buf; if (!dev) { mfc_err_dev("no mfc device to run\n"); @@ -94,20 +94,20 @@ static void mfc_release_common_context(struct s5p_mfc_dev *dev, } /* Release context buffers for SYS_INIT */ -void s5p_mfc_release_common_context(struct s5p_mfc_dev *dev) +void mfc_release_common_context(struct mfc_dev *dev) { - mfc_release_common_context(dev, MFCBUF_NORMAL); + __mfc_release_common_context(dev, MFCBUF_NORMAL); #ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION - mfc_release_common_context(dev, MFCBUF_DRM); + __mfc_release_common_context(dev, MFCBUF_DRM); #endif } /* Allocate memory for instance data buffer */ -int s5p_mfc_alloc_instance_context(struct s5p_mfc_ctx *ctx) +int mfc_alloc_instance_context(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev; - struct s5p_mfc_ctx_buf_size *buf_size; + struct mfc_dev *dev; + struct mfc_ctx_buf_size *buf_size; mfc_debug_enter(); if (!ctx) { @@ -122,36 +122,36 @@ int s5p_mfc_alloc_instance_context(struct s5p_mfc_ctx *ctx) buf_size = dev->variant->buf_size->ctx_buf; switch (ctx->codec_mode) { - case S5P_FIMV_CODEC_H264_DEC: - case S5P_FIMV_CODEC_H264_MVC_DEC: - case S5P_FIMV_CODEC_HEVC_DEC: - case S5P_FIMV_CODEC_BPG_DEC: + case MFC_REG_CODEC_H264_DEC: + case MFC_REG_CODEC_H264_MVC_DEC: + case MFC_REG_CODEC_HEVC_DEC: + case MFC_REG_CODEC_BPG_DEC: ctx->instance_ctx_buf.size = buf_size->h264_dec_ctx; break; - case S5P_FIMV_CODEC_MPEG4_DEC: - case S5P_FIMV_CODEC_H263_DEC: - case S5P_FIMV_CODEC_VC1_RCV_DEC: - case S5P_FIMV_CODEC_VC1_DEC: - case S5P_FIMV_CODEC_MPEG2_DEC: - case S5P_FIMV_CODEC_VP8_DEC: - case S5P_FIMV_CODEC_VP9_DEC: - case S5P_FIMV_CODEC_FIMV1_DEC: - case S5P_FIMV_CODEC_FIMV2_DEC: - case S5P_FIMV_CODEC_FIMV3_DEC: - case S5P_FIMV_CODEC_FIMV4_DEC: + case MFC_REG_CODEC_MPEG4_DEC: + case MFC_REG_CODEC_H263_DEC: + case MFC_REG_CODEC_VC1_RCV_DEC: + case MFC_REG_CODEC_VC1_DEC: + case MFC_REG_CODEC_MPEG2_DEC: + case MFC_REG_CODEC_VP8_DEC: + case MFC_REG_CODEC_VP9_DEC: + case MFC_REG_CODEC_FIMV1_DEC: + case MFC_REG_CODEC_FIMV2_DEC: + case MFC_REG_CODEC_FIMV3_DEC: + case MFC_REG_CODEC_FIMV4_DEC: ctx->instance_ctx_buf.size = buf_size->other_dec_ctx; break; - case S5P_FIMV_CODEC_H264_ENC: + case MFC_REG_CODEC_H264_ENC: ctx->instance_ctx_buf.size = buf_size->h264_enc_ctx; break; - case S5P_FIMV_CODEC_HEVC_ENC: - case S5P_FIMV_CODEC_BPG_ENC: + case MFC_REG_CODEC_HEVC_ENC: + case MFC_REG_CODEC_BPG_ENC: ctx->instance_ctx_buf.size = buf_size->hevc_enc_ctx; break; - case S5P_FIMV_CODEC_MPEG4_ENC: - case S5P_FIMV_CODEC_H263_ENC: - case S5P_FIMV_CODEC_VP8_ENC: - case S5P_FIMV_CODEC_VP9_ENC: + case MFC_REG_CODEC_MPEG4_ENC: + case MFC_REG_CODEC_H263_ENC: + case MFC_REG_CODEC_VP8_ENC: + case MFC_REG_CODEC_VP9_ENC: ctx->instance_ctx_buf.size = buf_size->other_enc_ctx; break; default: @@ -165,7 +165,7 @@ int s5p_mfc_alloc_instance_context(struct s5p_mfc_ctx *ctx) else ctx->instance_ctx_buf.buftype = MFCBUF_NORMAL; - if (s5p_mfc_mem_ion_alloc(dev, &ctx->instance_ctx_buf)) { + if (mfc_mem_ion_alloc(dev, &ctx->instance_ctx_buf)) { mfc_err_ctx("Allocating context buffer failed\n"); return -ENOMEM; } @@ -177,9 +177,9 @@ int s5p_mfc_alloc_instance_context(struct s5p_mfc_ctx *ctx) } /* Release instance buffer */ -void s5p_mfc_release_instance_context(struct s5p_mfc_ctx *ctx) +void mfc_release_instance_context(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev; + struct mfc_dev *dev; mfc_debug_enter(); if (!ctx) { @@ -193,33 +193,33 @@ void s5p_mfc_release_instance_context(struct s5p_mfc_ctx *ctx) return; } - s5p_mfc_mem_ion_free(dev, &ctx->instance_ctx_buf); + mfc_mem_ion_free(dev, &ctx->instance_ctx_buf); mfc_debug(2, "[MEMINFO] Release the instance buffer ctx[%d]\n", ctx->num); mfc_debug_leave(); } -static void mfc_calc_dec_codec_buffer_size(struct s5p_mfc_ctx *ctx) +static void __mfc_calc_dec_codec_buffer_size(struct mfc_ctx *ctx) { - struct s5p_mfc_dec *dec; + struct mfc_dec *dec; int i; dec = ctx->dec_priv; /* Codecs have different memory requirements */ switch (ctx->codec_mode) { - case S5P_FIMV_CODEC_H264_DEC: - case S5P_FIMV_CODEC_H264_MVC_DEC: + case MFC_REG_CODEC_H264_DEC: + case MFC_REG_CODEC_H264_MVC_DEC: ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256); ctx->codec_buf.size = ctx->scratch_buf_size + (dec->mv_count * ctx->mv_size); break; - case S5P_FIMV_CODEC_MPEG4_DEC: - case S5P_FIMV_CODEC_FIMV1_DEC: - case S5P_FIMV_CODEC_FIMV2_DEC: - case S5P_FIMV_CODEC_FIMV3_DEC: - case S5P_FIMV_CODEC_FIMV4_DEC: + case MFC_REG_CODEC_MPEG4_DEC: + case MFC_REG_CODEC_FIMV1_DEC: + case MFC_REG_CODEC_FIMV2_DEC: + case MFC_REG_CODEC_FIMV3_DEC: + case MFC_REG_CODEC_FIMV4_DEC: ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256); if (dec->loop_filter_mpeg4) { ctx->loopfilter_luma_size = ALIGN(ctx->raw_buf.plane_size[0], 256); @@ -232,31 +232,31 @@ static void mfc_calc_dec_codec_buffer_size(struct s5p_mfc_ctx *ctx) ctx->codec_buf.size = ctx->scratch_buf_size; } break; - case S5P_FIMV_CODEC_VC1_RCV_DEC: - case S5P_FIMV_CODEC_VC1_DEC: + case MFC_REG_CODEC_VC1_RCV_DEC: + case MFC_REG_CODEC_VC1_DEC: ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256); ctx->codec_buf.size = ctx->scratch_buf_size; break; - case S5P_FIMV_CODEC_MPEG2_DEC: + case MFC_REG_CODEC_MPEG2_DEC: ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256); ctx->codec_buf.size = ctx->scratch_buf_size; break; - case S5P_FIMV_CODEC_H263_DEC: + case MFC_REG_CODEC_H263_DEC: ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256); ctx->codec_buf.size = ctx->scratch_buf_size; break; - case S5P_FIMV_CODEC_VP8_DEC: + case MFC_REG_CODEC_VP8_DEC: ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256); ctx->codec_buf.size = ctx->scratch_buf_size; break; - case S5P_FIMV_CODEC_VP9_DEC: + case MFC_REG_CODEC_VP9_DEC: ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256); ctx->codec_buf.size = ctx->scratch_buf_size + DEC_STATIC_BUFFER_SIZE; break; - case S5P_FIMV_CODEC_HEVC_DEC: - case S5P_FIMV_CODEC_BPG_DEC: + case MFC_REG_CODEC_HEVC_DEC: + case MFC_REG_CODEC_BPG_DEC: ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256); ctx->codec_buf.size = ctx->scratch_buf_size + @@ -276,9 +276,9 @@ static void mfc_calc_dec_codec_buffer_size(struct s5p_mfc_ctx *ctx) NUM_MPEG4_LF_BUF); } -static void mfc_calc_enc_codec_buffer_size(struct s5p_mfc_ctx *ctx) +static void __mfc_calc_enc_codec_buffer_size(struct mfc_ctx *ctx) { - struct s5p_mfc_enc *enc; + struct mfc_enc *enc; unsigned int mb_width, mb_height; unsigned int lcu_width = 0, lcu_height = 0; @@ -299,7 +299,7 @@ static void mfc_calc_enc_codec_buffer_size(struct s5p_mfc_ctx *ctx) /* Codecs have different memory requirements */ switch (ctx->codec_mode) { - case S5P_FIMV_CODEC_H264_ENC: + case MFC_REG_CODEC_H264_ENC: enc->me_buffer_size = ALIGN(ENC_V100_H264_ME_SIZE(mb_width, mb_height), 256); @@ -309,8 +309,8 @@ static void mfc_calc_enc_codec_buffer_size(struct s5p_mfc_ctx *ctx) (ctx->dpb_count * (enc->luma_dpb_size + enc->chroma_dpb_size + enc->me_buffer_size)); break; - case S5P_FIMV_CODEC_MPEG4_ENC: - case S5P_FIMV_CODEC_H263_ENC: + case MFC_REG_CODEC_MPEG4_ENC: + case MFC_REG_CODEC_H263_ENC: enc->me_buffer_size = ALIGN(ENC_V100_MPEG4_ME_SIZE(mb_width, mb_height), 256); @@ -320,7 +320,7 @@ static void mfc_calc_enc_codec_buffer_size(struct s5p_mfc_ctx *ctx) (ctx->dpb_count * (enc->luma_dpb_size + enc->chroma_dpb_size + enc->me_buffer_size)); break; - case S5P_FIMV_CODEC_VP8_ENC: + case MFC_REG_CODEC_VP8_ENC: enc->me_buffer_size = ALIGN(ENC_V100_VP8_ME_SIZE(mb_width, mb_height), 256); @@ -330,7 +330,7 @@ static void mfc_calc_enc_codec_buffer_size(struct s5p_mfc_ctx *ctx) (ctx->dpb_count * (enc->luma_dpb_size + enc->chroma_dpb_size + enc->me_buffer_size)); break; - case S5P_FIMV_CODEC_VP9_ENC: + case MFC_REG_CODEC_VP9_ENC: if (ctx->is_10bit || ctx->is_422) { enc->luma_dpb_size = ALIGN(ENC_VP9_LUMA_DPB_10B_SIZE(ctx->crop_width, ctx->crop_height), 64); @@ -348,8 +348,8 @@ static void mfc_calc_enc_codec_buffer_size(struct s5p_mfc_ctx *ctx) (ctx->dpb_count * (enc->luma_dpb_size + enc->chroma_dpb_size + enc->me_buffer_size)); break; - case S5P_FIMV_CODEC_HEVC_ENC: - case S5P_FIMV_CODEC_BPG_ENC: + case MFC_REG_CODEC_HEVC_ENC: + case MFC_REG_CODEC_BPG_ENC: if (ctx->is_10bit || ctx->is_422) { enc->luma_dpb_size = ALIGN(ENC_HEVC_LUMA_DPB_10B_SIZE(ctx->crop_width, ctx->crop_height), 64); @@ -380,9 +380,9 @@ static void mfc_calc_enc_codec_buffer_size(struct s5p_mfc_ctx *ctx) } /* Allocate codec buffers */ -int s5p_mfc_alloc_codec_buffers(struct s5p_mfc_ctx *ctx) +int mfc_alloc_codec_buffers(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev; + struct mfc_dev *dev; mfc_debug_enter(); if (!ctx) { @@ -396,9 +396,9 @@ int s5p_mfc_alloc_codec_buffers(struct s5p_mfc_ctx *ctx) } if (ctx->type == MFCINST_DECODER) { - mfc_calc_dec_codec_buffer_size(ctx); + __mfc_calc_dec_codec_buffer_size(ctx); } else if (ctx->type == MFCINST_ENCODER) { - mfc_calc_enc_codec_buffer_size(ctx); + __mfc_calc_enc_codec_buffer_size(ctx); } else { mfc_err_ctx("invalid type: %d\n", ctx->type); return -EINVAL; @@ -410,12 +410,12 @@ int s5p_mfc_alloc_codec_buffers(struct s5p_mfc_ctx *ctx) ctx->codec_buf.buftype = MFCBUF_NORMAL; if (ctx->codec_buf.size > 0) { - if (s5p_mfc_mem_ion_alloc(dev, &ctx->codec_buf)) { + if (mfc_mem_ion_alloc(dev, &ctx->codec_buf)) { mfc_err_ctx("Allocating codec buffer failed\n"); return -ENOMEM; } ctx->codec_buffer_allocated = 1; - } else if (ctx->codec_mode == S5P_FIMV_CODEC_MPEG2_DEC) { + } else if (ctx->codec_mode == MFC_REG_CODEC_MPEG2_DEC) { ctx->codec_buffer_allocated = 1; } @@ -426,9 +426,9 @@ int s5p_mfc_alloc_codec_buffers(struct s5p_mfc_ctx *ctx) } /* Release buffers allocated for codec */ -void s5p_mfc_release_codec_buffers(struct s5p_mfc_ctx *ctx) +void mfc_release_codec_buffers(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev; + struct mfc_dev *dev; if (!ctx) { mfc_err_dev("no mfc context to run\n"); @@ -441,21 +441,21 @@ void s5p_mfc_release_codec_buffers(struct s5p_mfc_ctx *ctx) return; } - s5p_mfc_mem_ion_free(dev, &ctx->codec_buf); + mfc_mem_ion_free(dev, &ctx->codec_buf); ctx->codec_buffer_allocated = 0; mfc_debug(2, "[MEMINFO] Release the codec buffer ctx[%d]\n", ctx->num); } /* Allocation buffer of debug infor memory for FW debugging */ -int s5p_mfc_alloc_dbg_info_buffer(struct s5p_mfc_dev *dev) +int mfc_alloc_dbg_info_buffer(struct mfc_dev *dev) { - struct s5p_mfc_ctx_buf_size *buf_size = dev->variant->buf_size->ctx_buf; + struct mfc_ctx_buf_size *buf_size = dev->variant->buf_size->ctx_buf; mfc_debug(2, "Allocate a debug-info buffer\n"); dev->dbg_info_buf.buftype = MFCBUF_NORMAL; dev->dbg_info_buf.size = buf_size->dbg_info_buf; - if (s5p_mfc_mem_ion_alloc(dev, &dev->dbg_info_buf)) { + if (mfc_mem_ion_alloc(dev, &dev->dbg_info_buf)) { mfc_err_dev("Allocating debug info buffer failed\n"); return -ENOMEM; } @@ -466,7 +466,7 @@ int s5p_mfc_alloc_dbg_info_buffer(struct s5p_mfc_dev *dev) } /* Release buffer of debug infor memory for FW debugging */ -int s5p_mfc_release_dbg_info_buffer(struct s5p_mfc_dev *dev) +int mfc_release_dbg_info_buffer(struct mfc_dev *dev) { if (!dev) { mfc_err_dev("no mfc device to run\n"); @@ -478,21 +478,21 @@ int s5p_mfc_release_dbg_info_buffer(struct s5p_mfc_dev *dev) return 0; } - s5p_mfc_mem_ion_free(dev, &dev->dbg_info_buf); + mfc_mem_ion_free(dev, &dev->dbg_info_buf); mfc_debug(2, "[MEMINFO] Release the debug info buffer\n"); return 0; } /* Allocation buffer of ROI macroblock information */ -static int mfc_alloc_enc_roi_buffer(struct s5p_mfc_ctx *ctx, struct s5p_mfc_special_buf *roi_buf) +static int __mfc_alloc_enc_roi_buffer(struct mfc_ctx *ctx, struct mfc_special_buf *roi_buf) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_ctx_buf_size *buf_size = dev->variant->buf_size->ctx_buf; + struct mfc_dev *dev = ctx->dev; + struct mfc_ctx_buf_size *buf_size = dev->variant->buf_size->ctx_buf; roi_buf->buftype = MFCBUF_NORMAL; roi_buf->size = buf_size->shared_buf; - if (s5p_mfc_mem_ion_alloc(dev, roi_buf)) { + if (mfc_mem_ion_alloc(dev, roi_buf)) { mfc_err_ctx("[ROI] Allocating ROI buffer failed\n"); return -ENOMEM; } @@ -505,13 +505,13 @@ static int mfc_alloc_enc_roi_buffer(struct s5p_mfc_ctx *ctx, struct s5p_mfc_spec } /* Wrapper : allocation ROI buffers */ -int s5p_mfc_alloc_enc_roi_buffer(struct s5p_mfc_ctx *ctx) +int mfc_alloc_enc_roi_buffer(struct mfc_ctx *ctx) { - struct s5p_mfc_enc *enc = ctx->enc_priv; + struct mfc_enc *enc = ctx->enc_priv; int i; for (i = 0; i < MFC_MAX_EXTRA_BUF; i++) { - if (mfc_alloc_enc_roi_buffer(ctx, &enc->roi_buf[i]) < 0) { + if (__mfc_alloc_enc_roi_buffer(ctx, &enc->roi_buf[i]) < 0) { mfc_err_dev("[ROI] Allocating remapping buffer[%d] failed\n", i); return -ENOMEM; } @@ -521,25 +521,25 @@ int s5p_mfc_alloc_enc_roi_buffer(struct s5p_mfc_ctx *ctx) } /* Release buffer of ROI macroblock information */ -void s5p_mfc_release_enc_roi_buffer(struct s5p_mfc_ctx *ctx) +void mfc_release_enc_roi_buffer(struct mfc_ctx *ctx) { - struct s5p_mfc_enc *enc = ctx->enc_priv; + struct mfc_enc *enc = ctx->enc_priv; int i; for (i = 0; i < MFC_MAX_EXTRA_BUF; i++) if (enc->roi_buf[i].dma_buf) - s5p_mfc_mem_ion_free(ctx->dev, &enc->roi_buf[i]); + mfc_mem_ion_free(ctx->dev, &enc->roi_buf[i]); mfc_debug(2, "[MEMINFO][ROI] Release the ROI buffer\n"); } -int s5p_mfc_otf_alloc_stream_buf(struct s5p_mfc_ctx *ctx) +int mfc_otf_alloc_stream_buf(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; struct _otf_handle *handle = ctx->otf_handle; struct _otf_debug *debug = &handle->otf_debug; - struct s5p_mfc_special_buf *buf; - struct s5p_mfc_raw_info *raw = &ctx->raw_buf; + struct mfc_special_buf *buf; + struct mfc_raw_info *raw = &ctx->raw_buf; int i; mfc_debug_enter(); @@ -548,7 +548,7 @@ int s5p_mfc_otf_alloc_stream_buf(struct s5p_mfc_ctx *ctx) buf = &debug->stream_buf[i]; buf->buftype = MFCBUF_NORMAL; buf->size = raw->total_plane_size; - if (s5p_mfc_mem_ion_alloc(dev, buf)) { + if (mfc_mem_ion_alloc(dev, buf)) { mfc_err_ctx("[OTF] Allocating stream buffer failed\n"); return -EINVAL; } @@ -562,12 +562,12 @@ int s5p_mfc_otf_alloc_stream_buf(struct s5p_mfc_ctx *ctx) return 0; } -void s5p_mfc_otf_release_stream_buf(struct s5p_mfc_ctx *ctx) +void mfc_otf_release_stream_buf(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; struct _otf_handle *handle = ctx->otf_handle; struct _otf_debug *debug = &handle->otf_debug; - struct s5p_mfc_special_buf *buf; + struct mfc_special_buf *buf; int i; mfc_debug_enter(); @@ -575,7 +575,7 @@ void s5p_mfc_otf_release_stream_buf(struct s5p_mfc_ctx *ctx) for (i = 0; i < OTF_MAX_BUF; i++) { buf = &debug->stream_buf[i]; if (buf->dma_buf) - s5p_mfc_mem_ion_free(dev, buf); + mfc_mem_ion_free(dev, buf); } mfc_debug(2, "[OTF][MEMINFO] Release the OTF stream buffer\n"); @@ -583,10 +583,10 @@ void s5p_mfc_otf_release_stream_buf(struct s5p_mfc_ctx *ctx) } /* Allocate firmware */ -int s5p_mfc_alloc_firmware(struct s5p_mfc_dev *dev) +int mfc_alloc_firmware(struct mfc_dev *dev) { size_t firmware_size; - struct s5p_mfc_ctx_buf_size *buf_size; + struct mfc_ctx_buf_size *buf_size; mfc_debug_enter(); @@ -607,7 +607,7 @@ int s5p_mfc_alloc_firmware(struct s5p_mfc_dev *dev) dev->fw_buf.buftype = MFCBUF_NORMAL; dev->fw_buf.size = dev->fw.size; - if (s5p_mfc_mem_ion_alloc(dev, &dev->fw_buf)) { + if (mfc_mem_ion_alloc(dev, &dev->fw_buf)) { mfc_err_dev("[F/W] Allocating normal firmware buffer failed\n"); return -ENOMEM; } @@ -619,7 +619,7 @@ int s5p_mfc_alloc_firmware(struct s5p_mfc_dev *dev) #ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION dev->drm_fw_buf.buftype = MFCBUF_DRM_FW; dev->drm_fw_buf.size = dev->fw.size; - if (s5p_mfc_mem_ion_alloc(dev, &dev->drm_fw_buf)) { + if (mfc_mem_ion_alloc(dev, &dev->drm_fw_buf)) { mfc_err_dev("[F/W] Allocating DRM firmware buffer failed\n"); return -ENOMEM; } @@ -635,7 +635,7 @@ int s5p_mfc_alloc_firmware(struct s5p_mfc_dev *dev) } /* Load firmware to MFC */ -int s5p_mfc_load_firmware(struct s5p_mfc_dev *dev) +int mfc_load_firmware(struct mfc_dev *dev) { struct firmware *fw_blob; size_t firmware_size; @@ -687,7 +687,7 @@ int s5p_mfc_load_firmware(struct s5p_mfc_dev *dev) } /* Release firmware memory */ -int s5p_mfc_release_firmware(struct s5p_mfc_dev *dev) +int mfc_release_firmware(struct mfc_dev *dev) { /* Before calling this function one has to make sure * that MFC is no longer processing */ @@ -702,10 +702,10 @@ int s5p_mfc_release_firmware(struct s5p_mfc_dev *dev) } #ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION - s5p_mfc_mem_ion_free(dev, &dev->drm_fw_buf); + mfc_mem_ion_free(dev, &dev->drm_fw_buf); #endif - s5p_mfc_mem_ion_free(dev, &dev->fw_buf); + mfc_mem_ion_free(dev, &dev->fw_buf); return 0; } diff --git a/drivers/media/platform/exynos/mfc/mfc_buf.h b/drivers/media/platform/exynos/mfc/mfc_buf.h index ef5892320e89..f5aa63f85170 100644 --- a/drivers/media/platform/exynos/mfc/mfc_buf.h +++ b/drivers/media/platform/exynos/mfc/mfc_buf.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_buf.h + * drivers/media/platform/exynos/mfc/mfc_buf.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -16,26 +16,26 @@ #include "mfc_common.h" /* Memory allocation */ -int s5p_mfc_alloc_common_context(struct s5p_mfc_dev *dev); -void s5p_mfc_release_common_context(struct s5p_mfc_dev *dev); +int mfc_alloc_common_context(struct mfc_dev *dev); +void mfc_release_common_context(struct mfc_dev *dev); -int s5p_mfc_alloc_instance_context(struct s5p_mfc_ctx *ctx); -void s5p_mfc_release_instance_context(struct s5p_mfc_ctx *ctx); +int mfc_alloc_instance_context(struct mfc_ctx *ctx); +void mfc_release_instance_context(struct mfc_ctx *ctx); -int s5p_mfc_alloc_codec_buffers(struct s5p_mfc_ctx *ctx); -void s5p_mfc_release_codec_buffers(struct s5p_mfc_ctx *ctx); +int mfc_alloc_codec_buffers(struct mfc_ctx *ctx); +void mfc_release_codec_buffers(struct mfc_ctx *ctx); -int s5p_mfc_alloc_enc_roi_buffer(struct s5p_mfc_ctx *ctx); -void s5p_mfc_release_enc_roi_buffer(struct s5p_mfc_ctx *ctx); +int mfc_alloc_enc_roi_buffer(struct mfc_ctx *ctx); +void mfc_release_enc_roi_buffer(struct mfc_ctx *ctx); -int s5p_mfc_otf_alloc_stream_buf(struct s5p_mfc_ctx *ctx); -void s5p_mfc_otf_release_stream_buf(struct s5p_mfc_ctx *ctx); +int mfc_otf_alloc_stream_buf(struct mfc_ctx *ctx); +void mfc_otf_release_stream_buf(struct mfc_ctx *ctx); -int s5p_mfc_alloc_firmware(struct s5p_mfc_dev *dev); -int s5p_mfc_load_firmware(struct s5p_mfc_dev *dev); -int s5p_mfc_release_firmware(struct s5p_mfc_dev *dev); +int mfc_alloc_firmware(struct mfc_dev *dev); +int mfc_load_firmware(struct mfc_dev *dev); +int mfc_release_firmware(struct mfc_dev *dev); -int s5p_mfc_alloc_dbg_info_buffer(struct s5p_mfc_dev *dev); -int s5p_mfc_release_dbg_info_buffer(struct s5p_mfc_dev *dev); +int mfc_alloc_dbg_info_buffer(struct mfc_dev *dev); +int mfc_release_dbg_info_buffer(struct mfc_dev *dev); #endif /* __MFC_BUF_H */ diff --git a/drivers/media/platform/exynos/mfc/mfc_cal.c b/drivers/media/platform/exynos/mfc/mfc_cal.c index 78a2af0d38f3..56f9a1c6fee6 100644 --- a/drivers/media/platform/exynos/mfc/mfc_cal.c +++ b/drivers/media/platform/exynos/mfc/mfc_cal.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_cal.c + * drivers/media/platform/exynos/mfc/mfc_cal.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -16,7 +16,7 @@ #include "mfc_pm.h" /* Reset the device */ -int s5p_mfc_reset_mfc(struct s5p_mfc_dev *dev) +int mfc_reset_mfc(struct mfc_dev *dev) { int i; @@ -28,39 +28,39 @@ int s5p_mfc_reset_mfc(struct s5p_mfc_dev *dev) } /* Zero Initialization of MFC registers */ - MFC_WRITEL(0, S5P_FIMV_RISC2HOST_CMD); - MFC_WRITEL(0, S5P_FIMV_HOST2RISC_CMD); - MFC_WRITEL(0, S5P_FIMV_FW_VERSION); + MFC_WRITEL(0, MFC_REG_RISC2HOST_CMD); + MFC_WRITEL(0, MFC_REG_HOST2RISC_CMD); + MFC_WRITEL(0, MFC_REG_FW_VERSION); - for (i = 0; i < S5P_FIMV_REG_CLEAR_COUNT; i++) - MFC_WRITEL(0, S5P_FIMV_REG_CLEAR_BEGIN + (i*4)); + for (i = 0; i < MFC_REG_REG_CLEAR_COUNT; i++) + MFC_WRITEL(0, MFC_REG_REG_CLEAR_BEGIN + (i*4)); - MFC_WRITEL(0x1FFF, S5P_FIMV_MFC_RESET); - MFC_WRITEL(0, S5P_FIMV_MFC_RESET); + MFC_WRITEL(0x1FFF, MFC_REG_MFC_RESET); + MFC_WRITEL(0, MFC_REG_MFC_RESET); mfc_debug_leave(); return 0; } -void s5p_mfc_set_risc_base_addr(struct s5p_mfc_dev *dev, +void mfc_set_risc_base_addr(struct mfc_dev *dev, enum mfc_buf_usage_type buf_type) { - struct s5p_mfc_special_buf *fw_buf; + struct mfc_special_buf *fw_buf; fw_buf = &dev->fw_buf; if (buf_type == MFCBUF_DRM) fw_buf = &dev->drm_fw_buf; - MFC_WRITEL(fw_buf->daddr, S5P_FIMV_RISC_BASE_ADDRESS); + MFC_WRITEL(fw_buf->daddr, MFC_REG_RISC_BASE_ADDRESS); mfc_debug(2, "[MEMINFO][F/W] %s Base Address : %#x\n", buf_type == MFCBUF_DRM ? "DRM" : "NORMAL", fw_buf->daddr); MFC_TRACE_DEV("%s F/W Base Address : %#x\n", buf_type == MFCBUF_DRM ? "DRM" : "NORMAL", fw_buf->daddr); } -void s5p_mfc_cmd_host2risc(struct s5p_mfc_dev *dev, int cmd) +void mfc_cmd_host2risc(struct mfc_dev *dev, int cmd) { mfc_debug(1, "Issue the command: %d\n", cmd); MFC_TRACE_DEV(">> CMD : %d, (dev:0x%lx, bits:%lx, owned:%d, wl:%d, trans:%d)\n", @@ -69,30 +69,30 @@ void s5p_mfc_cmd_host2risc(struct s5p_mfc_dev *dev, int cmd) trace_mfc_frame_start(dev->curr_ctx, cmd, 0, 0); /* Reset RISC2HOST command except nal q stop command */ - if (cmd != S5P_FIMV_H2R_CMD_STOP_QUEUE) - MFC_WRITEL(0x0, S5P_FIMV_RISC2HOST_CMD); + if (cmd != MFC_REG_H2R_CMD_STOP_QUEUE) + MFC_WRITEL(0x0, MFC_REG_RISC2HOST_CMD); /* Start the timeout watchdog */ - if ((cmd != S5P_FIMV_H2R_CMD_NAL_QUEUE) && (cmd != S5P_FIMV_H2R_CMD_STOP_QUEUE)) - s5p_mfc_watchdog_start_tick(dev); + if ((cmd != MFC_REG_H2R_CMD_NAL_QUEUE) && (cmd != MFC_REG_H2R_CMD_STOP_QUEUE)) + mfc_watchdog_start_tick(dev); if (dbg_enable) { /* For FW debugging */ - s5p_mfc_dbg_set_addr(dev); - s5p_mfc_dbg_enable(dev); + mfc_dbg_set_addr(dev); + mfc_dbg_enable(dev); } /* Issue the command */ - MFC_WRITEL(cmd, S5P_FIMV_HOST2RISC_CMD); - MFC_WRITEL(0x1, S5P_FIMV_HOST2RISC_INT); + MFC_WRITEL(cmd, MFC_REG_HOST2RISC_CMD); + MFC_WRITEL(0x1, MFC_REG_HOST2RISC_INT); } /* Check whether HW interrupt has occurred or not */ -int s5p_mfc_check_risc2host(struct s5p_mfc_dev *dev) +int mfc_check_risc2host(struct mfc_dev *dev) { - if (s5p_mfc_pm_get_pwr_ref_cnt(dev) && s5p_mfc_pm_get_clk_ref_cnt(dev)) { - if (MFC_READL(S5P_FIMV_RISC2HOST_INT)) - return MFC_READL(S5P_FIMV_RISC2HOST_CMD); + if (mfc_pm_get_pwr_ref_cnt(dev) && mfc_pm_get_clk_ref_cnt(dev)) { + if (MFC_READL(MFC_REG_RISC2HOST_INT)) + return MFC_READL(MFC_REG_RISC2HOST_CMD); else return 0; } diff --git a/drivers/media/platform/exynos/mfc/mfc_cal.h b/drivers/media/platform/exynos/mfc/mfc_cal.h index 7ea31cb8cfec..7bed92ca4370 100644 --- a/drivers/media/platform/exynos/mfc/mfc_cal.h +++ b/drivers/media/platform/exynos/mfc/mfc_cal.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_cal.h + * drivers/media/platform/exynos/mfc/mfc_cal.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -20,21 +20,21 @@ #include "mfc_utils.h" -#define s5p_mfc_get_int_reason() (MFC_READL(S5P_FIMV_RISC2HOST_CMD) \ - & S5P_FIMV_RISC2HOST_CMD_MASK) -#define s5p_mfc_clear_int_sfr() \ +#define mfc_get_int_reason() (MFC_READL(MFC_REG_RISC2HOST_CMD) \ + & MFC_REG_RISC2HOST_CMD_MASK) +#define mfc_clear_int_sfr() \ do { \ - MFC_WRITEL(0, S5P_FIMV_RISC2HOST_CMD); \ - MFC_WRITEL(0, S5P_FIMV_RISC2HOST_INT); \ + MFC_WRITEL(0, MFC_REG_RISC2HOST_CMD); \ + MFC_WRITEL(0, MFC_REG_RISC2HOST_INT); \ } while (0) -static inline int s5p_mfc_stop_bus(struct s5p_mfc_dev *dev) +static inline int mfc_stop_bus(struct mfc_dev *dev) { unsigned int status; unsigned long timeout; /* Reset */ - MFC_WRITEL(0x1, S5P_FIMV_MFC_BUS_RESET_CTRL); + MFC_WRITEL(0x1, MFC_REG_MFC_BUS_RESET_CTRL); timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT); /* Check bus status */ @@ -43,32 +43,32 @@ static inline int s5p_mfc_stop_bus(struct s5p_mfc_dev *dev) mfc_err_dev("Timeout while resetting MFC.\n"); return -EIO; } - status = MFC_READL(S5P_FIMV_MFC_BUS_RESET_CTRL); + status = MFC_READL(MFC_REG_MFC_BUS_RESET_CTRL); } while ((status & 0x2) == 0); return 0; } -static inline void s5p_mfc_start_bus(struct s5p_mfc_dev *dev) +static inline void mfc_start_bus(struct mfc_dev *dev) { int val; - val = MFC_READL(S5P_FIMV_MFC_BUS_RESET_CTRL); + val = MFC_READL(MFC_REG_MFC_BUS_RESET_CTRL); val &= ~(0x1); - MFC_WRITEL(val, S5P_FIMV_MFC_BUS_RESET_CTRL); + MFC_WRITEL(val, MFC_REG_MFC_BUS_RESET_CTRL); } -static inline void s5p_mfc_risc_on(struct s5p_mfc_dev *dev) +static inline void mfc_risc_on(struct mfc_dev *dev) { - s5p_mfc_clean_dev_int_flags(dev); + mfc_clean_dev_int_flags(dev); - MFC_WRITEL(0x1, S5P_FIMV_RISC_ON); - MFC_WRITEL(0x0, S5P_FIMV_MFC_OFF); + MFC_WRITEL(0x1, MFC_REG_RISC_ON); + MFC_WRITEL(0x0, MFC_REG_MFC_OFF); mfc_debug(1, "RISC_ON\n"); MFC_TRACE_DEV(">> RISC ON\n"); } -static inline void s5p_mfc_risc_off(struct s5p_mfc_dev *dev) +static inline void mfc_risc_off(struct mfc_dev *dev) { unsigned int status; unsigned long timeout; @@ -80,33 +80,33 @@ static inline void s5p_mfc_risc_off(struct s5p_mfc_dev *dev) mfc_err_dev("Timeout while pendng clear\n"); mfc_err_dev("MFC access pending state: %#x\n", status); mfc_err_dev("MFC access pending R: %#x, W: %#x\n", - MFC_READL(S5P_FIMV_MFC_RPEND), - MFC_READL(S5P_FIMV_MFC_WPEND)); + MFC_READL(MFC_REG_MFC_RPEND), + MFC_READL(MFC_REG_MFC_WPEND)); break; } - status = MFC_READL(S5P_FIMV_MFC_BUS_STATUS); + status = MFC_READL(MFC_REG_MFC_BUS_STATUS); } while (status != 0); - MFC_WRITEL(0x0, S5P_FIMV_RISC_ON); + MFC_WRITEL(0x0, MFC_REG_RISC_ON); } -static inline void s5p_mfc_mfc_off(struct s5p_mfc_dev *dev) +static inline void mfc_mfc_off(struct mfc_dev *dev) { mfc_info_dev("MFC h/w state: %d\n", - MFC_READL(S5P_FIMV_MFC_STATE) & 0x7); - MFC_WRITEL(0x1, S5P_FIMV_MFC_OFF); + MFC_READL(MFC_REG_MFC_STATE) & 0x7); + MFC_WRITEL(0x1, MFC_REG_MFC_OFF); } -static inline void s5p_mfc_enable_all_clocks(struct s5p_mfc_dev *dev) +static inline void mfc_enable_all_clocks(struct mfc_dev *dev) { /* Enable all FW clock gating */ - MFC_WRITEL(0xFFFFFFFF, S5P_FIMV_MFC_FW_CLOCK); + MFC_WRITEL(0xFFFFFFFF, MFC_REG_MFC_FW_CLOCK); } -int s5p_mfc_reset_mfc(struct s5p_mfc_dev *dev); -void s5p_mfc_set_risc_base_addr(struct s5p_mfc_dev *dev, +int mfc_reset_mfc(struct mfc_dev *dev); +void mfc_set_risc_base_addr(struct mfc_dev *dev, enum mfc_buf_usage_type buf_type); -void s5p_mfc_cmd_host2risc(struct s5p_mfc_dev *dev, int cmd); -int s5p_mfc_check_risc2host(struct s5p_mfc_dev *dev); +void mfc_cmd_host2risc(struct mfc_dev *dev, int cmd); +int mfc_check_risc2host(struct mfc_dev *dev); #endif /* __MFC_CAL_H */ diff --git a/drivers/media/platform/exynos/mfc/mfc_cmd.c b/drivers/media/platform/exynos/mfc/mfc_cmd.c index d0477cd84bdf..87dad6691230 100644 --- a/drivers/media/platform/exynos/mfc/mfc_cmd.c +++ b/drivers/media/platform/exynos/mfc/mfc_cmd.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_cmd.c + * drivers/media/platform/exynos/mfc/mfc_cmd.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -21,11 +21,11 @@ #include "mfc_utils.h" #include "mfc_buf.h" -int s5p_mfc_cmd_sys_init(struct s5p_mfc_dev *dev, +int mfc_cmd_sys_init(struct mfc_dev *dev, enum mfc_buf_usage_type buf_type) { - struct s5p_mfc_ctx_buf_size *buf_size; - struct s5p_mfc_special_buf *ctx_buf; + struct mfc_ctx_buf_size *buf_size; + struct mfc_special_buf *ctx_buf; mfc_debug_enter(); @@ -34,7 +34,7 @@ int s5p_mfc_cmd_sys_init(struct s5p_mfc_dev *dev, return -EINVAL; } - s5p_mfc_clean_dev_int_flags(dev); + mfc_clean_dev_int_flags(dev); buf_size = dev->variant->buf_size->ctx_buf; ctx_buf = &dev->common_ctx_buf; @@ -42,40 +42,40 @@ int s5p_mfc_cmd_sys_init(struct s5p_mfc_dev *dev, if (buf_type == MFCBUF_DRM) ctx_buf = &dev->drm_common_ctx_buf; #endif - MFC_WRITEL(ctx_buf->daddr, S5P_FIMV_CONTEXT_MEM_ADDR); - MFC_WRITEL(buf_size->dev_ctx, S5P_FIMV_CONTEXT_MEM_SIZE); + MFC_WRITEL(ctx_buf->daddr, MFC_REG_CONTEXT_MEM_ADDR); + MFC_WRITEL(buf_size->dev_ctx, MFC_REG_CONTEXT_MEM_SIZE); - s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_SYS_INIT); + mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_SYS_INIT); mfc_debug_leave(); return 0; } -void s5p_mfc_cmd_sleep(struct s5p_mfc_dev *dev) +void mfc_cmd_sleep(struct mfc_dev *dev) { mfc_debug_enter(); - s5p_mfc_clean_dev_int_flags(dev); - s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_SLEEP); + mfc_clean_dev_int_flags(dev); + mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_SLEEP); mfc_debug_leave(); } -void s5p_mfc_cmd_wakeup(struct s5p_mfc_dev *dev) +void mfc_cmd_wakeup(struct mfc_dev *dev) { mfc_debug_enter(); - s5p_mfc_clean_dev_int_flags(dev); - s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_WAKEUP); + mfc_clean_dev_int_flags(dev); + mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_WAKEUP); mfc_debug_leave(); } /* Open a new instance and get its number */ -int s5p_mfc_cmd_open_inst(struct s5p_mfc_ctx *ctx) +int mfc_cmd_open_inst(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev; + struct mfc_dev *dev; mfc_debug_enter(); @@ -86,13 +86,13 @@ int s5p_mfc_cmd_open_inst(struct s5p_mfc_ctx *ctx) dev = ctx->dev; mfc_debug(2, "Requested codec mode: %d\n", ctx->codec_mode); - MFC_WRITEL(ctx->codec_mode, S5P_FIMV_CODEC_TYPE); - MFC_WRITEL(ctx->instance_ctx_buf.daddr, S5P_FIMV_CONTEXT_MEM_ADDR); - MFC_WRITEL(ctx->instance_ctx_buf.size, S5P_FIMV_CONTEXT_MEM_SIZE); + MFC_WRITEL(ctx->codec_mode, MFC_REG_CODEC_TYPE); + MFC_WRITEL(ctx->instance_ctx_buf.daddr, MFC_REG_CONTEXT_MEM_ADDR); + MFC_WRITEL(ctx->instance_ctx_buf.size, MFC_REG_CONTEXT_MEM_SIZE); if (ctx->type == MFCINST_DECODER) - MFC_WRITEL(ctx->dec_priv->crc_enable, S5P_FIMV_D_CRC_CTRL); + MFC_WRITEL(ctx->dec_priv->crc_enable, MFC_REG_D_CRC_CTRL); - s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_OPEN_INSTANCE); + mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_OPEN_INSTANCE); mfc_debug_leave(); @@ -100,9 +100,9 @@ int s5p_mfc_cmd_open_inst(struct s5p_mfc_ctx *ctx) } /* Close instance */ -int s5p_mfc_cmd_close_inst(struct s5p_mfc_ctx *ctx) +int mfc_cmd_close_inst(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev; + struct mfc_dev *dev; mfc_debug_enter(); @@ -112,47 +112,47 @@ int s5p_mfc_cmd_close_inst(struct s5p_mfc_ctx *ctx) } dev = ctx->dev; - MFC_WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID); + MFC_WRITEL(ctx->inst_no, MFC_REG_INSTANCE_ID); - s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_CLOSE_INSTANCE); + mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_CLOSE_INSTANCE); mfc_debug_leave(); return 0; } -int s5p_mfc_cmd_dpb_flush(struct s5p_mfc_ctx *ctx) +int mfc_cmd_dpb_flush(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; if (ON_RES_CHANGE(ctx)) mfc_err_ctx("dpb flush on res change(state:%d)\n", ctx->state); - s5p_mfc_clean_ctx_int_flags(ctx); + mfc_clean_ctx_int_flags(ctx); - MFC_WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID); - s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_DPB_FLUSH); + MFC_WRITEL(ctx->inst_no, MFC_REG_INSTANCE_ID); + mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_DPB_FLUSH); return 0; } -int s5p_mfc_cmd_cache_flush(struct s5p_mfc_dev *dev) +int mfc_cmd_cache_flush(struct mfc_dev *dev) { if (!dev) { mfc_err_dev("no mfc device to run\n"); return -EINVAL; } - s5p_mfc_clean_dev_int_flags(dev); - s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_CACHE_FLUSH); + mfc_clean_dev_int_flags(dev); + mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_CACHE_FLUSH); return 0; } -int s5p_mfc_cmd_dec_init_buffers(struct s5p_mfc_ctx *ctx) +int mfc_cmd_dec_init_buffers(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev; - struct s5p_mfc_dec *dec; + struct mfc_dev *dev; + struct mfc_dec *dec; unsigned int reg = 0, pix_val; int ret; @@ -198,47 +198,47 @@ int s5p_mfc_cmd_dec_init_buffers(struct s5p_mfc_ctx *ctx) pix_val = 0; break; } - reg = MFC_READL(S5P_FIMV_PIXEL_FORMAT); + reg = MFC_READL(MFC_REG_PIXEL_FORMAT); reg &= ~(0xF); reg |= pix_val & 0xF; - MFC_WRITEL(reg, S5P_FIMV_PIXEL_FORMAT); + MFC_WRITEL(reg, MFC_REG_PIXEL_FORMAT); mfc_debug(2, "[FRAME] pixel format: %d, mem_type_10bit should be fixed on SEQ_START(reg: %#x)\n", pix_val, reg); - s5p_mfc_clean_ctx_int_flags(ctx); - ret = s5p_mfc_set_dec_codec_buffers(ctx); + mfc_clean_ctx_int_flags(ctx); + ret = mfc_set_dec_codec_buffers(ctx); if (ret) { mfc_info_ctx("isn't enough codec buffer size, re-alloc!\n"); if (dev->has_mmcache && dev->mmcache.is_on_status) - s5p_mfc_invalidate_mmcache(dev); + mfc_invalidate_mmcache(dev); - s5p_mfc_release_codec_buffers(ctx); - ret = s5p_mfc_alloc_codec_buffers(ctx); + mfc_release_codec_buffers(ctx); + ret = mfc_alloc_codec_buffers(ctx); if (ret) { mfc_err_ctx("Failed to allocate decoding buffers\n"); return ret; } - ret = s5p_mfc_set_dec_codec_buffers(ctx); + ret = mfc_set_dec_codec_buffers(ctx); if (ret) { mfc_err_ctx("Failed to alloc frame mem\n"); return ret; } } - MFC_WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID); + MFC_WRITEL(ctx->inst_no, MFC_REG_INSTANCE_ID); if (sfr_dump & MFC_DUMP_DEC_INIT_BUFS) call_dop(dev, dump_regs, dev); - s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_INIT_BUFFERS); + mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_INIT_BUFFERS); return ret; } -int s5p_mfc_cmd_enc_init_buffers(struct s5p_mfc_ctx *ctx) +int mfc_cmd_enc_init_buffers(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev; + struct mfc_dev *dev; int ret; dev = ctx->dev; @@ -253,40 +253,40 @@ int s5p_mfc_cmd_enc_init_buffers(struct s5p_mfc_ctx *ctx) */ if (!ctx->codec_buffer_allocated) { mfc_info_ctx("there isn't codec buffer, re-alloc!\n"); - ret = s5p_mfc_alloc_codec_buffers(ctx); + ret = mfc_alloc_codec_buffers(ctx); if (ret) { mfc_err_ctx("Failed to allocate encoding buffers\n"); return ret; } } - s5p_mfc_clean_ctx_int_flags(ctx); - ret = s5p_mfc_set_enc_codec_buffers(ctx); + mfc_clean_ctx_int_flags(ctx); + ret = mfc_set_enc_codec_buffers(ctx); if (ret) { mfc_info_ctx("isn't enough codec buffer size, re-alloc!\n"); if (dev->has_mmcache && dev->mmcache.is_on_status) - s5p_mfc_invalidate_mmcache(dev); + mfc_invalidate_mmcache(dev); - s5p_mfc_release_codec_buffers(ctx); - ret = s5p_mfc_alloc_codec_buffers(ctx); + mfc_release_codec_buffers(ctx); + ret = mfc_alloc_codec_buffers(ctx); if (ret) { mfc_err_ctx("Failed to allocate encoding buffers\n"); return ret; } - ret = s5p_mfc_set_enc_codec_buffers(ctx); + ret = mfc_set_enc_codec_buffers(ctx); if (ret) { mfc_err_ctx("Failed to set enc codec buffers\n"); return ret; } } - MFC_WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID); + MFC_WRITEL(ctx->inst_no, MFC_REG_INSTANCE_ID); if (sfr_dump & MFC_DUMP_ENC_INIT_BUFS) call_dop(dev, dump_regs, dev); - s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_INIT_BUFFERS); + mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_INIT_BUFFERS); return ret; } diff --git a/drivers/media/platform/exynos/mfc/mfc_cmd.h b/drivers/media/platform/exynos/mfc/mfc_cmd.h index ebbd9705191c..2f5b79584424 100644 --- a/drivers/media/platform/exynos/mfc/mfc_cmd.h +++ b/drivers/media/platform/exynos/mfc/mfc_cmd.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_cmd.h + * drivers/media/platform/exynos/mfc/mfc_cmd.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -15,15 +15,15 @@ #include "mfc_common.h" -int s5p_mfc_cmd_sys_init(struct s5p_mfc_dev *dev, +int mfc_cmd_sys_init(struct mfc_dev *dev, enum mfc_buf_usage_type buf_type); -void s5p_mfc_cmd_sleep(struct s5p_mfc_dev *dev); -void s5p_mfc_cmd_wakeup(struct s5p_mfc_dev *dev); -int s5p_mfc_cmd_open_inst(struct s5p_mfc_ctx *ctx); -int s5p_mfc_cmd_close_inst(struct s5p_mfc_ctx *ctx); -int s5p_mfc_cmd_dpb_flush(struct s5p_mfc_ctx *ctx); -int s5p_mfc_cmd_cache_flush(struct s5p_mfc_dev *dev); -int s5p_mfc_cmd_dec_init_buffers(struct s5p_mfc_ctx *ctx); -int s5p_mfc_cmd_enc_init_buffers(struct s5p_mfc_ctx *ctx); +void mfc_cmd_sleep(struct mfc_dev *dev); +void mfc_cmd_wakeup(struct mfc_dev *dev); +int mfc_cmd_open_inst(struct mfc_ctx *ctx); +int mfc_cmd_close_inst(struct mfc_ctx *ctx); +int mfc_cmd_dpb_flush(struct mfc_ctx *ctx); +int mfc_cmd_cache_flush(struct mfc_dev *dev); +int mfc_cmd_dec_init_buffers(struct mfc_ctx *ctx); +int mfc_cmd_enc_init_buffers(struct mfc_ctx *ctx); #endif /* __MFC_CMD_H */ diff --git a/drivers/media/platform/exynos/mfc/mfc_common.h b/drivers/media/platform/exynos/mfc/mfc_common.h index 37e99fedf840..c45acb36903e 100644 --- a/drivers/media/platform/exynos/mfc/mfc_common.h +++ b/drivers/media/platform/exynos/mfc/mfc_common.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_common.h + * drivers/media/platform/exynos/mfc/mfc_common.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -50,7 +50,7 @@ #define MFC_INT_TIMEOUT_CNT 2 /* This value guarantees 299.4msec ~ 2.25sec according to MFC clock (668MHz ~ 89MHz) - * releated with S5P_FIMV_DEC_TIMEOUT_VALUE */ + * releated with MFC_REG_DEC_TIMEOUT_VALUE */ #define MFC_TIMEOUT_VALUE 200000000 #define NUM_MPEG4_LF_BUF 2 @@ -77,10 +77,10 @@ #define MFC_CONCEAL_COLOR 0x8020000 #define vb_to_mfc_buf(x) \ - container_of(x, struct s5p_mfc_buf, vb.vb2_buf) + container_of(x, struct mfc_buf, vb.vb2_buf) #define fh_to_mfc_ctx(x) \ - container_of(x, struct s5p_mfc_ctx, fh) + container_of(x, struct mfc_ctx, fh) #define call_bop(b, op, args...) \ (b->op ? b->op(args) : 0) @@ -112,28 +112,28 @@ (n == EXYNOS_VIDEONODE_MFC_ENC_OTF_DRM)) /* Decoder codec mode check */ -#define IS_H264_DEC(ctx) ((ctx)->codec_mode == S5P_FIMV_CODEC_H264_DEC) -#define IS_H264_MVC_DEC(ctx) ((ctx)->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC) -#define IS_MPEG4_DEC(ctx) ((ctx)->codec_mode == S5P_FIMV_CODEC_MPEG4_DEC) -#define IS_FIMV1_DEC(ctx) ((ctx)->codec_mode == S5P_FIMV_CODEC_FIMV1_DEC) -#define IS_FIMV2_DEC(ctx) ((ctx)->codec_mode == S5P_FIMV_CODEC_FIMV2_DEC) -#define IS_FIMV3_DEC(ctx) ((ctx)->codec_mode == S5P_FIMV_CODEC_FIMV3_DEC) -#define IS_FIMV4_DEC(ctx) ((ctx)->codec_mode == S5P_FIMV_CODEC_FIMV4_DEC) -#define IS_VC1_DEC(ctx) ((ctx)->codec_mode == S5P_FIMV_CODEC_VC1_DEC) -#define IS_VC1_RCV_DEC(ctx) ((ctx)->codec_mode == S5P_FIMV_CODEC_VC1_RCV_DEC) -#define IS_MPEG2_DEC(ctx) ((ctx)->codec_mode == S5P_FIMV_CODEC_MPEG2_DEC) -#define IS_HEVC_DEC(ctx) ((ctx)->codec_mode == S5P_FIMV_CODEC_HEVC_DEC) -#define IS_VP9_DEC(ctx) ((ctx)->codec_mode == S5P_FIMV_CODEC_VP9_DEC) -#define IS_BPG_DEC(ctx) ((ctx)->codec_mode == S5P_FIMV_CODEC_BPG_DEC) +#define IS_H264_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_H264_DEC) +#define IS_H264_MVC_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_H264_MVC_DEC) +#define IS_MPEG4_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_MPEG4_DEC) +#define IS_FIMV1_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_FIMV1_DEC) +#define IS_FIMV2_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_FIMV2_DEC) +#define IS_FIMV3_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_FIMV3_DEC) +#define IS_FIMV4_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_FIMV4_DEC) +#define IS_VC1_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_VC1_DEC) +#define IS_VC1_RCV_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_VC1_RCV_DEC) +#define IS_MPEG2_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_MPEG2_DEC) +#define IS_HEVC_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_HEVC_DEC) +#define IS_VP9_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_VP9_DEC) +#define IS_BPG_DEC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_BPG_DEC) /* Encoder codec mode check */ -#define IS_H264_ENC(ctx) ((ctx)->codec_mode == S5P_FIMV_CODEC_H264_ENC) -#define IS_MPEG4_ENC(ctx) ((ctx)->codec_mode == S5P_FIMV_CODEC_MPEG4_ENC) -#define IS_H263_ENC(ctx) ((ctx)->codec_mode == S5P_FIMV_CODEC_H263_ENC) -#define IS_VP8_ENC(ctx) ((ctx)->codec_mode == S5P_FIMV_CODEC_VP8_ENC) -#define IS_HEVC_ENC(ctx) ((ctx)->codec_mode == S5P_FIMV_CODEC_HEVC_ENC) -#define IS_VP9_ENC(ctx) ((ctx)->codec_mode == S5P_FIMV_CODEC_VP9_ENC) -#define IS_BPG_ENC(ctx) ((ctx)->codec_mode == S5P_FIMV_CODEC_BPG_ENC) +#define IS_H264_ENC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_H264_ENC) +#define IS_MPEG4_ENC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_MPEG4_ENC) +#define IS_H263_ENC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_H263_ENC) +#define IS_VP8_ENC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_VP8_ENC) +#define IS_HEVC_ENC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_HEVC_ENC) +#define IS_VP9_ENC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_VP9_ENC) +#define IS_BPG_ENC(ctx) ((ctx)->codec_mode == MFC_REG_CODEC_BPG_ENC) #define CODEC_NOT_CODED(ctx) (IS_MPEG4_DEC(ctx) || IS_VC1_DEC(ctx) || IS_VC1_RCV_DEC(ctx)) #define CODEC_INTERLACED(ctx) (IS_H264_DEC(ctx) || IS_H264_MVC_DEC(ctx) || \ diff --git a/drivers/media/platform/exynos/mfc/mfc_ctrl.c b/drivers/media/platform/exynos/mfc/mfc_ctrl.c index 10c2a324bebe..cef16fa01ba0 100644 --- a/drivers/media/platform/exynos/mfc/mfc_ctrl.c +++ b/drivers/media/platform/exynos/mfc/mfc_ctrl.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_ctrl.c + * drivers/media/platform/exynos/mfc/mfc_ctrl.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -24,7 +24,7 @@ #include "mfc_utils.h" /* Initialize hardware */ -static int mfc_init_hw(struct s5p_mfc_dev *dev, enum mfc_buf_usage_type buf_type) +static int __mfc_init_hw(struct mfc_dev *dev, enum mfc_buf_usage_type buf_type) { int fw_ver; int ret = 0; @@ -51,14 +51,14 @@ static int mfc_init_hw(struct s5p_mfc_dev *dev, enum mfc_buf_usage_type buf_type else if (buf_type == MFCBUF_DRM) dev->curr_ctx_is_drm = 1; - ret = s5p_mfc_pm_clock_on(dev); + ret = mfc_pm_clock_on(dev); if (ret) { mfc_err_dev("Failed to enable clock before reset(%d)\n", ret); dev->curr_ctx_is_drm = curr_ctx_is_drm_backup; return ret; } - ret = s5p_mfc_reset_mfc(dev); + ret = mfc_reset_mfc(dev); if (ret) { mfc_err_dev("Failed to reset MFC - timeout\n"); goto err_init_hw; @@ -66,36 +66,36 @@ static int mfc_init_hw(struct s5p_mfc_dev *dev, enum mfc_buf_usage_type buf_type mfc_debug(2, "Done MFC reset...\n"); /* 1. Set DRAM base Addr */ - s5p_mfc_set_risc_base_addr(dev, buf_type); + mfc_set_risc_base_addr(dev, buf_type); /* 2. Release reset signal to the RISC */ - s5p_mfc_risc_on(dev); + mfc_risc_on(dev); mfc_debug(2, "Will now wait for completion of firmware transfer\n"); - if (s5p_mfc_wait_for_done_dev(dev, S5P_FIMV_R2H_CMD_FW_STATUS_RET)) { + if (mfc_wait_for_done_dev(dev, MFC_REG_R2H_CMD_FW_STATUS_RET)) { mfc_err_dev("Failed to RISC_ON\n"); - s5p_mfc_clean_dev_int_flags(dev); + mfc_clean_dev_int_flags(dev); ret = -EIO; goto err_init_hw; } /* 3. Initialize firmware */ - ret = s5p_mfc_cmd_sys_init(dev, buf_type); + ret = mfc_cmd_sys_init(dev, buf_type); if (ret) { mfc_err_dev("Failed to send command to MFC - timeout\n"); goto err_init_hw; } mfc_debug(2, "Ok, now will write a command to init the system\n"); - if (s5p_mfc_wait_for_done_dev(dev, S5P_FIMV_R2H_CMD_SYS_INIT_RET)) { + if (mfc_wait_for_done_dev(dev, MFC_REG_R2H_CMD_SYS_INIT_RET)) { mfc_err_dev("Failed to SYS_INIT\n"); - s5p_mfc_clean_dev_int_flags(dev); + mfc_clean_dev_int_flags(dev); ret = -EIO; goto err_init_hw; } dev->int_condition = 0; - if (dev->int_err != 0 || dev->int_reason != S5P_FIMV_R2H_CMD_SYS_INIT_RET) { + if (dev->int_err != 0 || dev->int_reason != MFC_REG_R2H_CMD_SYS_INIT_RET) { /* Failure. */ mfc_err_dev("Failed to init firmware - error: %d, int: %d\n", dev->int_err, dev->int_reason); @@ -103,21 +103,21 @@ static int mfc_init_hw(struct s5p_mfc_dev *dev, enum mfc_buf_usage_type buf_type goto err_init_hw; } - dev->fw.fimv_info = s5p_mfc_get_fimv_info(); + dev->fw.fimv_info = mfc_get_fimv_info(); if (dev->fw.fimv_info != 'D' && dev->fw.fimv_info != 'E') dev->fw.fimv_info = 'N'; mfc_info_dev("[F/W] MFC v%x.%x, %02xyy %02xmm %02xdd (%c)\n", MFC_VER_MAJOR(dev), MFC_VER_MINOR(dev), - s5p_mfc_get_fw_ver_year(), - s5p_mfc_get_fw_ver_month(), - s5p_mfc_get_fw_ver_date(), + mfc_get_fw_ver_year(), + mfc_get_fw_ver_month(), + mfc_get_fw_ver_date(), dev->fw.fimv_info); - dev->fw.date = s5p_mfc_get_fw_ver_all(); + dev->fw.date = mfc_get_fw_ver_all(); /* Check MFC version and F/W version */ - fw_ver = s5p_mfc_get_mfc_version(); + fw_ver = mfc_get_mfc_version(); if (fw_ver != dev->pdata->ip_ver) { mfc_err_dev("Invalid F/W version(0x%x) for MFC H/W(0x%x)\n", fw_ver, dev->pdata->ip_ver); @@ -127,23 +127,23 @@ static int mfc_init_hw(struct s5p_mfc_dev *dev, enum mfc_buf_usage_type buf_type #ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION /* Cache flush for base address change */ - s5p_mfc_cmd_cache_flush(dev); - if (s5p_mfc_wait_for_done_dev(dev, S5P_FIMV_R2H_CMD_CACHE_FLUSH_RET)) { + mfc_cmd_cache_flush(dev); + if (mfc_wait_for_done_dev(dev, MFC_REG_R2H_CMD_CACHE_FLUSH_RET)) { mfc_err_dev("Failed to CACHE_FLUSH\n"); - s5p_mfc_clean_dev_int_flags(dev); + mfc_clean_dev_int_flags(dev); ret = -EIO; goto err_init_hw; } if (buf_type == MFCBUF_DRM && !curr_ctx_is_drm_backup) { - s5p_mfc_pm_clock_off(dev); + mfc_pm_clock_off(dev); dev->curr_ctx_is_drm = curr_ctx_is_drm_backup; - s5p_mfc_pm_clock_on_with_base(dev, MFCBUF_NORMAL); + mfc_pm_clock_on_with_base(dev, MFCBUF_NORMAL); } #endif err_init_hw: - s5p_mfc_pm_clock_off(dev); + mfc_pm_clock_off(dev); dev->curr_ctx_is_drm = curr_ctx_is_drm_backup; mfc_debug_leave(); @@ -151,17 +151,17 @@ err_init_hw: } /* Wrapper : Initialize hardware */ -int s5p_mfc_init_hw(struct s5p_mfc_dev *dev) +int mfc_init_hw(struct mfc_dev *dev) { int ret; - ret = mfc_init_hw(dev, MFCBUF_NORMAL); + ret = __mfc_init_hw(dev, MFCBUF_NORMAL); if (ret) return ret; #ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION if (dev->fw.drm_status) { - ret = mfc_init_hw(dev, MFCBUF_DRM); + ret = __mfc_init_hw(dev, MFCBUF_DRM); if (ret) return ret; } @@ -171,7 +171,7 @@ int s5p_mfc_init_hw(struct s5p_mfc_dev *dev) } /* Deinitialize hardware */ -void s5p_mfc_deinit_hw(struct s5p_mfc_dev *dev) +void mfc_deinit_hw(struct mfc_dev *dev) { int ret; @@ -182,22 +182,22 @@ void s5p_mfc_deinit_hw(struct s5p_mfc_dev *dev) return; } - ret = s5p_mfc_pm_clock_on(dev); + ret = mfc_pm_clock_on(dev); if (ret) { mfc_err_dev("Failed to enable clock before reset(%d)\n", ret); return; } - s5p_mfc_mfc_off(dev); + mfc_mfc_off(dev); - s5p_mfc_pm_clock_off(dev); + mfc_pm_clock_off(dev); mfc_debug(2, "mfc deinit completed\n"); } -int s5p_mfc_sleep(struct s5p_mfc_dev *dev) +int mfc_sleep(struct mfc_dev *dev) { - struct s5p_mfc_ctx *ctx; + struct mfc_ctx *ctx; int ret; int old_state, i; int need_cache_flush = 0; @@ -232,9 +232,9 @@ int s5p_mfc_sleep(struct s5p_mfc_dev *dev) } } old_state = ctx->state; - s5p_mfc_change_state(ctx, MFCINST_ABORT); + mfc_change_state(ctx, MFCINST_ABORT); MFC_TRACE_DEV_HWLOCK("**sleep (ctx:%d)\n", ctx->num); - ret = s5p_mfc_get_hwlock_dev(dev); + ret = mfc_get_hwlock_dev(dev); if (ret < 0) { mfc_err_dev("Failed to get hwlock\n"); mfc_err_dev("dev.hwlock.dev = 0x%lx, bits = 0x%lx, owned_by_irq = %d, wl_count = %d, transfer_owner = %d\n", @@ -246,15 +246,15 @@ int s5p_mfc_sleep(struct s5p_mfc_dev *dev) mfc_info_dev("curr_ctx_is_drm:%d, hwlock.bits:%lu, hwlock.dev:%lu\n", dev->curr_ctx_is_drm, dev->hwlock.bits, dev->hwlock.dev); - s5p_mfc_change_state(ctx, old_state); - s5p_mfc_pm_clock_on(dev); + mfc_change_state(ctx, old_state); + mfc_pm_clock_on(dev); if (need_cache_flush) - s5p_mfc_cache_flush(dev, ctx->is_drm); + mfc_cache_flush(dev, ctx->is_drm); - s5p_mfc_cmd_sleep(dev); + mfc_cmd_sleep(dev); - if (s5p_mfc_wait_for_done_dev(dev, S5P_FIMV_R2H_CMD_SLEEP_RET)) { + if (mfc_wait_for_done_dev(dev, MFC_REG_R2H_CMD_SLEEP_RET)) { mfc_err_dev("Failed to SLEEP\n"); dev->logging_data->cause |= (1 << MFC_CAUSE_FAIL_SLEEP); call_dop(dev, dump_and_stop_always, dev); @@ -262,7 +262,7 @@ int s5p_mfc_sleep(struct s5p_mfc_dev *dev) } dev->int_condition = 0; - if (dev->int_err != 0 || dev->int_reason != S5P_FIMV_R2H_CMD_SLEEP_RET) { + if (dev->int_err != 0 || dev->int_reason != MFC_REG_R2H_CMD_SLEEP_RET) { /* Failure. */ mfc_err_dev("Failed to sleep - error: %d, int: %d\n", dev->int_err, dev->int_reason); @@ -273,15 +273,15 @@ int s5p_mfc_sleep(struct s5p_mfc_dev *dev) dev->sleep = 1; err_mfc_sleep: - s5p_mfc_mfc_off(dev); - s5p_mfc_pm_clock_off(dev); - s5p_mfc_release_hwlock_dev(dev); + mfc_mfc_off(dev); + mfc_pm_clock_off(dev); + mfc_release_hwlock_dev(dev); mfc_debug_leave(); return ret; } -int s5p_mfc_wakeup(struct s5p_mfc_dev *dev) +int mfc_wakeup(struct mfc_dev *dev) { enum mfc_buf_usage_type buf_type; int ret = 0; @@ -295,7 +295,7 @@ int s5p_mfc_wakeup(struct s5p_mfc_dev *dev) mfc_info_dev("curr_ctx_is_drm:%d\n", dev->curr_ctx_is_drm); MFC_TRACE_DEV_HWLOCK("**wakeup\n"); - ret = s5p_mfc_get_hwlock_dev(dev); + ret = mfc_get_hwlock_dev(dev); if (ret < 0) { mfc_err_dev("Failed to get hwlock\n"); mfc_err_dev("dev.hwlock.dev = 0x%lx, bits = 0x%lx, owned_by_irq = %d, wl_count = %d, transfer_owner = %d\n", @@ -309,9 +309,9 @@ int s5p_mfc_wakeup(struct s5p_mfc_dev *dev) /* 0. MFC reset */ mfc_debug(2, "MFC reset...\n"); - s5p_mfc_pm_clock_on(dev); + mfc_pm_clock_on(dev); - ret = s5p_mfc_reset_mfc(dev); + ret = mfc_reset_mfc(dev); if (ret) { mfc_err_dev("Failed to reset MFC - timeout\n"); goto err_mfc_wakeup; @@ -323,13 +323,13 @@ int s5p_mfc_wakeup(struct s5p_mfc_dev *dev) buf_type = MFCBUF_NORMAL; /* 1. Set DRAM base Addr */ - s5p_mfc_set_risc_base_addr(dev, buf_type); + mfc_set_risc_base_addr(dev, buf_type); /* 2. Release reset signal to the RISC */ - s5p_mfc_risc_on(dev); + mfc_risc_on(dev); mfc_debug(2, "Will now wait for completion of firmware transfer\n"); - if (s5p_mfc_wait_for_done_dev(dev, S5P_FIMV_R2H_CMD_FW_STATUS_RET)) { + if (mfc_wait_for_done_dev(dev, MFC_REG_R2H_CMD_FW_STATUS_RET)) { mfc_err_dev("Failed to RISC_ON\n"); dev->logging_data->cause |= (1 << MFC_CAUSE_FAIL_RISC_ON); call_dop(dev, dump_and_stop_always, dev); @@ -337,10 +337,10 @@ int s5p_mfc_wakeup(struct s5p_mfc_dev *dev) } mfc_debug(2, "Ok, now will write a command to wakeup the system\n"); - s5p_mfc_cmd_wakeup(dev); + mfc_cmd_wakeup(dev); mfc_debug(2, "Will now wait for completion of firmware wake up\n"); - if (s5p_mfc_wait_for_done_dev(dev, S5P_FIMV_R2H_CMD_WAKEUP_RET)) { + if (mfc_wait_for_done_dev(dev, MFC_REG_R2H_CMD_WAKEUP_RET)) { mfc_err_dev("Failed to WAKEUP\n"); dev->logging_data->cause |= (1 << MFC_CAUSE_FAIL_WAKEUP); call_dop(dev, dump_and_stop_always, dev); @@ -348,7 +348,7 @@ int s5p_mfc_wakeup(struct s5p_mfc_dev *dev) } dev->int_condition = 0; - if (dev->int_err != 0 || dev->int_reason != S5P_FIMV_R2H_CMD_WAKEUP_RET) { + if (dev->int_err != 0 || dev->int_reason != MFC_REG_R2H_CMD_WAKEUP_RET) { /* Failure. */ mfc_err_dev("Failed to wakeup - error: %d, int: %d\n", dev->int_err, dev->int_reason); @@ -357,9 +357,9 @@ int s5p_mfc_wakeup(struct s5p_mfc_dev *dev) } err_mfc_wakeup: - s5p_mfc_pm_clock_off(dev); + mfc_pm_clock_off(dev); - s5p_mfc_release_hwlock_dev(dev); + mfc_release_hwlock_dev(dev); mfc_debug_leave(); diff --git a/drivers/media/platform/exynos/mfc/mfc_ctrl.h b/drivers/media/platform/exynos/mfc/mfc_ctrl.h index 4e98e2e61356..a8ad7918f6ea 100644 --- a/drivers/media/platform/exynos/mfc/mfc_ctrl.h +++ b/drivers/media/platform/exynos/mfc/mfc_ctrl.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_ctrl.h + * drivers/media/platform/exynos/mfc/mfc_ctrl.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -15,10 +15,10 @@ #include "mfc_common.h" -int s5p_mfc_init_hw(struct s5p_mfc_dev *dev); -void s5p_mfc_deinit_hw(struct s5p_mfc_dev *dev); +int mfc_init_hw(struct mfc_dev *dev); +void mfc_deinit_hw(struct mfc_dev *dev); -int s5p_mfc_sleep(struct s5p_mfc_dev *dev); -int s5p_mfc_wakeup(struct s5p_mfc_dev *dev); +int mfc_sleep(struct mfc_dev *dev); +int mfc_wakeup(struct mfc_dev *dev); #endif /* __MFC_CTRL_H */ diff --git a/drivers/media/platform/exynos/mfc/mfc_data_struct.h b/drivers/media/platform/exynos/mfc/mfc_data_struct.h index d7e15b729150..416c2f9a97cf 100644 --- a/drivers/media/platform/exynos/mfc/mfc_data_struct.h +++ b/drivers/media/platform/exynos/mfc/mfc_data_struct.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_data_struct.h + * drivers/media/platform/exynos/mfc/mfc_data_struct.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -69,9 +69,9 @@ enum { }; /** - * enum s5p_mfc_inst_type - The type of an MFC device node. + * enum mfc_inst_type - The type of an MFC device node. */ -enum s5p_mfc_node_type { +enum mfc_node_type { MFCNODE_INVALID = -1, MFCNODE_DECODER = 0, MFCNODE_ENCODER = 1, @@ -82,18 +82,18 @@ enum s5p_mfc_node_type { }; /** - * enum s5p_mfc_inst_type - The type of an MFC instance. + * enum mfc_inst_type - The type of an MFC instance. */ -enum s5p_mfc_inst_type { +enum mfc_inst_type { MFCINST_INVALID = 0, MFCINST_DECODER = 1, MFCINST_ENCODER = 2, }; /** - * enum s5p_mfc_inst_state - The state of an MFC instance. + * enum mfc_inst_state - The state of an MFC instance. */ -enum s5p_mfc_inst_state { +enum mfc_inst_state { MFCINST_FREE = 0, MFCINST_INIT = 100, MFCINST_GOT_INST, @@ -115,9 +115,9 @@ enum s5p_mfc_inst_state { }; /** - * enum s5p_mfc_queue_state - The state of buffer queue. + * enum mfc_queue_state - The state of buffer queue. */ -enum s5p_mfc_queue_state { +enum mfc_queue_state { QUEUE_FREE = 0, QUEUE_BUFS_REQUESTED, QUEUE_BUFS_QUERIED, @@ -131,9 +131,9 @@ enum mfc_dec_wait_state { }; /** - * enum s5p_mfc_check_state - The state for user notification + * enum mfc_check_state - The state for user notification */ -enum s5p_mfc_check_state { +enum mfc_check_state { MFCSTATE_PROCESSING = 0, MFCSTATE_DEC_RES_DETECT, MFCSTATE_DEC_TERMINATING, @@ -158,21 +158,21 @@ enum mfc_buf_process_type { MFCBUFPROC_ANBSHARE_NV12L = (1 << 4), }; -enum s5p_mfc_ctrl_type { +enum mfc_ctrl_type { MFC_CTRL_TYPE_GET_SRC = 0x1, MFC_CTRL_TYPE_GET_DST = 0x2, MFC_CTRL_TYPE_SET = 0x4, }; -enum s5p_mfc_ctrl_mode { +enum mfc_ctrl_mode { MFC_CTRL_MODE_NONE = 0x0, MFC_CTRL_MODE_SFR = 0x1, MFC_CTRL_MODE_CST = 0x2, }; -struct s5p_mfc_ctx; +struct mfc_ctx; -enum s5p_mfc_debug_cause { +enum mfc_debug_cause { MFC_CAUSE_0WRITE_PAGE_FAULT = 0, MFC_CAUSE_0READ_PAGE_FAULT = 1, MFC_CAUSE_1WRITE_PAGE_FAULT = 2, @@ -189,7 +189,7 @@ enum s5p_mfc_debug_cause { MFC_CAUSE_FAIL_CHACHE_FLUSH = 13, }; -struct s5p_mfc_debug { +struct mfc_debug { u32 cause; u8 fault_status; u32 fault_trans_info; @@ -200,10 +200,10 @@ struct s5p_mfc_debug { }; /** - * struct s5p_mfc_buf - MFC buffer + * struct mfc_buf - MFC buffer * */ -struct s5p_mfc_buf { +struct mfc_buf { struct vb2_v4l2_buffer vb; struct list_head list; dma_addr_t addr[MAX_NUM_IMAGES_IN_VB][MFC_MAX_PLANES]; @@ -217,17 +217,17 @@ struct s5p_mfc_buf { unsigned char *vir_addr; }; -struct s5p_mfc_buf_queue { +struct mfc_buf_queue { struct list_head head; unsigned int count; }; -struct s5p_mfc_bits { +struct mfc_bits { unsigned long bits; spinlock_t lock; }; -struct s5p_mfc_hwlock { +struct mfc_hwlock { struct list_head waiting_list; unsigned int wl_count; unsigned long bits; @@ -237,15 +237,15 @@ struct s5p_mfc_hwlock { spinlock_t lock; }; -struct s5p_mfc_listable_wq { +struct mfc_listable_wq { struct list_head list; wait_queue_head_t wait_queue; struct mutex wait_mutex; - struct s5p_mfc_dev *dev; - struct s5p_mfc_ctx *ctx; + struct mfc_dev *dev; + struct mfc_ctx *ctx; }; -struct s5p_mfc_pm { +struct mfc_pm { struct clk *clock; atomic_t pwr_ref; struct device *device; @@ -256,7 +256,7 @@ struct s5p_mfc_pm { enum mfc_buf_usage_type base_type; }; -struct s5p_mfc_fw { +struct mfc_fw { int date; int fimv_info; size_t size; @@ -264,7 +264,7 @@ struct s5p_mfc_fw { int drm_status; }; -struct s5p_mfc_ctx_buf_size { +struct mfc_ctx_buf_size { size_t dev_ctx; size_t h264_dec_ctx; size_t other_dec_ctx; @@ -275,14 +275,14 @@ struct s5p_mfc_ctx_buf_size { size_t dbg_info_buf; }; -struct s5p_mfc_buf_size { +struct mfc_buf_size { size_t firmware_code; unsigned int cpb_buf; void *ctx_buf; }; -struct s5p_mfc_variant { - struct s5p_mfc_buf_size *buf_size; +struct mfc_variant { + struct mfc_buf_size *buf_size; int num_entities; }; @@ -298,7 +298,7 @@ enum mfc_sfr_dump_type { MFC_DUMP_WARN_INT = (1 << 7), }; -struct s5p_mfc_debugfs { +struct mfc_debugfs { struct dentry *root; struct dentry *mfc_info; struct dentry *debug_info; @@ -317,13 +317,13 @@ struct s5p_mfc_debugfs { }; /** - * struct s5p_mfc_special_buf - represents internal used buffer + * struct mfc_special_buf - represents internal used buffer * @daddr: device virtual address * @virt: kernel virtual address, only valid when the * buffer accessed by driver */ -struct s5p_mfc_special_buf { - enum mfc_buf_usage_type buftype; +struct mfc_special_buf { + enum mfc_buf_usage_type buftype; struct dma_buf *dma_buf; struct dma_buf_attachment *attachment; struct sg_table *sgt; @@ -339,7 +339,7 @@ struct mfc_qos_bw_data { unsigned long write; }; -struct s5p_mfc_qos_bw { +struct mfc_qos_bw { struct mfc_qos_bw_data h264_dec_uhd_bw; struct mfc_qos_bw_data hevc_dec_uhd_bw; struct mfc_qos_bw_data hevc_dec_uhd_10bit_bw; @@ -359,7 +359,7 @@ struct s5p_mfc_qos_bw { * Total MB count can be calculated by * (MB of width) * (MB of height) * fps */ -struct s5p_mfc_qos { +struct mfc_qos { unsigned int threshold_mb; unsigned int freq_mfc; unsigned int freq_int; @@ -370,7 +370,7 @@ struct s5p_mfc_qos { unsigned int time_fw; }; -struct s5p_mfc_qos_boost { +struct mfc_qos_boost { unsigned int num_cluster; unsigned int freq_mfc; unsigned int freq_int; @@ -379,12 +379,12 @@ struct s5p_mfc_qos_boost { }; #endif -struct s5p_mfc_feature { +struct mfc_feature { unsigned int support; unsigned int version; }; -struct s5p_mfc_platdata { +struct mfc_platdata { /* MFC version */ unsigned int ip_ver; /* Debug mode */ @@ -394,13 +394,13 @@ struct s5p_mfc_platdata { unsigned int axid_mask; unsigned int mfc_fault_num; /* Features */ - struct s5p_mfc_feature nal_q; - struct s5p_mfc_feature skype; - struct s5p_mfc_feature black_bar; - struct s5p_mfc_feature color_aspect_dec; - struct s5p_mfc_feature static_info_dec; - struct s5p_mfc_feature color_aspect_enc; - struct s5p_mfc_feature static_info_enc; + struct mfc_feature nal_q; + struct mfc_feature skype; + struct mfc_feature black_bar; + struct mfc_feature color_aspect_dec; + struct mfc_feature static_info_dec; + struct mfc_feature color_aspect_enc; + struct mfc_feature static_info_enc; /* Default 10bit format for decoding */ unsigned int P010_decoding; /* Formats */ @@ -419,8 +419,8 @@ struct s5p_mfc_platdata { unsigned int mfc_freq_control; unsigned int mo_control; unsigned int bw_control; - struct s5p_mfc_qos *qos_table; - struct s5p_mfc_qos_boost *qos_boost_table; + struct mfc_qos *qos_table; + struct mfc_qos_boost *qos_boost_table; #endif }; @@ -592,8 +592,8 @@ typedef struct __EncoderOutputStr { */ typedef enum _nal_queue_state { NAL_Q_STATE_CREATED = 0, - NAL_Q_STATE_STARTED, /* when s5p_mfc_nal_q_start() is called */ - NAL_Q_STATE_STOPPED, /* when s5p_mfc_nal_q_stop() is called */ + NAL_Q_STATE_STARTED, /* when mfc_nal_q_start() is called */ + NAL_Q_STATE_STOPPED, /* when mfc_nal_q_stop() is called */ } nal_queue_state; typedef struct _nal_in_queue { @@ -613,14 +613,14 @@ typedef struct _nal_out_queue { struct _nal_queue_handle; typedef struct _nal_queue_in_handle { struct _nal_queue_handle *nal_q_handle; - struct s5p_mfc_special_buf in_buf; + struct mfc_special_buf in_buf; unsigned int in_exe_count; nal_in_queue *nal_q_in_addr; } nal_queue_in_handle; typedef struct _nal_queue_out_handle { struct _nal_queue_handle *nal_q_handle; - struct s5p_mfc_special_buf out_buf; + struct mfc_special_buf out_buf; unsigned int out_exe_count; nal_out_queue *nal_q_out_addr; int nal_q_ctx; @@ -650,7 +650,7 @@ struct _otf_buf_info { }; struct _otf_debug { - struct s5p_mfc_special_buf stream_buf[OTF_MAX_BUF]; + struct mfc_special_buf stream_buf[OTF_MAX_BUF]; unsigned int stream_size[OTF_MAX_BUF]; unsigned char frame_cnt; }; @@ -666,7 +666,7 @@ struct _otf_handle { }; /********************************************************************/ -struct s5p_mfc_perf { +struct mfc_perf { void __iomem *regs_base0; void __iomem *regs_base1; @@ -678,24 +678,24 @@ struct s5p_mfc_perf { int drv_margin; }; -extern struct s5p_mfc_dump_ops mfc_dump_ops; -struct s5p_mfc_dump_ops { - void (*dump_regs)(struct s5p_mfc_dev *dev); - void (*dump_info)(struct s5p_mfc_dev *dev); - void (*dump_info_without_regs)(struct s5p_mfc_dev *dev); - void (*dump_and_stop_always)(struct s5p_mfc_dev *dev); - void (*dump_and_stop_debug_mode)(struct s5p_mfc_dev *dev); +extern struct mfc_dump_ops mfc_dump_ops; +struct mfc_dump_ops { + void (*dump_regs)(struct mfc_dev *dev); + void (*dump_info)(struct mfc_dev *dev); + void (*dump_info_without_regs)(struct mfc_dev *dev); + void (*dump_and_stop_always)(struct mfc_dev *dev); + void (*dump_and_stop_debug_mode)(struct mfc_dev *dev); }; -struct s5p_mfc_mmcache { +struct mfc_mmcache { void __iomem *base; int is_on_status; }; /** - * struct s5p_mfc_dev - The struct containing driver internal parameters. + * struct mfc_dev - The struct containing driver internal parameters. */ -struct s5p_mfc_dev { +struct mfc_dev { struct v4l2_device v4l2_dev; struct video_device *vfd_dec; struct video_device *vfd_enc; @@ -713,11 +713,11 @@ struct s5p_mfc_dev { int irq; struct resource *mfc_mem; - struct s5p_mfc_pm pm; - struct s5p_mfc_fw fw; - struct s5p_mfc_variant *variant; - struct s5p_mfc_platdata *pdata; - struct s5p_mfc_debug *logging_data; + struct mfc_pm pm; + struct mfc_fw fw; + struct mfc_variant *variant; + struct mfc_platdata *pdata; + struct mfc_debug *logging_data; int num_inst; @@ -728,22 +728,22 @@ struct s5p_mfc_dev { unsigned int int_err; wait_queue_head_t cmd_wq; - struct s5p_mfc_listable_wq hwlock_wq; + struct mfc_listable_wq hwlock_wq; bool has_2sysmmu; bool has_hwfc; bool has_mmcache; - struct s5p_mfc_special_buf common_ctx_buf; - struct s5p_mfc_special_buf drm_common_ctx_buf; + struct mfc_special_buf common_ctx_buf; + struct mfc_special_buf drm_common_ctx_buf; - struct s5p_mfc_ctx *ctx[MFC_NUM_CONTEXTS]; + struct mfc_ctx *ctx[MFC_NUM_CONTEXTS]; int curr_ctx; int preempt_ctx; - struct s5p_mfc_bits work_bits; + struct mfc_bits work_bits; - struct s5p_mfc_hwlock hwlock; + struct mfc_hwlock hwlock; atomic_t sched_wait_cnt; atomic_t watchdog_tick_running; @@ -756,8 +756,8 @@ struct s5p_mfc_dev { /* for DRM */ int curr_ctx_is_drm; int num_drm_inst; - struct s5p_mfc_special_buf fw_buf; - struct s5p_mfc_special_buf drm_fw_buf; + struct mfc_special_buf fw_buf; + struct mfc_special_buf drm_fw_buf; struct workqueue_struct *butler_wq; struct work_struct butler_work; @@ -785,18 +785,18 @@ struct s5p_mfc_dev { nal_queue_handle *nal_q_handle; - struct s5p_mfc_special_buf dbg_info_buf; + struct mfc_special_buf dbg_info_buf; #ifdef CONFIG_EXYNOS_BTS struct bts_bw mfc_bw; #endif - struct s5p_mfc_debugfs debugfs; - struct s5p_mfc_dump_ops *dump_ops; + struct mfc_debugfs debugfs; + struct mfc_dump_ops *dump_ops; - struct s5p_mfc_perf perf; + struct mfc_perf perf; - struct s5p_mfc_mmcache mmcache; + struct mfc_mmcache mmcache; #ifdef CONFIG_EXYNOS_ITMON struct notifier_block itmon_nb; @@ -807,7 +807,7 @@ struct s5p_mfc_dev { /** * */ -struct s5p_mfc_h264_enc_params { +struct mfc_h264_enc_params { enum v4l2_mpeg_video_h264_profile profile; u8 level; u8 interlace; @@ -864,7 +864,7 @@ struct s5p_mfc_h264_enc_params { /** * */ -struct s5p_mfc_mpeg4_enc_params { +struct mfc_mpeg4_enc_params { /* MPEG4 Only */ enum v4l2_mpeg_video_mpeg4_profile profile; u8 level; @@ -886,7 +886,7 @@ struct s5p_mfc_mpeg4_enc_params { /** * */ -struct s5p_mfc_vp9_enc_params { +struct mfc_vp9_enc_params { /* VP9 Only */ u8 vp9_version; u8 rc_min_qp; @@ -909,7 +909,7 @@ struct s5p_mfc_vp9_enc_params { /** * */ -struct s5p_mfc_vp8_enc_params { +struct mfc_vp8_enc_params { /* VP8 Only */ u8 vp8_version; u8 rc_min_qp; @@ -933,7 +933,7 @@ struct s5p_mfc_vp8_enc_params { /** * */ -struct s5p_mfc_hevc_enc_params { +struct mfc_hevc_enc_params { u8 profile; u8 level; u8 tier_flag; @@ -988,7 +988,7 @@ struct s5p_mfc_hevc_enc_params { /** * */ -struct s5p_mfc_bpg_enc_params { +struct mfc_bpg_enc_params { u32 thumb_size; u32 exif_size; }; @@ -996,7 +996,7 @@ struct s5p_mfc_bpg_enc_params { /** * */ -struct s5p_mfc_enc_params { +struct mfc_enc_params { u16 width; u16 height; @@ -1055,28 +1055,28 @@ struct s5p_mfc_enc_params { u32 display_primaries_2; union { - struct s5p_mfc_h264_enc_params h264; - struct s5p_mfc_mpeg4_enc_params mpeg4; - struct s5p_mfc_vp8_enc_params vp8; - struct s5p_mfc_vp9_enc_params vp9; - struct s5p_mfc_hevc_enc_params hevc; - struct s5p_mfc_bpg_enc_params bpg; + struct mfc_h264_enc_params h264; + struct mfc_mpeg4_enc_params mpeg4; + struct mfc_vp8_enc_params vp8; + struct mfc_vp9_enc_params vp9; + struct mfc_hevc_enc_params hevc; + struct mfc_bpg_enc_params bpg; } codec; }; -struct s5p_mfc_ctx_ctrl { +struct mfc_ctx_ctrl { struct list_head list; - enum s5p_mfc_ctrl_type type; + enum mfc_ctrl_type type; unsigned int id; unsigned int addr; int has_new; int val; }; -struct s5p_mfc_buf_ctrl { +struct mfc_buf_ctrl { struct list_head list; unsigned int id; - enum s5p_mfc_ctrl_type type; + enum mfc_ctrl_type type; int has_new; int val; unsigned int old_val; /* only for MFC_CTRL_TYPE_SET */ @@ -1090,14 +1090,14 @@ struct s5p_mfc_buf_ctrl { unsigned int flag_mode; /* only for MFC_CTRL_TYPE_SET */ unsigned int flag_addr; /* only for MFC_CTRL_TYPE_SET */ unsigned int flag_shft; /* only for MFC_CTRL_TYPE_SET */ - int (*read_cst) (struct s5p_mfc_ctx *ctx, - struct s5p_mfc_buf_ctrl *buf_ctrl); - void (*write_cst) (struct s5p_mfc_ctx *ctx, - struct s5p_mfc_buf_ctrl *buf_ctrl); + int (*read_cst) (struct mfc_ctx *ctx, + struct mfc_buf_ctrl *buf_ctrl); + void (*write_cst) (struct mfc_ctx *ctx, + struct mfc_buf_ctrl *buf_ctrl); }; -struct s5p_mfc_ctrl_cfg { - enum s5p_mfc_ctrl_type type; +struct mfc_ctrl_cfg { + enum mfc_ctrl_type type; unsigned int id; unsigned int is_volatile; /* only for MFC_CTRL_TYPE_SET */ unsigned int mode; @@ -1107,41 +1107,41 @@ struct s5p_mfc_ctrl_cfg { unsigned int flag_mode; /* only for MFC_CTRL_TYPE_SET */ unsigned int flag_addr; /* only for MFC_CTRL_TYPE_SET */ unsigned int flag_shft; /* only for MFC_CTRL_TYPE_SET */ - int (*read_cst) (struct s5p_mfc_ctx *ctx, - struct s5p_mfc_buf_ctrl *buf_ctrl); - void (*write_cst) (struct s5p_mfc_ctx *ctx, - struct s5p_mfc_buf_ctrl *buf_ctrl); + int (*read_cst) (struct mfc_ctx *ctx, + struct mfc_buf_ctrl *buf_ctrl); + void (*write_cst) (struct mfc_ctx *ctx, + struct mfc_buf_ctrl *buf_ctrl); }; /* per buffer contol */ -struct s5p_mfc_ctrls_ops { +struct mfc_ctrls_ops { /* controls per buffer */ - int (*init_ctx_ctrls) (struct s5p_mfc_ctx *ctx); - int (*cleanup_ctx_ctrls) (struct s5p_mfc_ctx *ctx); - int (*init_buf_ctrls) (struct s5p_mfc_ctx *ctx, - enum s5p_mfc_ctrl_type type, unsigned int index); + int (*init_ctx_ctrls) (struct mfc_ctx *ctx); + int (*cleanup_ctx_ctrls) (struct mfc_ctx *ctx); + int (*init_buf_ctrls) (struct mfc_ctx *ctx, + enum mfc_ctrl_type type, unsigned int index); void (*reset_buf_ctrls) (struct list_head *head); - int (*cleanup_buf_ctrls) (struct s5p_mfc_ctx *ctx, - enum s5p_mfc_ctrl_type type, unsigned int index); - int (*to_buf_ctrls) (struct s5p_mfc_ctx *ctx, struct list_head *head); - int (*to_ctx_ctrls) (struct s5p_mfc_ctx *ctx, struct list_head *head); - int (*set_buf_ctrls_val) (struct s5p_mfc_ctx *ctx, + int (*cleanup_buf_ctrls) (struct mfc_ctx *ctx, + enum mfc_ctrl_type type, unsigned int index); + int (*to_buf_ctrls) (struct mfc_ctx *ctx, struct list_head *head); + int (*to_ctx_ctrls) (struct mfc_ctx *ctx, struct list_head *head); + int (*set_buf_ctrls_val) (struct mfc_ctx *ctx, struct list_head *head); - int (*get_buf_ctrls_val) (struct s5p_mfc_ctx *ctx, + int (*get_buf_ctrls_val) (struct mfc_ctx *ctx, struct list_head *head); - int (*recover_buf_ctrls_val) (struct s5p_mfc_ctx *ctx, + int (*recover_buf_ctrls_val) (struct mfc_ctx *ctx, struct list_head *head); - int (*get_buf_update_val) (struct s5p_mfc_ctx *ctx, + int (*get_buf_update_val) (struct mfc_ctx *ctx, struct list_head *head, unsigned int id, int value); - int (*set_buf_ctrls_val_nal_q_dec) (struct s5p_mfc_ctx *ctx, + int (*set_buf_ctrls_val_nal_q_dec) (struct mfc_ctx *ctx, struct list_head *head, DecoderInputStr *pInStr); - int (*get_buf_ctrls_val_nal_q_dec) (struct s5p_mfc_ctx *ctx, + int (*get_buf_ctrls_val_nal_q_dec) (struct mfc_ctx *ctx, struct list_head *head, DecoderOutputStr *pOutStr); - int (*set_buf_ctrls_val_nal_q_enc) (struct s5p_mfc_ctx *ctx, + int (*set_buf_ctrls_val_nal_q_enc) (struct mfc_ctx *ctx, struct list_head *head, EncoderInputStr *pInStr); - int (*get_buf_ctrls_val_nal_q_enc) (struct s5p_mfc_ctx *ctx, + int (*get_buf_ctrls_val_nal_q_enc) (struct mfc_ctx *ctx, struct list_head *head, EncoderOutputStr *pOutStr); - int (*recover_buf_ctrls_nal_q) (struct s5p_mfc_ctx *ctx, + int (*recover_buf_ctrls_nal_q) (struct mfc_ctx *ctx, struct list_head *head); }; @@ -1173,7 +1173,7 @@ struct mfc_user_shared_handle { void *vaddr; }; -struct s5p_mfc_raw_info { +struct mfc_raw_info { int num_planes; int stride[3]; int plane_size[3]; @@ -1189,7 +1189,7 @@ struct mfc_timestamp { int interval; }; -struct s5p_mfc_dec { +struct mfc_dec { int total_dpb_count; unsigned int src_buf_size; @@ -1232,7 +1232,7 @@ struct s5p_mfc_dec { struct dec_dpb_ref_info *ref_info; int assigned_fd[MFC_MAX_DPBS]; struct mfc_user_shared_handle sh_handle; - struct s5p_mfc_buf *assigned_dpb[MFC_MAX_DPBS]; + struct mfc_buf *assigned_dpb[MFC_MAX_DPBS]; int has_multiframe; int is_dpb_full; @@ -1254,8 +1254,8 @@ struct s5p_mfc_dec { unsigned int color_space; }; -struct s5p_mfc_enc { - struct s5p_mfc_enc_params params; +struct mfc_enc { + struct mfc_enc_params params; unsigned int dst_buf_size; unsigned int header_size; @@ -1280,11 +1280,11 @@ struct s5p_mfc_enc { struct mfc_user_shared_handle sh_handle_svc; struct mfc_user_shared_handle sh_handle_roi; int roi_index; - struct s5p_mfc_special_buf roi_buf[MFC_MAX_EXTRA_BUF]; + struct mfc_special_buf roi_buf[MFC_MAX_EXTRA_BUF]; struct mfc_enc_roi_info roi_info[MFC_MAX_EXTRA_BUF]; }; -struct s5p_mfc_fmt { +struct mfc_fmt { char *name; u32 fourcc; u32 codec_mode; @@ -1294,10 +1294,10 @@ struct s5p_mfc_fmt { }; /** - * struct s5p_mfc_ctx - This struct contains the instance context + * struct mfc_ctx - This struct contains the instance context */ -struct s5p_mfc_ctx { - struct s5p_mfc_dev *dev; +struct mfc_ctx { + struct mfc_dev *dev; struct v4l2_fh fh; int num; @@ -1306,23 +1306,23 @@ struct s5p_mfc_ctx { unsigned int int_err; wait_queue_head_t cmd_wq; - struct s5p_mfc_listable_wq hwlock_wq; + struct mfc_listable_wq hwlock_wq; - struct s5p_mfc_fmt *src_fmt; - struct s5p_mfc_fmt *dst_fmt; + struct mfc_fmt *src_fmt; + struct mfc_fmt *dst_fmt; struct vb2_queue vq_src; struct vb2_queue vq_dst; - struct s5p_mfc_buf_queue src_buf_queue; - struct s5p_mfc_buf_queue dst_buf_queue; - struct s5p_mfc_buf_queue src_buf_nal_queue; - struct s5p_mfc_buf_queue dst_buf_nal_queue; - struct s5p_mfc_buf_queue ref_buf_queue; + struct mfc_buf_queue src_buf_queue; + struct mfc_buf_queue dst_buf_queue; + struct mfc_buf_queue src_buf_nal_queue; + struct mfc_buf_queue dst_buf_nal_queue; + struct mfc_buf_queue ref_buf_queue; spinlock_t buf_queue_lock; - enum s5p_mfc_inst_type type; - enum s5p_mfc_inst_state state; + enum mfc_inst_type type; + enum mfc_inst_state state; int inst_no; int img_width; @@ -1336,14 +1336,14 @@ struct s5p_mfc_ctx { int min_dpb_size[3]; - struct s5p_mfc_raw_info raw_buf; + struct mfc_raw_info raw_buf; size_t mv_size; - struct s5p_mfc_special_buf codec_buf; + struct mfc_special_buf codec_buf; int codec_buffer_allocated; - enum s5p_mfc_queue_state capture_state; - enum s5p_mfc_queue_state output_state; + enum mfc_queue_state capture_state; + enum mfc_queue_state output_state; struct list_head ctrls; @@ -1360,12 +1360,12 @@ struct s5p_mfc_ctx { __u32 pix_format; /* Extra Buffers */ - struct s5p_mfc_special_buf instance_ctx_buf; + struct mfc_special_buf instance_ctx_buf; - struct s5p_mfc_dec *dec_priv; - struct s5p_mfc_enc *enc_priv; + struct mfc_dec *dec_priv; + struct mfc_enc *enc_priv; - struct s5p_mfc_ctrls_ops *c_ops; + struct mfc_ctrls_ops *c_ops; size_t scratch_buf_size; size_t loopfilter_luma_size; diff --git a/drivers/media/platform/exynos/mfc/mfc_debug.h b/drivers/media/platform/exynos/mfc/mfc_debug.h index 0f219b2fb305..179da9807fdd 100644 --- a/drivers/media/platform/exynos/mfc/mfc_debug.h +++ b/drivers/media/platform/exynos/mfc/mfc_debug.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_debug.h + * drivers/media/platform/exynos/mfc/mfc_debug.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ diff --git a/drivers/media/platform/exynos/mfc/mfc_debugfs.c b/drivers/media/platform/exynos/mfc/mfc_debugfs.c index f8b6092b0783..dfa8e7cbc3bf 100644 --- a/drivers/media/platform/exynos/mfc/mfc_debugfs.c +++ b/drivers/media/platform/exynos/mfc/mfc_debugfs.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_debug.c + * drivers/media/platform/exynos/mfc/mfc_debug.c * * Copyright (c) 2017 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -33,10 +33,10 @@ unsigned int mmcache_dump; unsigned int mmcache_disable; unsigned int perf_boost_mode; -static int mfc_info_show(struct seq_file *s, void *unused) +static int __mfc_info_show(struct seq_file *s, void *unused) { - struct s5p_mfc_dev *dev = s->private; - struct s5p_mfc_ctx *ctx = NULL; + struct mfc_dev *dev = s->private; + struct mfc_ctx *ctx = NULL; int i; char *codec_name = NULL; @@ -45,7 +45,7 @@ static int mfc_info_show(struct seq_file *s, void *unused) MFC_VER_MAJOR(dev), MFC_VER_MINOR(dev), dev->fw.date, dev->fw.fimv_info, MFC_DRIVER_INFO); seq_printf(s, "[PM] power: %d, clock: %d\n", - s5p_mfc_pm_get_pwr_ref_cnt(dev), s5p_mfc_pm_get_clk_ref_cnt(dev)); + mfc_pm_get_pwr_ref_cnt(dev), mfc_pm_get_clk_ref_cnt(dev)); seq_printf(s, "[CTX] num_inst: %d, num_drm_inst: %d, curr_ctx: %d(is_drm: %d)\n", dev->num_inst, dev->num_drm_inst, dev->curr_ctx, dev->curr_ctx_is_drm); seq_printf(s, "[HWLOCK] bits: %#lx, dev: %#lx, owned_by_irq = %d, wl_count = %d\n", @@ -88,18 +88,18 @@ static int mfc_info_show(struct seq_file *s, void *unused) ctx->img_width, ctx->img_height, ctx->crop_width, ctx->crop_height, ctx->crop_left, ctx->crop_top, ctx->state); seq_printf(s, " queue(src: %d, dst: %d, src_nal: %d, dst_nal: %d, ref: %d)\n", - s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_queue), - s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_queue), - s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_nal_queue), - s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_nal_queue), - s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->ref_buf_queue)); + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_nal_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_nal_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->ref_buf_queue)); } } return 0; } -static int mfc_debug_info_show(struct seq_file *s, void *unused) +static int __mfc_debug_info_show(struct seq_file *s, void *unused) { seq_puts(s, ">> MFC debug information\n"); @@ -123,33 +123,33 @@ static int mfc_debug_info_show(struct seq_file *s, void *unused) return 0; } -static int mfc_info_open(struct inode *inode, struct file *file) +static int __mfc_info_open(struct inode *inode, struct file *file) { - return single_open(file, mfc_info_show, inode->i_private); + return single_open(file, __mfc_info_show, inode->i_private); } -static int mfc_debug_info_open(struct inode *inode, struct file *file) +static int __mfc_debug_info_open(struct inode *inode, struct file *file) { - return single_open(file, mfc_debug_info_show, inode->i_private); + return single_open(file, __mfc_debug_info_show, inode->i_private); } static const struct file_operations mfc_info_fops = { - .open = mfc_info_open, + .open = __mfc_info_open, .read = seq_read, .llseek = seq_lseek, .release = single_release, }; static const struct file_operations debug_info_fops = { - .open = mfc_debug_info_open, + .open = __mfc_debug_info_open, .read = seq_read, .llseek = seq_lseek, .release = single_release, }; -void s5p_mfc_init_debugfs(struct s5p_mfc_dev *dev) +void mfc_init_debugfs(struct mfc_dev *dev) { - struct s5p_mfc_debugfs *debugfs = &dev->debugfs; + struct mfc_debugfs *debugfs = &dev->debugfs; debugfs->root = debugfs_create_dir("mfc", NULL); if (!debugfs->root) { diff --git a/drivers/media/platform/exynos/mfc/mfc_debugfs.h b/drivers/media/platform/exynos/mfc/mfc_debugfs.h index 36456deb6638..97f2ba086d15 100644 --- a/drivers/media/platform/exynos/mfc/mfc_debugfs.h +++ b/drivers/media/platform/exynos/mfc/mfc_debugfs.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_debugfs.h + * drivers/media/platform/exynos/mfc/mfc_debugfs.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -15,6 +15,6 @@ #include "mfc_common.h" -void s5p_mfc_init_debugfs(struct s5p_mfc_dev *dev); +void mfc_init_debugfs(struct mfc_dev *dev); #endif /* __MFC_DEBUGFS_H */ diff --git a/drivers/media/platform/exynos/mfc/mfc_dec.c b/drivers/media/platform/exynos/mfc/mfc_dec.c index d6e2a886fa2d..9c004a2a6b41 100644 --- a/drivers/media/platform/exynos/mfc/mfc_dec.c +++ b/drivers/media/platform/exynos/mfc/mfc_dec.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_dec.c + * drivers/media/platform/exynos/mfc/mfc_dec.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -27,16 +27,16 @@ #define MAX_FRAME_SIZE (2*1024*1024) /* Find selected format description */ -static struct s5p_mfc_fmt *mfc_dec_find_format(struct s5p_mfc_ctx *ctx, +static struct mfc_fmt *__mfc_dec_find_format(struct mfc_ctx *ctx, unsigned int pixelformat) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_fmt *fmt = NULL; + struct mfc_dev *dev = ctx->dev; + struct mfc_fmt *fmt = NULL; unsigned long i; for (i = 0; i < NUM_FORMATS; i++) { if (dec_formats[i].fourcc == pixelformat) { - fmt = (struct s5p_mfc_fmt *)&dec_formats[i]; + fmt = (struct mfc_fmt *)&dec_formats[i]; break; } } @@ -53,7 +53,7 @@ static struct s5p_mfc_fmt *mfc_dec_find_format(struct s5p_mfc_ctx *ctx, return fmt; } -static struct v4l2_queryctrl *mfc_dec_get_ctrl(int id) +static struct v4l2_queryctrl *__mfc_dec_get_ctrl(int id) { unsigned long i; @@ -65,11 +65,11 @@ static struct v4l2_queryctrl *mfc_dec_get_ctrl(int id) } /* Check whether a ctrl value if correct */ -static int mfc_dec_check_ctrl_val(struct s5p_mfc_ctx *ctx, struct v4l2_control *ctrl) +static int __mfc_dec_check_ctrl_val(struct mfc_ctx *ctx, struct v4l2_control *ctrl) { struct v4l2_queryctrl *c; - c = mfc_dec_get_ctrl(ctrl->id); + c = __mfc_dec_get_ctrl(ctrl->id); if (!c) { mfc_err_ctx("[CTRLS] not supported control id (%#x)\n", ctrl->id); return -EINVAL; @@ -104,10 +104,10 @@ static int vidioc_querycap(struct file *file, void *priv, return 0; } -static int mfc_dec_enum_fmt(struct s5p_mfc_dev *dev, struct v4l2_fmtdesc *f, +static int __mfc_dec_enum_fmt(struct mfc_dev *dev, struct v4l2_fmtdesc *f, unsigned int type) { - struct s5p_mfc_fmt *fmt; + struct mfc_fmt *fmt; unsigned long i, j = 0; for (i = 0; i < NUM_FORMATS; ++i) { @@ -136,22 +136,22 @@ static int mfc_dec_enum_fmt(struct s5p_mfc_dev *dev, struct v4l2_fmtdesc *f, static int vidioc_enum_fmt_vid_cap_mplane(struct file *file, void *pirv, struct v4l2_fmtdesc *f) { - struct s5p_mfc_dev *dev = video_drvdata(file); + struct mfc_dev *dev = video_drvdata(file); - return mfc_dec_enum_fmt(dev, f, MFC_FMT_FRAME); + return __mfc_dec_enum_fmt(dev, f, MFC_FMT_FRAME); } static int vidioc_enum_fmt_vid_out_mplane(struct file *file, void *prov, struct v4l2_fmtdesc *f) { - struct s5p_mfc_dev *dev = video_drvdata(file); + struct mfc_dev *dev = video_drvdata(file); - return mfc_dec_enum_fmt(dev, f, MFC_FMT_STREAM); + return __mfc_dec_enum_fmt(dev, f, MFC_FMT_STREAM); } -static void mfc_dec_change_format(struct s5p_mfc_ctx *ctx) +static void __mfc_dec_change_format(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; u32 org_fmt = ctx->dst_fmt->fourcc; if (ctx->is_10bit && ctx->is_422) { @@ -166,23 +166,23 @@ static void mfc_dec_change_format(struct s5p_mfc_ctx *ctx) case V4L2_PIX_FMT_NV16M: case V4L2_PIX_FMT_NV12M_S10B: case V4L2_PIX_FMT_NV12M_P010: - ctx->dst_fmt = mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV16M_S10B); + ctx->dst_fmt = __mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV16M_S10B); break; case V4L2_PIX_FMT_NV21M: case V4L2_PIX_FMT_NV61M: case V4L2_PIX_FMT_NV21M_S10B: case V4L2_PIX_FMT_NV21M_P010: - ctx->dst_fmt = mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV61M_S10B); + ctx->dst_fmt = __mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV61M_S10B); break; default: - ctx->dst_fmt = mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV16M_S10B); + ctx->dst_fmt = __mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV16M_S10B); break; } ctx->raw_buf.num_planes = 2; } else if (ctx->is_10bit && !ctx->is_422) { if (ctx->dst_fmt->mem_planes == 1) { /* YUV420 only supports the single plane */ - ctx->dst_fmt = mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV12N_10B); + ctx->dst_fmt = __mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV12N_10B); } else { switch (org_fmt) { case V4L2_PIX_FMT_NV12M_S10B: @@ -196,21 +196,21 @@ static void mfc_dec_change_format(struct s5p_mfc_ctx *ctx) case V4L2_PIX_FMT_NV16M_S10B: case V4L2_PIX_FMT_NV16M_P210: if (dev->pdata->P010_decoding) - ctx->dst_fmt = mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV12M_P010); + ctx->dst_fmt = __mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV12M_P010); else - ctx->dst_fmt = mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV12M_S10B); + ctx->dst_fmt = __mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV12M_S10B); break; case V4L2_PIX_FMT_NV21M: case V4L2_PIX_FMT_NV61M: case V4L2_PIX_FMT_NV61M_S10B: case V4L2_PIX_FMT_NV61M_P210: - ctx->dst_fmt = mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV21M_S10B); + ctx->dst_fmt = __mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV21M_S10B); break; default: if (dev->pdata->P010_decoding) - ctx->dst_fmt = mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV12M_P010); + ctx->dst_fmt = __mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV12M_P010); else - ctx->dst_fmt = mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV12M_S10B); + ctx->dst_fmt = __mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV12M_S10B); break; } } @@ -226,17 +226,17 @@ static void mfc_dec_change_format(struct s5p_mfc_ctx *ctx) case V4L2_PIX_FMT_NV16M_S10B: case V4L2_PIX_FMT_NV12M_P010: case V4L2_PIX_FMT_NV16M_P210: - ctx->dst_fmt = mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV16M); + ctx->dst_fmt = __mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV16M); break; case V4L2_PIX_FMT_NV21M: case V4L2_PIX_FMT_NV21M_S10B: case V4L2_PIX_FMT_NV61M_S10B: case V4L2_PIX_FMT_NV21M_P010: case V4L2_PIX_FMT_NV61M_P210: - ctx->dst_fmt = mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV61M); + ctx->dst_fmt = __mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV61M); break; default: - ctx->dst_fmt = mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV16M); + ctx->dst_fmt = __mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV16M); break; } ctx->raw_buf.num_planes = 2; @@ -248,14 +248,14 @@ static void mfc_dec_change_format(struct s5p_mfc_ctx *ctx) case V4L2_PIX_FMT_NV16M_S10B: case V4L2_PIX_FMT_NV12M_P010: case V4L2_PIX_FMT_NV16M_P210: - ctx->dst_fmt = mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV12M); + ctx->dst_fmt = __mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV12M); break; case V4L2_PIX_FMT_NV61M: case V4L2_PIX_FMT_NV21M_S10B: case V4L2_PIX_FMT_NV61M_S10B: case V4L2_PIX_FMT_NV21M_P010: case V4L2_PIX_FMT_NV61M_P210: - ctx->dst_fmt = mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV21M); + ctx->dst_fmt = __mfc_dec_find_format(ctx, V4L2_PIX_FMT_NV21M); break; default: /* It is right format */ @@ -271,10 +271,10 @@ static void mfc_dec_change_format(struct s5p_mfc_ctx *ctx) static int vidioc_g_fmt_vid_cap_mplane(struct file *file, void *priv, struct v4l2_format *f) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); - struct s5p_mfc_dec *dec; + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_dec *dec; struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp; - struct s5p_mfc_raw_info *raw; + struct mfc_raw_info *raw; int i; mfc_debug_enter(); @@ -292,8 +292,8 @@ static int vidioc_g_fmt_vid_cap_mplane(struct file *file, void *priv, ctx->state == MFCINST_RES_CHANGE_END) { /* If the MFC is parsing the header, * so wait until it is finished */ - if (s5p_mfc_wait_for_done_ctx(ctx, - S5P_FIMV_R2H_CMD_SEQ_DONE_RET)) { + if (mfc_wait_for_done_ctx(ctx, + MFC_REG_R2H_CMD_SEQ_DONE_RET)) { mfc_err_dev("header parsing failed\n"); return -EAGAIN; } @@ -305,14 +305,14 @@ static int vidioc_g_fmt_vid_cap_mplane(struct file *file, void *priv, /* only NV16(61) format is supported for 422 format */ /* only 2 plane is supported for 10bit */ - mfc_dec_change_format(ctx); + __mfc_dec_change_format(ctx); raw = &ctx->raw_buf; /* Width and height are set to the dimensions of the movie, the buffer is bigger and further processing stages should crop to this rectangle. */ - s5p_mfc_dec_calc_dpb_size(ctx); + mfc_dec_calc_dpb_size(ctx); if (IS_LOW_MEM) { unsigned int dpb_size; @@ -367,8 +367,8 @@ static int vidioc_g_fmt_vid_cap_mplane(struct file *file, void *priv, static int vidioc_g_fmt_vid_out_mplane(struct file *file, void *priv, struct v4l2_format *f) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); - struct s5p_mfc_dec *dec; + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_dec *dec; struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp; mfc_debug_enter(); @@ -400,11 +400,11 @@ static int vidioc_g_fmt_vid_out_mplane(struct file *file, void *priv, /* Try format */ static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); - struct s5p_mfc_fmt *fmt; + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_fmt *fmt; struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp; - fmt = mfc_dec_find_format(ctx, pix_fmt_mp->pixelformat); + fmt = __mfc_dec_find_format(ctx, pix_fmt_mp->pixelformat); if (!fmt) { mfc_err_dev("Unsupported format for %s\n", V4L2_TYPE_IS_OUTPUT(f->type) ? "source" : "destination"); @@ -418,7 +418,7 @@ static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f) static int vidioc_s_fmt_vid_cap_mplane(struct file *file, void *priv, struct v4l2_format *f) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp; mfc_debug_enter(); @@ -428,7 +428,7 @@ static int vidioc_s_fmt_vid_cap_mplane(struct file *file, void *priv, return -EBUSY; } - ctx->dst_fmt = mfc_dec_find_format(ctx, pix_fmt_mp->pixelformat); + ctx->dst_fmt = __mfc_dec_find_format(ctx, pix_fmt_mp->pixelformat); if (!ctx->dst_fmt) { mfc_err_ctx("Unsupported format for destination\n"); return -EINVAL; @@ -441,33 +441,33 @@ static int vidioc_s_fmt_vid_cap_mplane(struct file *file, void *priv, return 0; } -static int mfc_force_close_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx) +static int __mfc_force_close_inst(struct mfc_dev *dev, struct mfc_ctx *ctx) { if (ctx->inst_no == MFC_NO_INSTANCE_SET) return 0; - s5p_mfc_change_state(ctx, MFCINST_RETURN_INST); - s5p_mfc_set_bit(ctx->num, &dev->work_bits); - s5p_mfc_clean_ctx_int_flags(ctx); - if (s5p_mfc_just_run(dev, ctx->num)) { + mfc_change_state(ctx, MFCINST_RETURN_INST); + mfc_set_bit(ctx->num, &dev->work_bits); + mfc_clean_ctx_int_flags(ctx); + if (mfc_just_run(dev, ctx->num)) { mfc_err_ctx("Failed to run MFC\n"); - s5p_mfc_release_hwlock_ctx(ctx); - s5p_mfc_cleanup_work_bit_and_try_run(ctx); + mfc_release_hwlock_ctx(ctx); + mfc_cleanup_work_bit_and_try_run(ctx); return -EIO; } /* Wait until instance is returned or timeout occured */ - if (s5p_mfc_wait_for_done_ctx(ctx, - S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET)) { + if (mfc_wait_for_done_ctx(ctx, + MFC_REG_R2H_CMD_CLOSE_INSTANCE_RET)) { mfc_err_ctx("Waiting for CLOSE_INSTANCE timed out\n"); - s5p_mfc_release_hwlock_ctx(ctx); - s5p_mfc_cleanup_work_bit_and_try_run(ctx); + mfc_release_hwlock_ctx(ctx); + mfc_cleanup_work_bit_and_try_run(ctx); return -EIO; } /* Free resources */ - s5p_mfc_release_instance_context(ctx); - s5p_mfc_change_state(ctx, MFCINST_INIT); + mfc_release_instance_context(ctx); + mfc_change_state(ctx, MFCINST_INIT); return 0; } @@ -475,9 +475,9 @@ static int mfc_force_close_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx static int vidioc_s_fmt_vid_out_mplane(struct file *file, void *priv, struct v4l2_format *f) { - struct s5p_mfc_dev *dev = video_drvdata(file); - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); - struct s5p_mfc_dec *dec = ctx->dec_priv; + struct mfc_dev *dev = video_drvdata(file); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_dec *dec = ctx->dec_priv; struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp; int ret = 0; @@ -488,7 +488,7 @@ static int vidioc_s_fmt_vid_out_mplane(struct file *file, void *priv, return -EBUSY; } - ctx->src_fmt = mfc_dec_find_format(ctx, pix_fmt_mp->pixelformat); + ctx->src_fmt = __mfc_dec_find_format(ctx, pix_fmt_mp->pixelformat); if (!ctx->src_fmt) { mfc_err_ctx("Unsupported format for source\n"); return -EINVAL; @@ -514,52 +514,52 @@ static int vidioc_s_fmt_vid_out_mplane(struct file *file, void *priv, pix_fmt_mp->plane_fmt[0].bytesperline = 0; MFC_TRACE_CTX_HWLOCK("**DEC s_fmt\n"); - ret = s5p_mfc_get_hwlock_ctx(ctx); + ret = mfc_get_hwlock_ctx(ctx); if (ret < 0) { mfc_err_ctx("Failed to get hwlock\n"); return -EBUSY; } /* In case of calling s_fmt twice or more */ - ret = mfc_force_close_inst(dev, ctx); + ret = __mfc_force_close_inst(dev, ctx); if (ret) { mfc_err_ctx("Failed to close already opening instance\n"); return -EIO; } - ret = s5p_mfc_alloc_instance_context(ctx); + ret = mfc_alloc_instance_context(ctx); if (ret) { mfc_err_ctx("Failed to allocate dec instance[%d] buffers\n", ctx->num); - s5p_mfc_release_hwlock_ctx(ctx); + mfc_release_hwlock_ctx(ctx); return -ENOMEM; } - s5p_mfc_set_bit(ctx->num, &dev->work_bits); - ret = s5p_mfc_just_run(dev, ctx->num); + mfc_set_bit(ctx->num, &dev->work_bits); + ret = mfc_just_run(dev, ctx->num); if (ret) { mfc_err_ctx("Failed to run MFC\n"); - s5p_mfc_release_hwlock_ctx(ctx); - s5p_mfc_cleanup_work_bit_and_try_run(ctx); - s5p_mfc_release_instance_context(ctx); + mfc_release_hwlock_ctx(ctx); + mfc_cleanup_work_bit_and_try_run(ctx); + mfc_release_instance_context(ctx); return -EIO; } - if (s5p_mfc_wait_for_done_ctx(ctx, - S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET)) { - s5p_mfc_release_hwlock_ctx(ctx); - s5p_mfc_cleanup_work_bit_and_try_run(ctx); - s5p_mfc_release_instance_context(ctx); + if (mfc_wait_for_done_ctx(ctx, + MFC_REG_R2H_CMD_OPEN_INSTANCE_RET)) { + mfc_release_hwlock_ctx(ctx); + mfc_cleanup_work_bit_and_try_run(ctx); + mfc_release_instance_context(ctx); return -EIO; } - s5p_mfc_release_hwlock_ctx(ctx); + mfc_release_hwlock_ctx(ctx); mfc_debug(2, "Got instance number: %d\n", ctx->inst_no); - if (s5p_mfc_dec_ctx_ready(ctx)) - s5p_mfc_set_bit(ctx->num, &dev->work_bits); - if (s5p_mfc_is_work_to_do(dev)) + if (mfc_dec_ctx_ready(ctx)) + mfc_set_bit(ctx->num, &dev->work_bits); + if (mfc_is_work_to_do(dev)) queue_work(dev->butler_wq, &dev->butler_work); mfc_debug_leave(); @@ -571,9 +571,9 @@ static int vidioc_s_fmt_vid_out_mplane(struct file *file, void *priv, static int vidioc_reqbufs(struct file *file, void *priv, struct v4l2_requestbuffers *reqbufs) { - struct s5p_mfc_dev *dev = video_drvdata(file); - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); - struct s5p_mfc_dec *dec; + struct mfc_dev *dev = video_drvdata(file); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_dec *dec; int ret = 0; mfc_debug_enter(); @@ -625,9 +625,9 @@ static int vidioc_reqbufs(struct file *file, void *priv, ret = vb2_reqbufs(&ctx->vq_dst, reqbufs); if (dev->has_mmcache && dev->mmcache.is_on_status) - s5p_mfc_invalidate_mmcache(dev); + mfc_invalidate_mmcache(dev); - s5p_mfc_release_codec_buffers(ctx); + mfc_release_codec_buffers(ctx); ctx->capture_state = QUEUE_FREE; return ret; } @@ -654,7 +654,7 @@ static int vidioc_reqbufs(struct file *file, void *priv, dec->total_dpb_count = reqbufs->count; - ret = s5p_mfc_alloc_codec_buffers(ctx); + ret = mfc_alloc_codec_buffers(ctx); if (ret) { mfc_err_ctx("Failed to allocate decoding buffers\n"); reqbufs->count = 0; @@ -664,10 +664,10 @@ static int vidioc_reqbufs(struct file *file, void *priv, ctx->capture_state = QUEUE_BUFS_REQUESTED; - if (s5p_mfc_dec_ctx_ready(ctx)) - s5p_mfc_set_bit(ctx->num, &dev->work_bits); + if (mfc_dec_ctx_ready(ctx)) + mfc_set_bit(ctx->num, &dev->work_bits); - s5p_mfc_try_run(dev); + mfc_try_run(dev); } mfc_debug_leave(); @@ -679,7 +679,7 @@ static int vidioc_reqbufs(struct file *file, void *priv, static int vidioc_querybuf(struct file *file, void *priv, struct v4l2_buffer *buf) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); int ret; mfc_debug_enter(); @@ -711,7 +711,7 @@ static int vidioc_querybuf(struct file *file, void *priv, /* Queue a buffer */ static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); int ret = -EINVAL; mfc_debug_enter(); @@ -736,7 +736,7 @@ static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf) return -EIO; } - s5p_mfc_qos_update_framerate(ctx); + mfc_qos_update_framerate(ctx); if (!buf->m.planes[0].bytesused) { buf->m.planes[0].bytesused = buf->m.planes[0].length; @@ -758,8 +758,8 @@ static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf) /* Dequeue a buffer */ static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); - struct s5p_mfc_dec *dec = ctx->dec_priv; + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_dec *dec = ctx->dec_priv; struct dec_dpb_ref_info *dstBuf, *srcBuf; int ret; int ncount = 0; @@ -806,7 +806,7 @@ static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf) static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type type) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); int ret = -EINVAL; mfc_debug_enter(); @@ -819,14 +819,14 @@ static int vidioc_streamon(struct file *file, void *priv, ret = vb2_streamon(&ctx->vq_dst, type); if (!ret) - s5p_mfc_qos_on(ctx); + mfc_qos_on(ctx); } else { mfc_err_ctx("unknown v4l2 buffer type\n"); } mfc_debug(2, "src: %d, dst: %d, state = %d, dpb_count = %d\n", - s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_queue), - s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_queue), ctx->state, ctx->dpb_count); mfc_debug_leave(); @@ -838,21 +838,21 @@ static int vidioc_streamon(struct file *file, void *priv, static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type type) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); int ret = -EINVAL; mfc_debug_enter(); if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { mfc_debug(4, "dec src streamoff\n"); - s5p_mfc_qos_reset_last_framerate(ctx); + mfc_qos_reset_last_framerate(ctx); ret = vb2_streamoff(&ctx->vq_src, type); } else if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { mfc_debug(4, "dec dst streamoff\n"); ret = vb2_streamoff(&ctx->vq_dst, type); if (!ret) - s5p_mfc_qos_off(ctx); + mfc_qos_off(ctx); } else { mfc_err_ctx("unknown v4l2 buffer type\n"); } @@ -868,7 +868,7 @@ static int vidioc_queryctrl(struct file *file, void *priv, { struct v4l2_queryctrl *c; - c = mfc_dec_get_ctrl(qc->id); + c = __mfc_dec_get_ctrl(qc->id); if (!c) { mfc_err_dev("[CTRLS] not supported control id (%#x)\n", qc->id); return -EINVAL; @@ -878,9 +878,9 @@ static int vidioc_queryctrl(struct file *file, void *priv, return 0; } -static int mfc_dec_ext_info(struct s5p_mfc_ctx *ctx) +static int __mfc_dec_ext_info(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; int val = 0; val |= DEC_SET_DYNAMIC_DPB; @@ -893,11 +893,11 @@ static int mfc_dec_ext_info(struct s5p_mfc_ctx *ctx) } /* Get ctrl */ -static int mfc_dec_get_ctrl_val(struct s5p_mfc_ctx *ctx, struct v4l2_control *ctrl) +static int __mfc_dec_get_ctrl_val(struct mfc_ctx *ctx, struct v4l2_control *ctrl) { - struct s5p_mfc_dev *dev; - struct s5p_mfc_dec *dec; - struct s5p_mfc_ctx_ctrl *ctx_ctrl; + struct mfc_dev *dev; + struct mfc_dec *dec; + struct mfc_ctx_ctrl *ctx_ctrl; int found = 0; if (!ctx) { @@ -936,9 +936,9 @@ static int mfc_dec_get_ctrl_val(struct s5p_mfc_ctx *ctx, struct v4l2_control *ct } /* Should wait for the header to be parsed */ - if (s5p_mfc_wait_for_done_ctx(ctx, - S5P_FIMV_R2H_CMD_SEQ_DONE_RET)) { - s5p_mfc_cleanup_work_bit_and_try_run(ctx); + if (mfc_wait_for_done_ctx(ctx, + MFC_REG_R2H_CMD_SEQ_DONE_RET)) { + mfc_cleanup_work_bit_and_try_run(ctx); return -EIO; } @@ -978,7 +978,7 @@ static int mfc_dec_get_ctrl_val(struct s5p_mfc_ctx *ctx, struct v4l2_control *ct ctrl->value = dec->idr_decoding; break; case V4L2_CID_MPEG_MFC51_VIDEO_FRAME_RATE: - ctrl->value = s5p_mfc_qos_get_framerate(ctx); + ctrl->value = mfc_qos_get_framerate(ctx); break; case V4L2_CID_MPEG_MFC_GET_VERSION_INFO: ctrl->value = dev->pdata->ip_ver; @@ -990,7 +990,7 @@ static int mfc_dec_get_ctrl_val(struct s5p_mfc_ctx *ctx, struct v4l2_control *ct ctrl->value = dec->is_dynamic_dpb; break; case V4L2_CID_MPEG_MFC_GET_EXT_INFO: - ctrl->value = mfc_dec_ext_info(ctx); + ctrl->value = __mfc_dec_ext_info(ctx); break; case V4L2_CID_MPEG_MFC_GET_10BIT_INFO: ctrl->value = ctx->is_10bit; @@ -1035,11 +1035,11 @@ static int mfc_dec_get_ctrl_val(struct s5p_mfc_ctx *ctx, struct v4l2_control *ct static int vidioc_g_ctrl(struct file *file, void *priv, struct v4l2_control *ctrl) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); int ret = 0; mfc_debug_enter(); - ret = mfc_dec_get_ctrl_val(ctx, ctrl); + ret = __mfc_dec_get_ctrl_val(ctx, ctrl); mfc_debug_leave(); return ret; @@ -1049,10 +1049,10 @@ static int vidioc_g_ctrl(struct file *file, void *priv, static int vidioc_s_ctrl(struct file *file, void *priv, struct v4l2_control *ctrl) { - struct s5p_mfc_dev *dev = video_drvdata(file); - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); - struct s5p_mfc_dec *dec; - struct s5p_mfc_ctx_ctrl *ctx_ctrl; + struct mfc_dev *dev = video_drvdata(file); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_dec *dec; + struct mfc_ctx_ctrl *ctx_ctrl; int ret = 0; int found = 0; @@ -1069,7 +1069,7 @@ static int vidioc_s_ctrl(struct file *file, void *priv, return -EINVAL; } - ret = mfc_dec_check_ctrl_val(ctx, ctrl); + ret = __mfc_dec_check_ctrl_val(ctx, ctrl); if (ret) return ret; @@ -1124,7 +1124,7 @@ static int vidioc_s_ctrl(struct file *file, void *priv, case V4L2_CID_MPEG_MFC_SET_USER_SHARED_HANDLE: if (dec->sh_handle.fd == -1) { dec->sh_handle.fd = ctrl->value; - if (s5p_mfc_mem_get_user_shared_handle(ctx, &dec->sh_handle)) + if (mfc_mem_get_user_shared_handle(ctx, &dec->sh_handle)) return -EINVAL; else mfc_debug(2, "[MEMINFO][DPB] shared handle fd: %d, vaddr: 0x%p\n", @@ -1167,8 +1167,8 @@ static int vidioc_s_ctrl(struct file *file, void *priv, static int vidioc_g_crop(struct file *file, void *priv, struct v4l2_crop *cr) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); - struct s5p_mfc_dec *dec = ctx->dec_priv; + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_dec *dec = ctx->dec_priv; mfc_debug_enter(); @@ -1220,7 +1220,7 @@ static int vidioc_g_crop(struct file *file, void *priv, static int vidioc_g_ext_ctrls(struct file *file, void *priv, struct v4l2_ext_controls *f) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); struct v4l2_ext_control *ext_ctrl; struct v4l2_control ctrl; int i; @@ -1234,7 +1234,7 @@ static int vidioc_g_ext_ctrls(struct file *file, void *priv, ctrl.id = ext_ctrl->id; - ret = mfc_dec_get_ctrl_val(ctx, &ctrl); + ret = __mfc_dec_get_ctrl_val(ctx, &ctrl); if (ret == 0) { ext_ctrl->value = ctrl.value; } else { @@ -1250,7 +1250,7 @@ static int vidioc_g_ext_ctrls(struct file *file, void *priv, } /* v4l2_ioctl_ops */ -static const struct v4l2_ioctl_ops s5p_mfc_dec_ioctl_ops = { +static const struct v4l2_ioctl_ops mfc_dec_ioctl_ops = { .vidioc_querycap = vidioc_querycap, .vidioc_enum_fmt_vid_cap_mplane = vidioc_enum_fmt_vid_cap_mplane, .vidioc_enum_fmt_vid_out_mplane = vidioc_enum_fmt_vid_out_mplane, @@ -1273,7 +1273,7 @@ static const struct v4l2_ioctl_ops s5p_mfc_dec_ioctl_ops = { .vidioc_g_ext_ctrls = vidioc_g_ext_ctrls, }; -const struct v4l2_ioctl_ops *s5p_mfc_get_dec_v4l2_ioctl_ops(void) +const struct v4l2_ioctl_ops *mfc_get_dec_v4l2_ioctl_ops(void) { - return &s5p_mfc_dec_ioctl_ops; + return &mfc_dec_ioctl_ops; } diff --git a/drivers/media/platform/exynos/mfc/mfc_dec.h b/drivers/media/platform/exynos/mfc/mfc_dec.h index c5871ac76470..b9f9081ab422 100644 --- a/drivers/media/platform/exynos/mfc/mfc_dec.h +++ b/drivers/media/platform/exynos/mfc/mfc_dec.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_dec.h + * drivers/media/platform/exynos/mfc/mfc_dec.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -15,6 +15,6 @@ #include "mfc_common.h" -const struct v4l2_ioctl_ops *s5p_mfc_get_dec_v4l2_ioctl_ops(void); +const struct v4l2_ioctl_ops *mfc_get_dec_v4l2_ioctl_ops(void); #endif /* __MFC_DEC_H */ diff --git a/drivers/media/platform/exynos/mfc/mfc_dec_internal.h b/drivers/media/platform/exynos/mfc/mfc_dec_internal.h index 81c8eedc27bf..e906d5e131ba 100644 --- a/drivers/media/platform/exynos/mfc/mfc_dec_internal.h +++ b/drivers/media/platform/exynos/mfc/mfc_dec_internal.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_dec_internal.h + * drivers/media/platform/exynos/mfc/mfc_dec_internal.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -15,7 +15,7 @@ #include "mfc_common.h" -struct s5p_mfc_fmt dec_formats[] = { +struct mfc_fmt dec_formats[] = { { .name = "4:2:0 3 Planes Y/Cb/Cr", .fourcc = V4L2_PIX_FMT_YUV420M, @@ -155,7 +155,7 @@ struct s5p_mfc_fmt dec_formats[] = { { .name = "H264 Encoded Stream", .fourcc = V4L2_PIX_FMT_H264, - .codec_mode = S5P_FIMV_CODEC_H264_DEC, + .codec_mode = MFC_REG_CODEC_H264_DEC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, @@ -163,7 +163,7 @@ struct s5p_mfc_fmt dec_formats[] = { { .name = "H264/MVC Encoded Stream", .fourcc = V4L2_PIX_FMT_H264_MVC, - .codec_mode = S5P_FIMV_CODEC_H264_MVC_DEC, + .codec_mode = MFC_REG_CODEC_H264_MVC_DEC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, @@ -171,7 +171,7 @@ struct s5p_mfc_fmt dec_formats[] = { { .name = "H263 Encoded Stream", .fourcc = V4L2_PIX_FMT_H263, - .codec_mode = S5P_FIMV_CODEC_H263_DEC, + .codec_mode = MFC_REG_CODEC_H263_DEC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, @@ -179,7 +179,7 @@ struct s5p_mfc_fmt dec_formats[] = { { .name = "MPEG1 Encoded Stream", .fourcc = V4L2_PIX_FMT_MPEG1, - .codec_mode = S5P_FIMV_CODEC_MPEG2_DEC, + .codec_mode = MFC_REG_CODEC_MPEG2_DEC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, @@ -187,7 +187,7 @@ struct s5p_mfc_fmt dec_formats[] = { { .name = "MPEG2 Encoded Stream", .fourcc = V4L2_PIX_FMT_MPEG2, - .codec_mode = S5P_FIMV_CODEC_MPEG2_DEC, + .codec_mode = MFC_REG_CODEC_MPEG2_DEC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, @@ -195,7 +195,7 @@ struct s5p_mfc_fmt dec_formats[] = { { .name = "MPEG4 Encoded Stream", .fourcc = V4L2_PIX_FMT_MPEG4, - .codec_mode = S5P_FIMV_CODEC_MPEG4_DEC, + .codec_mode = MFC_REG_CODEC_MPEG4_DEC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, @@ -203,7 +203,7 @@ struct s5p_mfc_fmt dec_formats[] = { { .name = "FIMV Encoded Stream", .fourcc = V4L2_PIX_FMT_FIMV, - .codec_mode = S5P_FIMV_CODEC_MPEG4_DEC, + .codec_mode = MFC_REG_CODEC_MPEG4_DEC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, @@ -211,7 +211,7 @@ struct s5p_mfc_fmt dec_formats[] = { { .name = "FIMV1 Encoded Stream", .fourcc = V4L2_PIX_FMT_FIMV1, - .codec_mode = S5P_FIMV_CODEC_FIMV1_DEC, + .codec_mode = MFC_REG_CODEC_FIMV1_DEC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, @@ -219,7 +219,7 @@ struct s5p_mfc_fmt dec_formats[] = { { .name = "FIMV2 Encoded Stream", .fourcc = V4L2_PIX_FMT_FIMV2, - .codec_mode = S5P_FIMV_CODEC_FIMV2_DEC, + .codec_mode = MFC_REG_CODEC_FIMV2_DEC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, @@ -227,7 +227,7 @@ struct s5p_mfc_fmt dec_formats[] = { { .name = "FIMV3 Encoded Stream", .fourcc = V4L2_PIX_FMT_FIMV3, - .codec_mode = S5P_FIMV_CODEC_FIMV3_DEC, + .codec_mode = MFC_REG_CODEC_FIMV3_DEC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, @@ -235,7 +235,7 @@ struct s5p_mfc_fmt dec_formats[] = { { .name = "FIMV4 Encoded Stream", .fourcc = V4L2_PIX_FMT_FIMV4, - .codec_mode = S5P_FIMV_CODEC_FIMV4_DEC, + .codec_mode = MFC_REG_CODEC_FIMV4_DEC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, @@ -243,7 +243,7 @@ struct s5p_mfc_fmt dec_formats[] = { { .name = "XviD Encoded Stream", .fourcc = V4L2_PIX_FMT_XVID, - .codec_mode = S5P_FIMV_CODEC_MPEG4_DEC, + .codec_mode = MFC_REG_CODEC_MPEG4_DEC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, @@ -251,7 +251,7 @@ struct s5p_mfc_fmt dec_formats[] = { { .name = "VC1 Encoded Stream", .fourcc = V4L2_PIX_FMT_VC1_ANNEX_G, - .codec_mode = S5P_FIMV_CODEC_VC1_DEC, + .codec_mode = MFC_REG_CODEC_VC1_DEC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, @@ -259,7 +259,7 @@ struct s5p_mfc_fmt dec_formats[] = { { .name = "VC1 RCV Encoded Stream", .fourcc = V4L2_PIX_FMT_VC1_ANNEX_L, - .codec_mode = S5P_FIMV_CODEC_VC1_RCV_DEC, + .codec_mode = MFC_REG_CODEC_VC1_RCV_DEC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, @@ -267,7 +267,7 @@ struct s5p_mfc_fmt dec_formats[] = { { .name = "VP8 Encoded Stream", .fourcc = V4L2_PIX_FMT_VP8, - .codec_mode = S5P_FIMV_CODEC_VP8_DEC, + .codec_mode = MFC_REG_CODEC_VP8_DEC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, @@ -275,7 +275,7 @@ struct s5p_mfc_fmt dec_formats[] = { { .name = "VP9 Encoded Stream", .fourcc = V4L2_PIX_FMT_VP9, - .codec_mode = S5P_FIMV_CODEC_VP9_DEC, + .codec_mode = MFC_REG_CODEC_VP9_DEC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, @@ -283,7 +283,7 @@ struct s5p_mfc_fmt dec_formats[] = { { .name = "HEVC Encoded Stream", .fourcc = V4L2_PIX_FMT_HEVC, - .codec_mode = S5P_FIMV_CODEC_HEVC_DEC, + .codec_mode = MFC_REG_CODEC_HEVC_DEC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, @@ -291,7 +291,7 @@ struct s5p_mfc_fmt dec_formats[] = { { .name = "BPG Encoded Stream", .fourcc = V4L2_PIX_FMT_BPG, - .codec_mode = S5P_FIMV_CODEC_BPG_DEC, + .codec_mode = MFC_REG_CODEC_BPG_DEC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, diff --git a/drivers/media/platform/exynos/mfc/mfc_dec_ops.c b/drivers/media/platform/exynos/mfc/mfc_dec_ops.c index 1cbd273daf87..cbc0bfc2cfa0 100644 --- a/drivers/media/platform/exynos/mfc/mfc_dec_ops.c +++ b/drivers/media/platform/exynos/mfc/mfc_dec_ops.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_dec_ops.c + * drivers/media/platform/exynos/mfc/mfc_dec_ops.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -16,13 +16,13 @@ #define NUM_CTRL_CFGS ARRAY_SIZE(mfc_ctrl_list) -struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { +struct mfc_ctrl_cfg mfc_ctrl_list[] = { { .type = MFC_CTRL_TYPE_SET, .id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_PICTURE_TAG, + .addr = MFC_REG_D_PICTURE_TAG, .mask = 0xFFFFFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -34,7 +34,7 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_RET_PICTURE_TAG_TOP, + .addr = MFC_REG_D_RET_PICTURE_TAG_TOP, .mask = 0xFFFFFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -46,7 +46,7 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_MFC51_VIDEO_DISPLAY_STATUS, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_DISPLAY_STATUS, + .addr = MFC_REG_D_DISPLAY_STATUS, .mask = 0x7, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -59,7 +59,7 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_LUMA, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_DISPLAY_FIRST_PLANE_CRC, + .addr = MFC_REG_D_DISPLAY_FIRST_PLANE_CRC, .mask = 0xFFFFFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -71,7 +71,7 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_CHROMA, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_DISPLAY_SECOND_PLANE_CRC, + .addr = MFC_REG_D_DISPLAY_SECOND_PLANE_CRC, .mask = 0xFFFFFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -83,7 +83,7 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_CHROMA1, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_DISPLAY_THIRD_PLANE_CRC, + .addr = MFC_REG_D_DISPLAY_THIRD_PLANE_CRC, .mask = 0xFFFFFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -95,7 +95,7 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_2BIT_LUMA, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_DISPLAY_FIRST_PLANE_2BIT_CRC, + .addr = MFC_REG_D_DISPLAY_FIRST_PLANE_2BIT_CRC, .mask = 0xFFFFFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -107,7 +107,7 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_MFC51_VIDEO_CRC_DATA_2BIT_CHROMA, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_DISPLAY_SECOND_PLANE_2BIT_CRC, + .addr = MFC_REG_D_DISPLAY_SECOND_PLANE_2BIT_CRC, .mask = 0xFFFFFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -119,7 +119,7 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_MFC51_VIDEO_CRC_GENERATED, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_DISPLAY_STATUS, + .addr = MFC_REG_D_DISPLAY_STATUS, .mask = 0x1, .shft = 6, .flag_mode = MFC_CTRL_MODE_NONE, @@ -131,7 +131,7 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_H264_SEI_FP_AVAIL, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_SEI_AVAIL, + .addr = MFC_REG_D_SEI_AVAIL, .mask = 0x1, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -143,7 +143,7 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRGMENT_ID, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_FRAME_PACK_ARRGMENT_ID, + .addr = MFC_REG_D_FRAME_PACK_ARRGMENT_ID, .mask = 0xFFFFFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -155,7 +155,7 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_H264_SEI_FP_INFO, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_FRAME_PACK_SEI_INFO, + .addr = MFC_REG_D_FRAME_PACK_SEI_INFO, .mask = 0x3FFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -167,7 +167,7 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_H264_SEI_FP_GRID_POS, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_FRAME_PACK_GRID_POS, + .addr = MFC_REG_D_FRAME_PACK_GRID_POS, .mask = 0xFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -179,7 +179,7 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_H264_MVC_VIEW_ID, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_MVC_VIEW_ID, + .addr = MFC_REG_D_MVC_VIEW_ID, .mask = 0xFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -191,7 +191,7 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_SEI_MAX_PIC_AVERAGE_LIGHT, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_CONTENT_LIGHT_LEVEL_INFO_SEI, + .addr = MFC_REG_D_CONTENT_LIGHT_LEVEL_INFO_SEI, .mask = 0xFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -203,7 +203,7 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_SEI_MAX_CONTENT_LIGHT, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_CONTENT_LIGHT_LEVEL_INFO_SEI, + .addr = MFC_REG_D_CONTENT_LIGHT_LEVEL_INFO_SEI, .mask = 0xFFFF, .shft = 16, .flag_mode = MFC_CTRL_MODE_NONE, @@ -215,7 +215,7 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_SEI_MAX_DISPLAY_LUMINANCE, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_0, + .addr = MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_0, .mask = 0xFFFFFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -227,7 +227,7 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_SEI_MIN_DISPLAY_LUMINANCE, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_1, + .addr = MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_1, .mask = 0xFFFFFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -239,7 +239,7 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_MATRIX_COEFFICIENTS, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_VIDEO_SIGNAL_TYPE, + .addr = MFC_REG_D_VIDEO_SIGNAL_TYPE, .mask = 0xFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -251,7 +251,7 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_FORMAT, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_VIDEO_SIGNAL_TYPE, + .addr = MFC_REG_D_VIDEO_SIGNAL_TYPE, .mask = 0x7, .shft = 26, .flag_mode = MFC_CTRL_MODE_NONE, @@ -263,7 +263,7 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_FULL_RANGE_FLAG, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_VIDEO_SIGNAL_TYPE, + .addr = MFC_REG_D_VIDEO_SIGNAL_TYPE, .mask = 0x1, .shft = 25, .flag_mode = MFC_CTRL_MODE_NONE, @@ -275,7 +275,7 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_COLOUR_PRIMARIES, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_VIDEO_SIGNAL_TYPE, + .addr = MFC_REG_D_VIDEO_SIGNAL_TYPE, .mask = 0xFF, .shft = 16, .flag_mode = MFC_CTRL_MODE_NONE, @@ -287,7 +287,7 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_TRANSFER_CHARACTERISTICS, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_VIDEO_SIGNAL_TYPE, + .addr = MFC_REG_D_VIDEO_SIGNAL_TYPE, .mask = 0xFF, .shft = 8, .flag_mode = MFC_CTRL_MODE_NONE, @@ -299,7 +299,7 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_SEI_WHITE_POINT, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_2, + .addr = MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_2, .mask = 0xFFFFFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -311,7 +311,7 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_SEI_DISPLAY_PRIMARIES_0, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_3, + .addr = MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_3, .mask = 0xFFFFFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -323,7 +323,7 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_SEI_DISPLAY_PRIMARIES_1, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_4, + .addr = MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_4, .mask = 0xFFFFFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -335,7 +335,7 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_SEI_DISPLAY_PRIMARIES_2, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_5, + .addr = MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_5, .mask = 0xFFFFFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -344,13 +344,13 @@ struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { }, }; -static int s5p_mfc_dec_cleanup_ctx_ctrls(struct s5p_mfc_ctx *ctx) +static int mfc_dec_cleanup_ctx_ctrls(struct mfc_ctx *ctx) { - struct s5p_mfc_ctx_ctrl *ctx_ctrl; + struct mfc_ctx_ctrl *ctx_ctrl; while (!list_empty(&ctx->ctrls)) { ctx_ctrl = list_entry((&ctx->ctrls)->next, - struct s5p_mfc_ctx_ctrl, list); + struct mfc_ctx_ctrl, list); list_del(&ctx_ctrl->list); kfree(ctx_ctrl); } @@ -360,22 +360,22 @@ static int s5p_mfc_dec_cleanup_ctx_ctrls(struct s5p_mfc_ctx *ctx) return 0; } -static int s5p_mfc_dec_init_ctx_ctrls(struct s5p_mfc_ctx *ctx) +static int mfc_dec_init_ctx_ctrls(struct mfc_ctx *ctx) { unsigned long i; - struct s5p_mfc_ctx_ctrl *ctx_ctrl; + struct mfc_ctx_ctrl *ctx_ctrl; INIT_LIST_HEAD(&ctx->ctrls); for (i = 0; i < NUM_CTRL_CFGS; i++) { - ctx_ctrl = kzalloc(sizeof(struct s5p_mfc_ctx_ctrl), GFP_KERNEL); + ctx_ctrl = kzalloc(sizeof(struct mfc_ctx_ctrl), GFP_KERNEL); if (ctx_ctrl == NULL) { mfc_err_dev("Failed to allocate context control "\ "id: 0x%08x, type: %d\n", mfc_ctrl_list[i].id, mfc_ctrl_list[i].type); - s5p_mfc_dec_cleanup_ctx_ctrls(ctx); + mfc_dec_cleanup_ctx_ctrls(ctx); return -ENOMEM; } @@ -392,13 +392,13 @@ static int s5p_mfc_dec_init_ctx_ctrls(struct s5p_mfc_ctx *ctx) return 0; } -static void mfc_dec_remove_buf_ctrls(struct list_head *head) +static void __mfc_dec_remove_buf_ctrls(struct list_head *head) { - struct s5p_mfc_buf_ctrl *buf_ctrl; + struct mfc_buf_ctrl *buf_ctrl; while (!list_empty(head)) { buf_ctrl = list_entry(head->next, - struct s5p_mfc_buf_ctrl, list); + struct mfc_buf_ctrl, list); list_del(&buf_ctrl->list); kfree(buf_ctrl); } @@ -406,9 +406,9 @@ static void mfc_dec_remove_buf_ctrls(struct list_head *head) INIT_LIST_HEAD(head); } -static void s5p_mfc_dec_reset_buf_ctrls(struct list_head *head) +static void mfc_dec_reset_buf_ctrls(struct list_head *head) { - struct s5p_mfc_buf_ctrl *buf_ctrl; + struct mfc_buf_ctrl *buf_ctrl; list_for_each_entry(buf_ctrl, head, list) { buf_ctrl->has_new = 0; @@ -418,12 +418,12 @@ static void s5p_mfc_dec_reset_buf_ctrls(struct list_head *head) } } -static int s5p_mfc_dec_init_buf_ctrls(struct s5p_mfc_ctx *ctx, - enum s5p_mfc_ctrl_type type, unsigned int index) +static int mfc_dec_init_buf_ctrls(struct mfc_ctx *ctx, + enum mfc_ctrl_type type, unsigned int index) { unsigned long i; - struct s5p_mfc_ctx_ctrl *ctx_ctrl; - struct s5p_mfc_buf_ctrl *buf_ctrl; + struct mfc_ctx_ctrl *ctx_ctrl; + struct mfc_buf_ctrl *buf_ctrl; struct list_head *head; if (index >= MFC_MAX_BUFFERS) { @@ -433,7 +433,7 @@ static int s5p_mfc_dec_init_buf_ctrls(struct s5p_mfc_ctx *ctx, if (type & MFC_CTRL_TYPE_SRC) { if (test_bit(index, &ctx->src_ctrls_avail)) { - s5p_mfc_dec_reset_buf_ctrls(&ctx->src_ctrls[index]); + mfc_dec_reset_buf_ctrls(&ctx->src_ctrls[index]); return 0; } @@ -441,7 +441,7 @@ static int s5p_mfc_dec_init_buf_ctrls(struct s5p_mfc_ctx *ctx, head = &ctx->src_ctrls[index]; } else if (type & MFC_CTRL_TYPE_DST) { if (test_bit(index, &ctx->dst_ctrls_avail)) { - s5p_mfc_dec_reset_buf_ctrls(&ctx->dst_ctrls[index]); + mfc_dec_reset_buf_ctrls(&ctx->dst_ctrls[index]); return 0; } @@ -471,14 +471,14 @@ static int s5p_mfc_dec_init_buf_ctrls(struct s5p_mfc_ctx *ctx, continue; } - buf_ctrl = kzalloc(sizeof(struct s5p_mfc_buf_ctrl), GFP_KERNEL); + buf_ctrl = kzalloc(sizeof(struct mfc_buf_ctrl), GFP_KERNEL); if (buf_ctrl == NULL) { mfc_err_dev("Failed to allocate buffer control "\ "id: 0x%08x, type: %d\n", mfc_ctrl_list[i].id, mfc_ctrl_list[i].type); - mfc_dec_remove_buf_ctrls(head); + __mfc_dec_remove_buf_ctrls(head); return -ENOMEM; } @@ -498,7 +498,7 @@ static int s5p_mfc_dec_init_buf_ctrls(struct s5p_mfc_ctx *ctx, list_add_tail(&buf_ctrl->list, head); } - s5p_mfc_dec_reset_buf_ctrls(head); + mfc_dec_reset_buf_ctrls(head); if (type & MFC_CTRL_TYPE_SRC) set_bit(index, &ctx->src_ctrls_avail); @@ -508,8 +508,8 @@ static int s5p_mfc_dec_init_buf_ctrls(struct s5p_mfc_ctx *ctx, return 0; } -static int s5p_mfc_dec_cleanup_buf_ctrls(struct s5p_mfc_ctx *ctx, - enum s5p_mfc_ctrl_type type, unsigned int index) +static int mfc_dec_cleanup_buf_ctrls(struct mfc_ctx *ctx, + enum mfc_ctrl_type type, unsigned int index) { struct list_head *head; @@ -535,15 +535,15 @@ static int s5p_mfc_dec_cleanup_buf_ctrls(struct s5p_mfc_ctx *ctx, return -EINVAL; } - mfc_dec_remove_buf_ctrls(head); + __mfc_dec_remove_buf_ctrls(head); return 0; } -static int s5p_mfc_dec_to_buf_ctrls(struct s5p_mfc_ctx *ctx, struct list_head *head) +static int mfc_dec_to_buf_ctrls(struct mfc_ctx *ctx, struct list_head *head) { - struct s5p_mfc_ctx_ctrl *ctx_ctrl; - struct s5p_mfc_buf_ctrl *buf_ctrl; + struct mfc_ctx_ctrl *ctx_ctrl; + struct mfc_buf_ctrl *buf_ctrl; list_for_each_entry(ctx_ctrl, &ctx->ctrls, list) { if (!(ctx_ctrl->type & MFC_CTRL_TYPE_SET) || !ctx_ctrl->has_new) @@ -568,10 +568,10 @@ static int s5p_mfc_dec_to_buf_ctrls(struct s5p_mfc_ctx *ctx, struct list_head *h return 0; } -static int s5p_mfc_dec_to_ctx_ctrls(struct s5p_mfc_ctx *ctx, struct list_head *head) +static int mfc_dec_to_ctx_ctrls(struct mfc_ctx *ctx, struct list_head *head) { - struct s5p_mfc_ctx_ctrl *ctx_ctrl; - struct s5p_mfc_buf_ctrl *buf_ctrl; + struct mfc_ctx_ctrl *ctx_ctrl; + struct mfc_buf_ctrl *buf_ctrl; list_for_each_entry(buf_ctrl, head, list) { if (!(buf_ctrl->type & MFC_CTRL_TYPE_GET) || !buf_ctrl->has_new) @@ -593,11 +593,11 @@ static int s5p_mfc_dec_to_ctx_ctrls(struct s5p_mfc_ctx *ctx, struct list_head *h return 0; } -static int s5p_mfc_dec_set_buf_ctrls_val(struct s5p_mfc_ctx *ctx, struct list_head *head) +static int mfc_dec_set_buf_ctrls_val(struct mfc_ctx *ctx, struct list_head *head) { - struct s5p_mfc_buf_ctrl *buf_ctrl; - struct s5p_mfc_dec *dec = ctx->dec_priv; - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_buf_ctrl *buf_ctrl; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_dev *dev = ctx->dev; unsigned int value = 0; list_for_each_entry(buf_ctrl, head, list) { @@ -636,11 +636,11 @@ static int s5p_mfc_dec_set_buf_ctrls_val(struct s5p_mfc_ctx *ctx, struct list_he return 0; } -static int s5p_mfc_dec_get_buf_ctrls_val(struct s5p_mfc_ctx *ctx, struct list_head *head) +static int mfc_dec_get_buf_ctrls_val(struct mfc_ctx *ctx, struct list_head *head) { - struct s5p_mfc_buf_ctrl *buf_ctrl; - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_dec *dec = ctx->dec_priv; + struct mfc_buf_ctrl *buf_ctrl; + struct mfc_dev *dev = ctx->dev; + struct mfc_dec *dec = ctx->dec_priv; unsigned int value = 0; list_for_each_entry(buf_ctrl, head, list) { @@ -667,11 +667,11 @@ static int s5p_mfc_dec_get_buf_ctrls_val(struct s5p_mfc_ctx *ctx, struct list_he return 0; } -static int s5p_mfc_dec_set_buf_ctrls_val_nal_q_dec(struct s5p_mfc_ctx *ctx, +static int mfc_dec_set_buf_ctrls_val_nal_q_dec(struct mfc_ctx *ctx, struct list_head *head, DecoderInputStr *pInStr) { - struct s5p_mfc_buf_ctrl *buf_ctrl; - struct s5p_mfc_dec *dec = ctx->dec_priv; + struct mfc_buf_ctrl *buf_ctrl; + struct mfc_dec *dec = ctx->dec_priv; mfc_debug_enter(); @@ -702,11 +702,11 @@ static int s5p_mfc_dec_set_buf_ctrls_val_nal_q_dec(struct s5p_mfc_ctx *ctx, return 0; } -static int s5p_mfc_dec_get_buf_ctrls_val_nal_q_dec(struct s5p_mfc_ctx *ctx, +static int mfc_dec_get_buf_ctrls_val_nal_q_dec(struct mfc_ctx *ctx, struct list_head *head, DecoderOutputStr *pOutStr) { - struct s5p_mfc_dec *dec = ctx->dec_priv; - struct s5p_mfc_buf_ctrl *buf_ctrl; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_buf_ctrl *buf_ctrl; unsigned int value = 0; mfc_debug_enter(); @@ -810,10 +810,10 @@ static int s5p_mfc_dec_get_buf_ctrls_val_nal_q_dec(struct s5p_mfc_ctx *ctx, return 0; } -static int s5p_mfc_dec_recover_buf_ctrls_val(struct s5p_mfc_ctx *ctx, struct list_head *head) +static int mfc_dec_recover_buf_ctrls_val(struct mfc_ctx *ctx, struct list_head *head) { - struct s5p_mfc_buf_ctrl *buf_ctrl; - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_buf_ctrl *buf_ctrl; + struct mfc_dev *dev = ctx->dev; unsigned int value = 0; list_for_each_entry(buf_ctrl, head, list) { @@ -842,10 +842,10 @@ static int s5p_mfc_dec_recover_buf_ctrls_val(struct s5p_mfc_ctx *ctx, struct lis return 0; } -static int s5p_mfc_dec_get_buf_update_val(struct s5p_mfc_ctx *ctx, +static int mfc_dec_get_buf_update_val(struct mfc_ctx *ctx, struct list_head *head, unsigned int id, int value) { - struct s5p_mfc_buf_ctrl *buf_ctrl; + struct mfc_buf_ctrl *buf_ctrl; list_for_each_entry(buf_ctrl, head, list) { if (buf_ctrl->id == id) { @@ -859,10 +859,10 @@ static int s5p_mfc_dec_get_buf_update_val(struct s5p_mfc_ctx *ctx, return 0; } -static int s5p_mfc_dec_recover_buf_ctrls_nal_q(struct s5p_mfc_ctx *ctx, +static int mfc_dec_recover_buf_ctrls_nal_q(struct mfc_ctx *ctx, struct list_head *head) { - struct s5p_mfc_buf_ctrl *buf_ctrl; + struct mfc_buf_ctrl *buf_ctrl; list_for_each_entry(buf_ctrl, head, list) { if (!(buf_ctrl->type & MFC_CTRL_TYPE_SET) @@ -878,19 +878,19 @@ static int s5p_mfc_dec_recover_buf_ctrls_nal_q(struct s5p_mfc_ctx *ctx, return 0; } -struct s5p_mfc_ctrls_ops decoder_ctrls_ops = { - .init_ctx_ctrls = s5p_mfc_dec_init_ctx_ctrls, - .cleanup_ctx_ctrls = s5p_mfc_dec_cleanup_ctx_ctrls, - .init_buf_ctrls = s5p_mfc_dec_init_buf_ctrls, - .reset_buf_ctrls = s5p_mfc_dec_reset_buf_ctrls, - .cleanup_buf_ctrls = s5p_mfc_dec_cleanup_buf_ctrls, - .to_buf_ctrls = s5p_mfc_dec_to_buf_ctrls, - .to_ctx_ctrls = s5p_mfc_dec_to_ctx_ctrls, - .set_buf_ctrls_val = s5p_mfc_dec_set_buf_ctrls_val, - .get_buf_ctrls_val = s5p_mfc_dec_get_buf_ctrls_val, - .set_buf_ctrls_val_nal_q_dec = s5p_mfc_dec_set_buf_ctrls_val_nal_q_dec, - .get_buf_ctrls_val_nal_q_dec = s5p_mfc_dec_get_buf_ctrls_val_nal_q_dec, - .recover_buf_ctrls_val = s5p_mfc_dec_recover_buf_ctrls_val, - .get_buf_update_val = s5p_mfc_dec_get_buf_update_val, - .recover_buf_ctrls_nal_q = s5p_mfc_dec_recover_buf_ctrls_nal_q, +struct mfc_ctrls_ops decoder_ctrls_ops = { + .init_ctx_ctrls = mfc_dec_init_ctx_ctrls, + .cleanup_ctx_ctrls = mfc_dec_cleanup_ctx_ctrls, + .init_buf_ctrls = mfc_dec_init_buf_ctrls, + .reset_buf_ctrls = mfc_dec_reset_buf_ctrls, + .cleanup_buf_ctrls = mfc_dec_cleanup_buf_ctrls, + .to_buf_ctrls = mfc_dec_to_buf_ctrls, + .to_ctx_ctrls = mfc_dec_to_ctx_ctrls, + .set_buf_ctrls_val = mfc_dec_set_buf_ctrls_val, + .get_buf_ctrls_val = mfc_dec_get_buf_ctrls_val, + .set_buf_ctrls_val_nal_q_dec = mfc_dec_set_buf_ctrls_val_nal_q_dec, + .get_buf_ctrls_val_nal_q_dec = mfc_dec_get_buf_ctrls_val_nal_q_dec, + .recover_buf_ctrls_val = mfc_dec_recover_buf_ctrls_val, + .get_buf_update_val = mfc_dec_get_buf_update_val, + .recover_buf_ctrls_nal_q = mfc_dec_recover_buf_ctrls_nal_q, }; diff --git a/drivers/media/platform/exynos/mfc/mfc_dec_vb2_ops.c b/drivers/media/platform/exynos/mfc/mfc_dec_vb2_ops.c index dbe739f85354..a07446e16b59 100644 --- a/drivers/media/platform/exynos/mfc/mfc_dec_vb2_ops.c +++ b/drivers/media/platform/exynos/mfc/mfc_dec_vb2_ops.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_dec_vb2_ops.c + * drivers/media/platform/exynos/mfc/mfc_dec_vb2_ops.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -22,14 +22,14 @@ #include "mfc_buf.h" #include "mfc_mem.h" -static int s5p_mfc_dec_queue_setup(struct vb2_queue *vq, +static int mfc_dec_queue_setup(struct vb2_queue *vq, unsigned int *buf_count, unsigned int *plane_count, unsigned int psize[], struct device *alloc_devs[]) { - struct s5p_mfc_ctx *ctx; - struct s5p_mfc_dev *dev; - struct s5p_mfc_dec *dec; - struct s5p_mfc_raw_info *raw; + struct mfc_ctx *ctx; + struct mfc_dev *dev; + struct mfc_dec *dec; + struct mfc_raw_info *raw; int i; mfc_debug_enter(); @@ -109,10 +109,10 @@ static int s5p_mfc_dec_queue_setup(struct vb2_queue *vq, return 0; } -static void s5p_mfc_dec_unlock(struct vb2_queue *q) +static void mfc_dec_unlock(struct vb2_queue *q) { - struct s5p_mfc_ctx *ctx = q->drv_priv; - struct s5p_mfc_dev *dev; + struct mfc_ctx *ctx = q->drv_priv; + struct mfc_dev *dev; if (!ctx) { mfc_err_dev("no mfc context to run\n"); @@ -127,10 +127,10 @@ static void s5p_mfc_dec_unlock(struct vb2_queue *q) mutex_unlock(&dev->mfc_mutex); } -static void s5p_mfc_dec_lock(struct vb2_queue *q) +static void mfc_dec_lock(struct vb2_queue *q) { - struct s5p_mfc_ctx *ctx = q->drv_priv; - struct s5p_mfc_dev *dev; + struct mfc_ctx *ctx = q->drv_priv; + struct mfc_dev *dev; if (!ctx) { mfc_err_dev("no mfc context to run\n"); @@ -145,13 +145,13 @@ static void s5p_mfc_dec_lock(struct vb2_queue *q) mutex_lock(&dev->mfc_mutex); } -static int s5p_mfc_dec_buf_init(struct vb2_buffer *vb) +static int mfc_dec_buf_init(struct vb2_buffer *vb) { struct vb2_queue *vq = vb->vb2_queue; - struct s5p_mfc_ctx *ctx = vq->drv_priv; - struct s5p_mfc_dev *dev; - struct s5p_mfc_dec *dec; - struct s5p_mfc_buf *buf = vb_to_mfc_buf(vb); + struct mfc_ctx *ctx = vq->drv_priv; + struct mfc_dev *dev; + struct mfc_dec *dec; + struct mfc_buf *buf = vb_to_mfc_buf(vb); dma_addr_t start_raw; int i, ret; @@ -172,11 +172,11 @@ static int s5p_mfc_dec_buf_init(struct vb2_buffer *vb) } if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { - ret = s5p_mfc_check_vb_with_fmt(ctx->dst_fmt, vb); + ret = mfc_check_vb_with_fmt(ctx->dst_fmt, vb); if (ret < 0) return ret; - start_raw = s5p_mfc_mem_get_daddr_vb(vb, 0); + start_raw = mfc_mem_get_daddr_vb(vb, 0); if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV12N) { buf->addr[0][0] = start_raw; buf->addr[0][1] = NV12N_CBCR_BASE(start_raw, @@ -197,24 +197,24 @@ static int s5p_mfc_dec_buf_init(struct vb2_buffer *vb) ctx->img_height); } else { for (i = 0; i < ctx->dst_fmt->mem_planes; i++) - buf->addr[0][i] = s5p_mfc_mem_get_daddr_vb(vb, i); + buf->addr[0][i] = mfc_mem_get_daddr_vb(vb, i); } if (call_cop(ctx, init_buf_ctrls, ctx, MFC_CTRL_TYPE_DST, vb->index) < 0) mfc_err_ctx("failed in init_buf_ctrls\n"); } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { - ret = s5p_mfc_check_vb_with_fmt(ctx->src_fmt, vb); + ret = mfc_check_vb_with_fmt(ctx->src_fmt, vb); if (ret < 0) return ret; - buf->addr[0][0] = s5p_mfc_mem_get_daddr_vb(vb, 0); + buf->addr[0][0] = mfc_mem_get_daddr_vb(vb, 0); if (call_cop(ctx, init_buf_ctrls, ctx, MFC_CTRL_TYPE_SRC, vb->index) < 0) mfc_err_ctx("failed in init_buf_ctrls\n"); } else { - mfc_err_ctx("s5p_mfc_dec_buf_init: unknown queue type\n"); + mfc_err_ctx("mfc_dec_buf_init: unknown queue type\n"); return -EINVAL; } @@ -223,12 +223,12 @@ static int s5p_mfc_dec_buf_init(struct vb2_buffer *vb) return 0; } -static int s5p_mfc_dec_buf_prepare(struct vb2_buffer *vb) +static int mfc_dec_buf_prepare(struct vb2_buffer *vb) { struct vb2_queue *vq = vb->vb2_queue; - struct s5p_mfc_ctx *ctx = vq->drv_priv; - struct s5p_mfc_dec *dec; - struct s5p_mfc_raw_info *raw; + struct mfc_ctx *ctx = vq->drv_priv; + struct mfc_dec *dec; + struct mfc_raw_info *raw; unsigned int index = vb->index; size_t buf_size; int i; @@ -284,10 +284,10 @@ static int s5p_mfc_dec_buf_prepare(struct vb2_buffer *vb) return 0; } -static void s5p_mfc_dec_buf_finish(struct vb2_buffer *vb) +static void mfc_dec_buf_finish(struct vb2_buffer *vb) { struct vb2_queue *vq = vb->vb2_queue; - struct s5p_mfc_ctx *ctx = vq->drv_priv; + struct mfc_ctx *ctx = vq->drv_priv; unsigned int index = vb->index; if (!ctx) { @@ -304,10 +304,10 @@ static void s5p_mfc_dec_buf_finish(struct vb2_buffer *vb) } } -static void s5p_mfc_dec_buf_cleanup(struct vb2_buffer *vb) +static void mfc_dec_buf_cleanup(struct vb2_buffer *vb) { struct vb2_queue *vq = vb->vb2_queue; - struct s5p_mfc_ctx *ctx = vq->drv_priv; + struct mfc_ctx *ctx = vq->drv_priv; unsigned int index = vb->index; mfc_debug_enter(); @@ -325,16 +325,16 @@ static void s5p_mfc_dec_buf_cleanup(struct vb2_buffer *vb) MFC_CTRL_TYPE_SRC, index) < 0) mfc_err_ctx("failed in cleanup_buf_ctrls\n"); } else { - mfc_err_ctx("s5p_mfc_dec_buf_cleanup: unknown queue type\n"); + mfc_err_ctx("mfc_dec_buf_cleanup: unknown queue type\n"); } mfc_debug_leave(); } -static int s5p_mfc_dec_start_streaming(struct vb2_queue *q, unsigned int count) +static int mfc_dec_start_streaming(struct vb2_queue *q, unsigned int count) { - struct s5p_mfc_ctx *ctx = q->drv_priv; - struct s5p_mfc_dev *dev; + struct mfc_ctx *ctx = q->drv_priv; + struct mfc_dev *dev; if (!ctx) { mfc_err_dev("no mfc context to run\n"); @@ -348,23 +348,23 @@ static int s5p_mfc_dec_start_streaming(struct vb2_queue *q, unsigned int count) } if (ctx->state == MFCINST_FINISHING) - s5p_mfc_change_state(ctx, MFCINST_RUNNING); + mfc_change_state(ctx, MFCINST_RUNNING); /* If context is ready then dev = work->data;schedule it to run */ - if (s5p_mfc_dec_ctx_ready(ctx)) { - s5p_mfc_set_bit(ctx->num, &dev->work_bits); + if (mfc_dec_ctx_ready(ctx)) { + mfc_set_bit(ctx->num, &dev->work_bits); } - s5p_mfc_try_run(dev); + mfc_try_run(dev); return 0; } -static void mfc_dec_src_stop_streaming(struct s5p_mfc_ctx *ctx) +static void __mfc_dec_src_stop_streaming(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev; - struct s5p_mfc_dec *dec; - struct s5p_mfc_buf *src_mb; + struct mfc_dev *dev; + struct mfc_dec *dec; + struct mfc_buf *src_mb; int index, csd, condition = 0; int ret = 0; @@ -381,43 +381,43 @@ static void mfc_dec_src_stop_streaming(struct s5p_mfc_ctx *ctx) } while (1) { - csd = s5p_mfc_peek_buf_csd(&ctx->buf_queue_lock, &ctx->src_buf_queue); + csd = mfc_peek_buf_csd(&ctx->buf_queue_lock, &ctx->src_buf_queue); if (csd == 1) { - s5p_mfc_clean_ctx_int_flags(ctx); + mfc_clean_ctx_int_flags(ctx); if (need_to_special_parsing(ctx)) { - s5p_mfc_change_state(ctx, MFCINST_SPECIAL_PARSING); - condition = S5P_FIMV_R2H_CMD_SEQ_DONE_RET; + mfc_change_state(ctx, MFCINST_SPECIAL_PARSING); + condition = MFC_REG_R2H_CMD_SEQ_DONE_RET; mfc_info_ctx("try to special parsing! (before NAL_START)\n"); } else if (need_to_special_parsing_nal(ctx)) { - s5p_mfc_change_state(ctx, MFCINST_SPECIAL_PARSING_NAL); - condition = S5P_FIMV_R2H_CMD_FRAME_DONE_RET; + mfc_change_state(ctx, MFCINST_SPECIAL_PARSING_NAL); + condition = MFC_REG_R2H_CMD_FRAME_DONE_RET; mfc_info_ctx("try to special parsing! (after NAL_START)\n"); } else { mfc_info_ctx("can't parsing CSD!, state = %d\n", ctx->state); } if (condition) { - s5p_mfc_set_bit(ctx->num, &dev->work_bits); + mfc_set_bit(ctx->num, &dev->work_bits); - ret = s5p_mfc_just_run(dev, ctx->num); + ret = mfc_just_run(dev, ctx->num); if (ret) { mfc_err_ctx("Failed to run MFC\n"); } else { - if (s5p_mfc_wait_for_done_ctx(ctx, condition)) + if (mfc_wait_for_done_ctx(ctx, condition)) mfc_err_ctx("special parsing time out\n"); } } } - src_mb = s5p_mfc_get_del_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, MFC_BUF_NO_TOUCH_USED); + src_mb = mfc_get_del_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, MFC_BUF_NO_TOUCH_USED); if (!src_mb) break; index = src_mb->vb.vb2_buf.index; if (ctx->is_drm) - s5p_mfc_stream_unprotect(ctx, src_mb, index); + mfc_stream_unprotect(ctx, src_mb, index); vb2_set_plane_payload(&src_mb->vb.vb2_buf, 0, 0); vb2_buffer_done(&src_mb->vb.vb2_buf, VB2_BUF_STATE_ERROR); } @@ -426,7 +426,7 @@ static void mfc_dec_src_stop_streaming(struct s5p_mfc_ctx *ctx) dec->remained_size = 0; ctx->check_dump = 0; - s5p_mfc_init_queue(&ctx->src_buf_queue); + mfc_init_queue(&ctx->src_buf_queue); index = 0; while (index < MFC_MAX_BUFFERS) { @@ -438,9 +438,9 @@ static void mfc_dec_src_stop_streaming(struct s5p_mfc_ctx *ctx) } } -static void mfc_dec_dst_stop_streaming(struct s5p_mfc_ctx *ctx) +static void __mfc_dec_dst_stop_streaming(struct mfc_ctx *ctx) { - struct s5p_mfc_dec *dec; + struct mfc_dec *dec; int index = 0; dec = ctx->dec_priv; @@ -449,21 +449,21 @@ static void mfc_dec_dst_stop_streaming(struct s5p_mfc_ctx *ctx) return; } - s5p_mfc_cleanup_assigned_fd(ctx); - s5p_mfc_cleanup_queue(&ctx->buf_queue_lock, &ctx->ref_buf_queue); + mfc_cleanup_assigned_fd(ctx); + mfc_cleanup_queue(&ctx->buf_queue_lock, &ctx->ref_buf_queue); dec->dynamic_used = 0; dec->err_reuse_flag = 0; dec->dec_only_release_flag = 0; - s5p_mfc_cleanup_queue(&ctx->buf_queue_lock, &ctx->dst_buf_queue); + mfc_cleanup_queue(&ctx->buf_queue_lock, &ctx->dst_buf_queue); ctx->is_dpb_realloc = 0; dec->available_dpb = 0; dec->y_addr_for_pb = 0; - s5p_mfc_cleanup_assigned_dpb(ctx); + mfc_cleanup_assigned_dpb(ctx); while (index < MFC_MAX_BUFFERS) { index = find_next_bit(&ctx->dst_ctrls_avail, @@ -480,10 +480,10 @@ static void mfc_dec_dst_stop_streaming(struct s5p_mfc_ctx *ctx) } } -static void s5p_mfc_dec_stop_streaming(struct vb2_queue *q) +static void mfc_dec_stop_streaming(struct vb2_queue *q) { - struct s5p_mfc_ctx *ctx = q->drv_priv; - struct s5p_mfc_dev *dev; + struct mfc_ctx *ctx = q->drv_priv; + struct mfc_dev *dev; int ret = 0; int prev_state; @@ -504,61 +504,61 @@ static void s5p_mfc_dec_stop_streaming(struct vb2_queue *q) MFC_TRACE_CTX_HWLOCK("**DEC streamoff(type:%d)\n", q->type); /* If a H/W operation is in progress, wait for it complete */ - ret = s5p_mfc_get_hwlock_ctx(ctx); + ret = mfc_get_hwlock_ctx(ctx); if (ret < 0) { mfc_err_ctx("Failed to get hwlock\n"); return; } if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) - mfc_dec_dst_stop_streaming(ctx); + __mfc_dec_dst_stop_streaming(ctx); else if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) - mfc_dec_src_stop_streaming(ctx); + __mfc_dec_src_stop_streaming(ctx); if (ctx->state == MFCINST_FINISHING) - s5p_mfc_change_state(ctx, MFCINST_RUNNING); + mfc_change_state(ctx, MFCINST_RUNNING); if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE && need_to_dpb_flush(ctx)) { prev_state = ctx->state; - s5p_mfc_change_state(ctx, MFCINST_DPB_FLUSHING); - s5p_mfc_set_bit(ctx->num, &dev->work_bits); - s5p_mfc_clean_ctx_int_flags(ctx); + mfc_change_state(ctx, MFCINST_DPB_FLUSHING); + mfc_set_bit(ctx->num, &dev->work_bits); + mfc_clean_ctx_int_flags(ctx); mfc_info_ctx("try to DPB flush\n"); - ret = s5p_mfc_just_run(dev, ctx->num); + ret = mfc_just_run(dev, ctx->num); if (ret) { mfc_err_ctx("Failed to run MFC\n"); - s5p_mfc_release_hwlock_ctx(ctx); - s5p_mfc_cleanup_work_bit_and_try_run(ctx); + mfc_release_hwlock_ctx(ctx); + mfc_cleanup_work_bit_and_try_run(ctx); return; } - if (s5p_mfc_wait_for_done_ctx(ctx, S5P_FIMV_R2H_CMD_DPB_FLUSH_RET)) { + if (mfc_wait_for_done_ctx(ctx, MFC_REG_R2H_CMD_DPB_FLUSH_RET)) { mfc_err_ctx("time out during DPB flush\n"); dev->logging_data->cause |= (1 << MFC_CAUSE_FAIL_DPB_FLUSH); call_dop(dev, dump_and_stop_always, dev); } - s5p_mfc_change_state(ctx, prev_state); + mfc_change_state(ctx, prev_state); } mfc_debug(2, "buffer cleanup & flush is done in stop_streaming, type : %d\n", q->type); - s5p_mfc_clear_bit(ctx->num, &dev->work_bits); - s5p_mfc_release_hwlock_ctx(ctx); + mfc_clear_bit(ctx->num, &dev->work_bits); + mfc_release_hwlock_ctx(ctx); - if (s5p_mfc_dec_ctx_ready(ctx)) - s5p_mfc_set_bit(ctx->num, &dev->work_bits); - if (s5p_mfc_is_work_to_do(dev)) + if (mfc_dec_ctx_ready(ctx)) + mfc_set_bit(ctx->num, &dev->work_bits); + if (mfc_is_work_to_do(dev)) queue_work(dev->butler_wq, &dev->butler_work); } -static void s5p_mfc_dec_buf_queue(struct vb2_buffer *vb) +static void mfc_dec_buf_queue(struct vb2_buffer *vb) { struct vb2_queue *vq = vb->vb2_queue; - struct s5p_mfc_ctx *ctx = vq->drv_priv; - struct s5p_mfc_dev *dev; - struct s5p_mfc_dec *dec; - struct s5p_mfc_buf *buf = vb_to_mfc_buf(vb); + struct mfc_ctx *ctx = vq->drv_priv; + struct mfc_dev *dev; + struct mfc_dec *dec; + struct mfc_buf *buf = vb_to_mfc_buf(vb); int i; unsigned char *stream_vir = NULL; @@ -589,7 +589,7 @@ static void s5p_mfc_dec_buf_queue(struct vb2_buffer *vb) buf->vir_addr = stream_vir; - s5p_mfc_add_tail_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, buf); + mfc_add_tail_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, buf); MFC_TRACE_CTX("Q src[%d] fd: %d, %#llx\n", vb->index, vb->planes[0].m.fd, buf->addr[0][0]); @@ -597,10 +597,10 @@ static void s5p_mfc_dec_buf_queue(struct vb2_buffer *vb) for (i = 0; i < ctx->dst_fmt->mem_planes; i++) mfc_debug(2, "[BUFINFO] ctx[%d] add dst index: %d, addr[%d]: 0x%08llx\n", ctx->num, vb->index, i, buf->addr[0][i]); - s5p_mfc_store_dpb(ctx, vb); + mfc_store_dpb(ctx, vb); if ((dec->dst_memtype == V4L2_MEMORY_USERPTR || dec->dst_memtype == V4L2_MEMORY_DMABUF) && - s5p_mfc_is_queue_count_same(&ctx->buf_queue_lock, + mfc_is_queue_count_same(&ctx->buf_queue_lock, &ctx->dst_buf_queue, dec->total_dpb_count)) ctx->capture_state = QUEUE_BUFS_MMAPED; @@ -611,23 +611,23 @@ static void s5p_mfc_dec_buf_queue(struct vb2_buffer *vb) mfc_err_ctx("Unsupported buffer type (%d)\n", vq->type); } - if (s5p_mfc_dec_ctx_ready(ctx)) { - s5p_mfc_set_bit(ctx->num, &dev->work_bits); - s5p_mfc_try_run(dev); + if (mfc_dec_ctx_ready(ctx)) { + mfc_set_bit(ctx->num, &dev->work_bits); + mfc_try_run(dev); } mfc_debug_leave(); } -struct vb2_ops s5p_mfc_dec_qops = { - .queue_setup = s5p_mfc_dec_queue_setup, - .wait_prepare = s5p_mfc_dec_unlock, - .wait_finish = s5p_mfc_dec_lock, - .buf_init = s5p_mfc_dec_buf_init, - .buf_prepare = s5p_mfc_dec_buf_prepare, - .buf_finish = s5p_mfc_dec_buf_finish, - .buf_cleanup = s5p_mfc_dec_buf_cleanup, - .start_streaming = s5p_mfc_dec_start_streaming, - .stop_streaming = s5p_mfc_dec_stop_streaming, - .buf_queue = s5p_mfc_dec_buf_queue, +struct vb2_ops mfc_dec_qops = { + .queue_setup = mfc_dec_queue_setup, + .wait_prepare = mfc_dec_unlock, + .wait_finish = mfc_dec_lock, + .buf_init = mfc_dec_buf_init, + .buf_prepare = mfc_dec_buf_prepare, + .buf_finish = mfc_dec_buf_finish, + .buf_cleanup = mfc_dec_buf_cleanup, + .start_streaming = mfc_dec_start_streaming, + .stop_streaming = mfc_dec_stop_streaming, + .buf_queue = mfc_dec_buf_queue, }; diff --git a/drivers/media/platform/exynos/mfc/mfc_enc.c b/drivers/media/platform/exynos/mfc/mfc_enc.c index f32c507119dd..ab5249b9f3ba 100644 --- a/drivers/media/platform/exynos/mfc/mfc_enc.c +++ b/drivers/media/platform/exynos/mfc/mfc_enc.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_enc.c + * drivers/media/platform/exynos/mfc/mfc_enc.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -24,16 +24,16 @@ #include "mfc_buf.h" #include "mfc_mem.h" -static struct s5p_mfc_fmt *mfc_enc_find_format(struct s5p_mfc_ctx *ctx, +static struct mfc_fmt *__mfc_enc_find_format(struct mfc_ctx *ctx, unsigned int pixelformat) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_fmt *fmt = NULL; + struct mfc_dev *dev = ctx->dev; + struct mfc_fmt *fmt = NULL; unsigned long i; for (i = 0; i < NUM_FORMATS; i++) { if (enc_formats[i].fourcc == pixelformat) { - fmt = (struct s5p_mfc_fmt *)&enc_formats[i]; + fmt = (struct mfc_fmt *)&enc_formats[i]; break; } } @@ -54,7 +54,7 @@ static struct s5p_mfc_fmt *mfc_enc_find_format(struct s5p_mfc_ctx *ctx, return fmt; } -static struct v4l2_queryctrl *mfc_enc_get_ctrl(int id) +static struct v4l2_queryctrl *__mfc_enc_get_ctrl(int id) { unsigned long i; @@ -64,11 +64,11 @@ static struct v4l2_queryctrl *mfc_enc_get_ctrl(int id) return NULL; } -static int mfc_enc_check_ctrl_val(struct s5p_mfc_ctx *ctx, struct v4l2_control *ctrl) +static int __mfc_enc_check_ctrl_val(struct mfc_ctx *ctx, struct v4l2_control *ctrl) { struct v4l2_queryctrl *c; - c = mfc_enc_get_ctrl(ctrl->id); + c = __mfc_enc_get_ctrl(ctrl->id); if (!c) { mfc_err_ctx("[CTRLS] not supported control id (%#x)\n", ctrl->id); return -EINVAL; @@ -102,25 +102,25 @@ static int mfc_enc_check_ctrl_val(struct s5p_mfc_ctx *ctx, struct v4l2_control * return 0; } -static inline int mfc_enc_h264_profile(struct s5p_mfc_ctx *ctx, int profile) +static inline int __mfc_enc_h264_profile(struct mfc_ctx *ctx, int profile) { int ret = 0; switch (profile) { case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN: - ret = S5P_FIMV_E_PROFILE_H264_MAIN; + ret = MFC_REG_E_PROFILE_H264_MAIN; break; case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH: - ret = S5P_FIMV_E_PROFILE_H264_HIGH; + ret = MFC_REG_E_PROFILE_H264_HIGH; break; case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE: - ret = S5P_FIMV_E_PROFILE_H264_BASELINE; + ret = MFC_REG_E_PROFILE_H264_BASELINE; break; case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE: - ret = S5P_FIMV_E_PROFILE_H264_CONSTRAINED_BASELINE; + ret = MFC_REG_E_PROFILE_H264_CONSTRAINED_BASELINE; break; case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH: - ret = S5P_FIMV_E_PROFILE_H264_CONSTRAINED_HIGH; + ret = MFC_REG_E_PROFILE_H264_CONSTRAINED_HIGH; break; default: ret = -EINVAL; @@ -149,10 +149,10 @@ static int vidioc_querycap(struct file *file, void *priv, return 0; } -static int mfc_enc_enum_fmt(struct s5p_mfc_dev *dev, struct v4l2_fmtdesc *f, +static int __mfc_enc_enum_fmt(struct mfc_dev *dev, struct v4l2_fmtdesc *f, unsigned int type) { - struct s5p_mfc_fmt *fmt; + struct mfc_fmt *fmt; unsigned long i, j = 0; for (i = 0; i < NUM_FORMATS; ++i) { @@ -183,25 +183,25 @@ static int mfc_enc_enum_fmt(struct s5p_mfc_dev *dev, struct v4l2_fmtdesc *f, static int vidioc_enum_fmt_vid_cap_mplane(struct file *file, void *pirv, struct v4l2_fmtdesc *f) { - struct s5p_mfc_dev *dev = video_drvdata(file); + struct mfc_dev *dev = video_drvdata(file); - return mfc_enc_enum_fmt(dev, f, MFC_FMT_STREAM); + return __mfc_enc_enum_fmt(dev, f, MFC_FMT_STREAM); } static int vidioc_enum_fmt_vid_out_mplane(struct file *file, void *prov, struct v4l2_fmtdesc *f) { - struct s5p_mfc_dev *dev = video_drvdata(file); + struct mfc_dev *dev = video_drvdata(file); - return mfc_enc_enum_fmt(dev, f, MFC_FMT_FRAME); + return __mfc_enc_enum_fmt(dev, f, MFC_FMT_FRAME); } static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); - struct s5p_mfc_enc *enc = ctx->enc_priv; + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_enc *enc = ctx->enc_priv; struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp; - struct s5p_mfc_raw_info *raw; + struct mfc_raw_info *raw; int i; mfc_debug_enter(); @@ -243,11 +243,11 @@ static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f) static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); - struct s5p_mfc_fmt *fmt; + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_fmt *fmt; struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp; - fmt = mfc_enc_find_format(ctx, pix_fmt_mp->pixelformat); + fmt = __mfc_enc_find_format(ctx, pix_fmt_mp->pixelformat); if (!fmt) { mfc_err_dev("Unsupported format for %s\n", V4L2_TYPE_IS_OUTPUT(f->type) ? "source" : "destination"); @@ -257,7 +257,7 @@ static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f) return 0; } -static void mfc_enc_check_format(struct s5p_mfc_ctx *ctx) +static void __mfc_enc_check_format(struct mfc_ctx *ctx) { switch (ctx->src_fmt->fourcc) { case V4L2_PIX_FMT_NV16M_S10B: @@ -290,13 +290,13 @@ static void mfc_enc_check_format(struct s5p_mfc_ctx *ctx) mfc_debug(2, "[FRAME] 10bit: %d, 422: %d\n", ctx->is_10bit, ctx->is_422); } -static int mfc_enc_check_resolution(struct s5p_mfc_ctx *ctx) +static int __mfc_enc_check_resolution(struct mfc_ctx *ctx) { int max_width = 0, max_height = 0, min_width = 0, min_height = 0, swap_check = 0; /* Check max resolution */ switch (ctx->codec_mode) { - case S5P_FIMV_CODEC_HEVC_ENC: + case MFC_REG_CODEC_HEVC_ENC: if (ctx->is_422) { max_width = 65536; max_height = 8192; @@ -306,25 +306,25 @@ static int mfc_enc_check_resolution(struct s5p_mfc_ctx *ctx) max_height = 8192; } break; - case S5P_FIMV_CODEC_BPG_ENC: + case MFC_REG_CODEC_BPG_ENC: max_width = 65536; max_height = 8192; swap_check = 1; break; - case S5P_FIMV_CODEC_H264_ENC: - case S5P_FIMV_CODEC_VP8_ENC: + case MFC_REG_CODEC_H264_ENC: + case MFC_REG_CODEC_VP8_ENC: max_width = 8192; max_height = 8192; break; - case S5P_FIMV_CODEC_VP9_ENC: + case MFC_REG_CODEC_VP9_ENC: max_width = 4096; max_height = 8192; break; - case S5P_FIMV_CODEC_MPEG4_ENC: + case MFC_REG_CODEC_MPEG4_ENC: max_width = 2048; max_height = 2048; break; - case S5P_FIMV_CODEC_H263_ENC: + case MFC_REG_CODEC_H263_ENC: max_width = 2048; max_height = 1152; break; @@ -351,16 +351,16 @@ static int mfc_enc_check_resolution(struct s5p_mfc_ctx *ctx) /* Check min resolution */ switch (ctx->codec_mode) { - case S5P_FIMV_CODEC_HEVC_ENC: - case S5P_FIMV_CODEC_BPG_ENC: - case S5P_FIMV_CODEC_VP9_ENC: + case MFC_REG_CODEC_HEVC_ENC: + case MFC_REG_CODEC_BPG_ENC: + case MFC_REG_CODEC_VP9_ENC: min_width = 64; min_height = 64; break; - case S5P_FIMV_CODEC_H264_ENC: - case S5P_FIMV_CODEC_VP8_ENC: - case S5P_FIMV_CODEC_MPEG4_ENC: - case S5P_FIMV_CODEC_H263_ENC: + case MFC_REG_CODEC_H264_ENC: + case MFC_REG_CODEC_VP8_ENC: + case MFC_REG_CODEC_MPEG4_ENC: + case MFC_REG_CODEC_H263_ENC: min_width = 32; min_height = 32; break; @@ -381,9 +381,9 @@ static int mfc_enc_check_resolution(struct s5p_mfc_ctx *ctx) static int vidioc_s_fmt_vid_cap_mplane(struct file *file, void *priv, struct v4l2_format *f) { - struct s5p_mfc_dev *dev = video_drvdata(file); - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); - struct s5p_mfc_enc *enc = ctx->enc_priv; + struct mfc_dev *dev = video_drvdata(file); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_enc *enc = ctx->enc_priv; struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp; int ret = 0; @@ -394,7 +394,7 @@ static int vidioc_s_fmt_vid_cap_mplane(struct file *file, void *priv, return -EBUSY; } - ctx->dst_fmt = mfc_enc_find_format(ctx, pix_fmt_mp->pixelformat); + ctx->dst_fmt = __mfc_enc_find_format(ctx, pix_fmt_mp->pixelformat); if (!ctx->dst_fmt) { mfc_err_ctx("Unsupported format for destination\n"); return -EINVAL; @@ -404,7 +404,7 @@ static int vidioc_s_fmt_vid_cap_mplane(struct file *file, void *priv, mfc_info_ctx("[STREAM] Enc dst codec(%d) : %s\n", ctx->codec_mode, ctx->dst_fmt->name); - if (mfc_enc_check_resolution(ctx)) { + if (__mfc_enc_check_resolution(ctx)) { mfc_err_ctx("Unsupported resolution\n"); return -EINVAL; } @@ -415,9 +415,9 @@ static int vidioc_s_fmt_vid_cap_mplane(struct file *file, void *priv, mfc_err_ctx("[OTF] only H.264 and HEVC is supported\n"); return -EINVAL; } - if (s5p_mfc_otf_init(ctx)) { + if (mfc_otf_init(ctx)) { mfc_err_ctx("[OTF] otf_init failed\n"); - s5p_mfc_otf_destroy(ctx); + mfc_otf_destroy(ctx); return -EINVAL; } } @@ -425,63 +425,63 @@ static int vidioc_s_fmt_vid_cap_mplane(struct file *file, void *priv, enc->dst_buf_size = pix_fmt_mp->plane_fmt[0].sizeimage; pix_fmt_mp->plane_fmt[0].bytesperline = 0; - ret = s5p_mfc_alloc_instance_context(ctx); + ret = mfc_alloc_instance_context(ctx); if (ret) { mfc_err_ctx("Failed to allocate enc instance[%d] buffers\n", ctx->num); return -ENOMEM; } - s5p_mfc_change_state(ctx, MFCINST_INIT); + mfc_change_state(ctx, MFCINST_INIT); ctx->capture_state = QUEUE_FREE; - ret = s5p_mfc_alloc_enc_roi_buffer(ctx); + ret = mfc_alloc_enc_roi_buffer(ctx); if (ret) { mfc_err_ctx("[ROI] Failed to allocate ROI buffers\n"); - s5p_mfc_release_instance_context(ctx); + mfc_release_instance_context(ctx); return -ENOMEM; } MFC_TRACE_CTX_HWLOCK("**ENC s_fmt\n"); - ret = s5p_mfc_get_hwlock_ctx(ctx); + ret = mfc_get_hwlock_ctx(ctx); if (ret < 0) { mfc_err_dev("Failed to get hwlock\n"); - s5p_mfc_release_instance_context(ctx); - s5p_mfc_release_enc_roi_buffer(ctx); + mfc_release_instance_context(ctx); + mfc_release_enc_roi_buffer(ctx); return -EBUSY; } - s5p_mfc_set_bit(ctx->num, &dev->work_bits); - ret = s5p_mfc_just_run(dev, ctx->num); + mfc_set_bit(ctx->num, &dev->work_bits); + ret = mfc_just_run(dev, ctx->num); if (ret) { mfc_err_ctx("Failed to run MFC\n"); - s5p_mfc_release_hwlock_ctx(ctx); - s5p_mfc_cleanup_work_bit_and_try_run(ctx); - s5p_mfc_release_instance_context(ctx); - s5p_mfc_release_enc_roi_buffer(ctx); + mfc_release_hwlock_ctx(ctx); + mfc_cleanup_work_bit_and_try_run(ctx); + mfc_release_instance_context(ctx); + mfc_release_enc_roi_buffer(ctx); return -EIO; } - if (s5p_mfc_wait_for_done_ctx(ctx, - S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET)) { + if (mfc_wait_for_done_ctx(ctx, + MFC_REG_R2H_CMD_OPEN_INSTANCE_RET)) { mfc_err_ctx("time out during open instance\n"); - s5p_mfc_release_hwlock_ctx(ctx); - s5p_mfc_cleanup_work_bit_and_try_run(ctx); - s5p_mfc_release_instance_context(ctx); - s5p_mfc_release_enc_roi_buffer(ctx); + mfc_release_hwlock_ctx(ctx); + mfc_cleanup_work_bit_and_try_run(ctx); + mfc_release_instance_context(ctx); + mfc_release_enc_roi_buffer(ctx); return -EIO; } - s5p_mfc_release_hwlock_ctx(ctx); + mfc_release_hwlock_ctx(ctx); mfc_debug(2, "Got instance number: %d\n", ctx->inst_no); - if (s5p_mfc_enc_ctx_ready(ctx)) - s5p_mfc_set_bit(ctx->num, &dev->work_bits); - if (ctx->otf_handle && s5p_mfc_otf_ctx_ready(ctx)) - s5p_mfc_set_bit(ctx->num, &dev->work_bits); - if (s5p_mfc_is_work_to_do(dev)) + if (mfc_enc_ctx_ready(ctx)) + mfc_set_bit(ctx->num, &dev->work_bits); + if (ctx->otf_handle && mfc_otf_ctx_ready(ctx)) + mfc_set_bit(ctx->num, &dev->work_bits); + if (mfc_is_work_to_do(dev)) queue_work(dev->butler_wq, &dev->butler_work); mfc_debug_leave(); @@ -491,7 +491,7 @@ static int vidioc_s_fmt_vid_cap_mplane(struct file *file, void *priv, static int vidioc_s_fmt_vid_out_mplane(struct file *file, void *priv, struct v4l2_format *f) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp; mfc_debug_enter(); @@ -506,7 +506,7 @@ static int vidioc_s_fmt_vid_out_mplane(struct file *file, void *priv, return 0; } - ctx->src_fmt = mfc_enc_find_format(ctx, pix_fmt_mp->pixelformat); + ctx->src_fmt = __mfc_enc_find_format(ctx, pix_fmt_mp->pixelformat); if (!ctx->src_fmt) { mfc_err_ctx("Unsupported format for source\n"); return -EINVAL; @@ -523,10 +523,10 @@ static int vidioc_s_fmt_vid_out_mplane(struct file *file, void *priv, ctx->img_height = pix_fmt_mp->height; ctx->buf_stride = pix_fmt_mp->plane_fmt[0].bytesperline; - mfc_enc_check_format(ctx); + __mfc_enc_check_format(ctx); if (ctx->state == MFCINST_RUNNING) { - s5p_mfc_change_state(ctx, MFCINST_GOT_INST); + mfc_change_state(ctx, MFCINST_GOT_INST); mfc_info_ctx("[DRC] Enc resolution is changed\n"); } @@ -540,7 +540,7 @@ static int vidioc_s_fmt_vid_out_mplane(struct file *file, void *priv, */ ctx->crop_width = ctx->img_width; ctx->crop_height = ctx->img_height; - s5p_mfc_enc_calc_src_size(ctx); + mfc_enc_calc_src_size(ctx); ctx->output_state = QUEUE_FREE; @@ -550,7 +550,7 @@ static int vidioc_s_fmt_vid_out_mplane(struct file *file, void *priv, static int vidioc_g_crop(struct file *file, void *fh, struct v4l2_crop *cr) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); mfc_debug_enter(); @@ -569,7 +569,7 @@ static int vidioc_g_crop(struct file *file, void *fh, struct v4l2_crop *cr) static int vidioc_s_crop(struct file *file, void *priv, const struct v4l2_crop *cr) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); mfc_debug_enter(); @@ -609,7 +609,7 @@ static int vidioc_s_crop(struct file *file, void *priv, const struct v4l2_crop * static int vidioc_reqbufs(struct file *file, void *priv, struct v4l2_requestbuffers *reqbufs) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); int ret = 0; mfc_debug_enter(); @@ -677,7 +677,7 @@ static int vidioc_reqbufs(struct file *file, void *priv, static int vidioc_querybuf(struct file *file, void *priv, struct v4l2_buffer *buf) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); int ret = 0; mfc_debug_enter(); @@ -714,7 +714,7 @@ static int vidioc_querybuf(struct file *file, void *priv, /* Queue a buffer */ static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); int i, ret = -EINVAL; mfc_debug_enter(); @@ -760,7 +760,7 @@ static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf) /* Dequeue a buffer */ static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); int ret; mfc_debug_enter(); @@ -789,7 +789,7 @@ static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf) static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type type) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); int ret = -EINVAL; mfc_debug_enter(); @@ -804,7 +804,7 @@ static int vidioc_streamon(struct file *file, void *priv, ret = vb2_streamon(&ctx->vq_src, type); if (!ret) { - s5p_mfc_qos_on(ctx); + mfc_qos_on(ctx); } } else { mfc_debug(4, "enc dst streamon\n"); @@ -812,8 +812,8 @@ static int vidioc_streamon(struct file *file, void *priv, } mfc_debug(2, "src: %d, dst: %d, state = %d, dpb_count = %d\n", - s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_queue), - s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_queue), ctx->state, ctx->dpb_count); mfc_debug_leave(); return ret; @@ -823,7 +823,7 @@ static int vidioc_streamon(struct file *file, void *priv, static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type type) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); int ret; mfc_debug_enter(); @@ -836,11 +836,11 @@ static int vidioc_streamoff(struct file *file, void *priv, ret = -EINVAL; if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { mfc_debug(4, "enc src streamoff\n"); - s5p_mfc_qos_reset_last_framerate(ctx); + mfc_qos_reset_last_framerate(ctx); ret = vb2_streamoff(&ctx->vq_src, type); if (!ret) - s5p_mfc_qos_off(ctx); + mfc_qos_off(ctx); } else { mfc_debug(4, "enc dst streamoff\n"); ret = vb2_streamoff(&ctx->vq_dst, type); @@ -857,7 +857,7 @@ static int vidioc_queryctrl(struct file *file, void *priv, { struct v4l2_queryctrl *c; - c = mfc_enc_get_ctrl(qc->id); + c = __mfc_enc_get_ctrl(qc->id); if (!c) { mfc_err_dev("[CTRLS] not supported control id (%#x)\n", qc->id); return -EINVAL; @@ -867,9 +867,9 @@ static int vidioc_queryctrl(struct file *file, void *priv, return 0; } -static int mfc_enc_ext_info(struct s5p_mfc_ctx *ctx) +static int __mfc_enc_ext_info(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; int val = 0; val |= ENC_SET_SPARE_SIZE; @@ -897,11 +897,11 @@ static int mfc_enc_ext_info(struct s5p_mfc_ctx *ctx) return val; } -static int mfc_enc_get_ctrl_val(struct s5p_mfc_ctx *ctx, struct v4l2_control *ctrl) +static int __mfc_enc_get_ctrl_val(struct mfc_ctx *ctx, struct v4l2_control *ctrl) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_enc *enc = ctx->enc_priv; - struct s5p_mfc_ctx_ctrl *ctx_ctrl; + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_ctx_ctrl *ctx_ctrl; int ret = 0; int found = 0; @@ -960,7 +960,7 @@ static int mfc_enc_get_ctrl_val(struct s5p_mfc_ctx *ctx, struct v4l2_control *ct ctrl->value = ctx->qos_ratio; break; case V4L2_CID_MPEG_MFC_GET_EXT_INFO: - ctrl->value = mfc_enc_ext_info(ctx); + ctrl->value = __mfc_enc_ext_info(ctx); break; case V4L2_CID_MPEG_VIDEO_BPG_HEADER_SIZE: ctrl->value = enc->header_size; @@ -979,17 +979,17 @@ static int mfc_enc_get_ctrl_val(struct s5p_mfc_ctx *ctx, struct v4l2_control *ct static int vidioc_g_ctrl(struct file *file, void *priv, struct v4l2_control *ctrl) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); int ret = 0; mfc_debug_enter(); - ret = mfc_enc_get_ctrl_val(ctx, ctrl); + ret = __mfc_enc_get_ctrl_val(ctx, ctrl); mfc_debug_leave(); return ret; } -static inline int mfc_enc_h264_level(enum v4l2_mpeg_video_h264_level lvl) +static inline int __mfc_enc_h264_level(enum v4l2_mpeg_video_h264_level lvl) { static unsigned int t[V4L2_MPEG_VIDEO_H264_LEVEL_5_1 + 1] = { /* V4L2_MPEG_VIDEO_H264_LEVEL_1_0 */ 10, @@ -1012,7 +1012,7 @@ static inline int mfc_enc_h264_level(enum v4l2_mpeg_video_h264_level lvl) return t[lvl]; } -static inline int mfc_enc_mpeg4_level(enum v4l2_mpeg_video_mpeg4_level lvl) +static inline int __mfc_enc_mpeg4_level(enum v4l2_mpeg_video_mpeg4_level lvl) { static unsigned int t[V4L2_MPEG_VIDEO_MPEG4_LEVEL_6 + 1] = { /* V4L2_MPEG_VIDEO_MPEG4_LEVEL_0 */ 0, @@ -1028,7 +1028,7 @@ static inline int mfc_enc_mpeg4_level(enum v4l2_mpeg_video_mpeg4_level lvl) return t[lvl]; } -static inline int mfc_enc_vui_sar_idc(enum v4l2_mpeg_video_h264_vui_sar_idc sar) +static inline int __mfc_enc_vui_sar_idc(enum v4l2_mpeg_video_h264_vui_sar_idc sar) { static unsigned int t[V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED + 1] = { /* V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_UNSPECIFIED */ 0, @@ -1053,10 +1053,10 @@ static inline int mfc_enc_vui_sar_idc(enum v4l2_mpeg_video_h264_vui_sar_idc sar) return t[sar]; } -static int mfc_enc_set_param(struct s5p_mfc_ctx *ctx, struct v4l2_control *ctrl) +static int __mfc_enc_set_param(struct mfc_ctx *ctx, struct v4l2_control *ctrl) { - struct s5p_mfc_enc *enc = ctx->enc_priv; - struct s5p_mfc_enc_params *p = &enc->params; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; int ret = 0; switch (ctrl->id) { @@ -1119,11 +1119,11 @@ static int mfc_enc_set_param(struct s5p_mfc_ctx *ctx, struct v4l2_control *ctrl) break; case V4L2_CID_MPEG_VIDEO_H264_PROFILE: p->codec.h264.profile = - mfc_enc_h264_profile(ctx, (enum v4l2_mpeg_video_h264_profile)(ctrl->value)); + __mfc_enc_h264_profile(ctx, (enum v4l2_mpeg_video_h264_profile)(ctrl->value)); break; case V4L2_CID_MPEG_VIDEO_H264_LEVEL: p->codec.h264.level = - mfc_enc_h264_level((enum v4l2_mpeg_video_h264_level)(ctrl->value)); + __mfc_enc_h264_level((enum v4l2_mpeg_video_h264_level)(ctrl->value)); break; case V4L2_CID_MPEG_MFC51_VIDEO_H264_INTERLACE: p->codec.h264.interlace = ctrl->value; @@ -1198,7 +1198,7 @@ static int mfc_enc_set_param(struct s5p_mfc_ctx *ctx, struct v4l2_control *ctrl) break; case V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC: p->codec.h264.ar_vui_idc = - mfc_enc_vui_sar_idc((enum v4l2_mpeg_video_h264_vui_sar_idc)(ctrl->value)); + __mfc_enc_vui_sar_idc((enum v4l2_mpeg_video_h264_vui_sar_idc)(ctrl->value)); break; case V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH: p->codec.h264.ext_sar_width = ctrl->value; @@ -1312,11 +1312,11 @@ static int mfc_enc_set_param(struct s5p_mfc_ctx *ctx, struct v4l2_control *ctrl) switch ((enum v4l2_mpeg_video_mpeg4_profile)(ctrl->value)) { case V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE: p->codec.mpeg4.profile = - S5P_FIMV_E_PROFILE_MPEG4_SIMPLE; + MFC_REG_E_PROFILE_MPEG4_SIMPLE; break; case V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_SIMPLE: p->codec.mpeg4.profile = - S5P_FIMV_E_PROFILE_MPEG4_ADVANCED_SIMPLE; + MFC_REG_E_PROFILE_MPEG4_ADVANCED_SIMPLE; break; default: ret = -EINVAL; @@ -1324,7 +1324,7 @@ static int mfc_enc_set_param(struct s5p_mfc_ctx *ctx, struct v4l2_control *ctrl) break; case V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL: p->codec.mpeg4.level = - mfc_enc_mpeg4_level((enum v4l2_mpeg_video_mpeg4_level)(ctrl->value)); + __mfc_enc_mpeg4_level((enum v4l2_mpeg_video_mpeg4_level)(ctrl->value)); break; case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP: p->codec.mpeg4.rc_frame_qp = ctrl->value; @@ -1761,11 +1761,11 @@ static int mfc_enc_set_param(struct s5p_mfc_ctx *ctx, struct v4l2_control *ctrl) return ret; } -static int mfc_enc_set_ctrl_val(struct s5p_mfc_ctx *ctx, struct v4l2_control *ctrl) +static int __mfc_enc_set_ctrl_val(struct mfc_ctx *ctx, struct v4l2_control *ctrl) { - struct s5p_mfc_enc *enc = ctx->enc_priv; - struct s5p_mfc_enc_params *p = &enc->params; - struct s5p_mfc_ctx_ctrl *ctx_ctrl; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + struct mfc_ctx_ctrl *ctx_ctrl; int ret = 0; int found = 0; int index = 0; @@ -1851,7 +1851,7 @@ static int mfc_enc_set_ctrl_val(struct s5p_mfc_ctx *ctx, struct v4l2_control *ct V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_CH)) && (enc->sh_handle_svc.fd == -1)) { enc->sh_handle_svc.fd = ctrl->value; - if (s5p_mfc_mem_get_user_shared_handle(ctx, + if (mfc_mem_get_user_shared_handle(ctx, &enc->sh_handle_svc)) return -EINVAL; else @@ -1869,13 +1869,13 @@ static int mfc_enc_set_ctrl_val(struct s5p_mfc_ctx *ctx, struct v4l2_control *ct } } if (ctx_ctrl->id == V4L2_CID_MPEG_VIDEO_H264_LEVEL) - ctx_ctrl->val = mfc_enc_h264_level((enum v4l2_mpeg_video_h264_level)(ctrl->value)); + ctx_ctrl->val = __mfc_enc_h264_level((enum v4l2_mpeg_video_h264_level)(ctrl->value)); if (ctx_ctrl->id == V4L2_CID_MPEG_VIDEO_H264_PROFILE) - ctx_ctrl->val = mfc_enc_h264_profile(ctx, (enum v4l2_mpeg_video_h264_profile)(ctrl->value)); + ctx_ctrl->val = __mfc_enc_h264_profile(ctx, (enum v4l2_mpeg_video_h264_profile)(ctrl->value)); if (ctx_ctrl->id == V4L2_CID_MPEG_VIDEO_ROI_CONTROL) { if (enc->sh_handle_roi.fd == -1) { enc->sh_handle_roi.fd = ctrl->value; - if (s5p_mfc_mem_get_user_shared_handle(ctx, + if (mfc_mem_get_user_shared_handle(ctx, &enc->sh_handle_roi)) return -EINVAL; else @@ -1904,7 +1904,7 @@ static int mfc_enc_set_ctrl_val(struct s5p_mfc_ctx *ctx, struct v4l2_control *ct } break; default: - ret = mfc_enc_set_param(ctx, ctrl); + ret = __mfc_enc_set_param(ctx, ctrl); break; } @@ -1914,16 +1914,16 @@ static int mfc_enc_set_ctrl_val(struct s5p_mfc_ctx *ctx, struct v4l2_control *ct static int vidioc_s_ctrl(struct file *file, void *priv, struct v4l2_control *ctrl) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); int ret = 0; mfc_debug_enter(); - ret = mfc_enc_check_ctrl_val(ctx, ctrl); + ret = __mfc_enc_check_ctrl_val(ctx, ctrl); if (ret != 0) return ret; - ret = mfc_enc_set_ctrl_val(ctx, ctrl); + ret = __mfc_enc_set_ctrl_val(ctx, ctrl); mfc_debug_leave(); @@ -1933,7 +1933,7 @@ static int vidioc_s_ctrl(struct file *file, void *priv, static int vidioc_g_ext_ctrls(struct file *file, void *priv, struct v4l2_ext_controls *f) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); struct v4l2_ext_control *ext_ctrl; struct v4l2_control ctrl; int i; @@ -1947,7 +1947,7 @@ static int vidioc_g_ext_ctrls(struct file *file, void *priv, ctrl.id = ext_ctrl->id; - ret = mfc_enc_get_ctrl_val(ctx, &ctrl); + ret = __mfc_enc_get_ctrl_val(ctx, &ctrl); if (ret == 0) { ext_ctrl->value = ctrl.value; } else { @@ -1965,7 +1965,7 @@ static int vidioc_g_ext_ctrls(struct file *file, void *priv, static int vidioc_s_ext_ctrls(struct file *file, void *priv, struct v4l2_ext_controls *f) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); struct v4l2_ext_control *ext_ctrl; struct v4l2_control ctrl; int i; @@ -1980,13 +1980,13 @@ static int vidioc_s_ext_ctrls(struct file *file, void *priv, ctrl.id = ext_ctrl->id; ctrl.value = ext_ctrl->value; - ret = mfc_enc_check_ctrl_val(ctx, &ctrl); + ret = __mfc_enc_check_ctrl_val(ctx, &ctrl); if (ret != 0) { f->error_idx = i; break; } - ret = mfc_enc_set_param(ctx, &ctrl); + ret = __mfc_enc_set_param(ctx, &ctrl); if (ret != 0) { f->error_idx = i; break; @@ -2002,7 +2002,7 @@ static int vidioc_s_ext_ctrls(struct file *file, void *priv, static int vidioc_try_ext_ctrls(struct file *file, void *priv, struct v4l2_ext_controls *f) { - struct s5p_mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); + struct mfc_ctx *ctx = fh_to_mfc_ctx(file->private_data); struct v4l2_ext_control *ext_ctrl; struct v4l2_control ctrl; int i; @@ -2017,7 +2017,7 @@ static int vidioc_try_ext_ctrls(struct file *file, void *priv, ctrl.id = ext_ctrl->id; ctrl.value = ext_ctrl->value; - ret = mfc_enc_check_ctrl_val(ctx, &ctrl); + ret = __mfc_enc_check_ctrl_val(ctx, &ctrl); if (ret != 0) { f->error_idx = i; break; @@ -2029,7 +2029,7 @@ static int vidioc_try_ext_ctrls(struct file *file, void *priv, return ret; } -static const struct v4l2_ioctl_ops s5p_mfc_enc_ioctl_ops = { +static const struct v4l2_ioctl_ops mfc_enc_ioctl_ops = { .vidioc_querycap = vidioc_querycap, .vidioc_enum_fmt_vid_cap_mplane = vidioc_enum_fmt_vid_cap_mplane, .vidioc_enum_fmt_vid_out_mplane = vidioc_enum_fmt_vid_out_mplane, @@ -2055,7 +2055,7 @@ static const struct v4l2_ioctl_ops s5p_mfc_enc_ioctl_ops = { .vidioc_try_ext_ctrls = vidioc_try_ext_ctrls, }; -const struct v4l2_ioctl_ops *s5p_mfc_get_enc_v4l2_ioctl_ops(void) +const struct v4l2_ioctl_ops *mfc_get_enc_v4l2_ioctl_ops(void) { - return &s5p_mfc_enc_ioctl_ops; + return &mfc_enc_ioctl_ops; } diff --git a/drivers/media/platform/exynos/mfc/mfc_enc.h b/drivers/media/platform/exynos/mfc/mfc_enc.h index bc0a0ad801fd..f2092faf966c 100644 --- a/drivers/media/platform/exynos/mfc/mfc_enc.h +++ b/drivers/media/platform/exynos/mfc/mfc_enc.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_enc.h + * drivers/media/platform/exynos/mfc/mfc_enc.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -15,6 +15,6 @@ #include "mfc_common.h" -const struct v4l2_ioctl_ops *s5p_mfc_get_enc_v4l2_ioctl_ops(void); +const struct v4l2_ioctl_ops *mfc_get_enc_v4l2_ioctl_ops(void); #endif /* __MFC_ENC_H */ diff --git a/drivers/media/platform/exynos/mfc/mfc_enc_internal.h b/drivers/media/platform/exynos/mfc/mfc_enc_internal.h index 60f35f66b2a1..f3b7eb606989 100644 --- a/drivers/media/platform/exynos/mfc/mfc_enc_internal.h +++ b/drivers/media/platform/exynos/mfc/mfc_enc_internal.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_enc_internal.h + * drivers/media/platform/exynos/mfc/mfc_enc_internal.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -24,7 +24,7 @@ * 2 4 6 8 0 * |B......BG......GR......RA......A| */ -struct s5p_mfc_fmt enc_formats[] = { +struct mfc_fmt enc_formats[] = { { .name = "4:2:0 3 Planes Y/Cb/Cr", .fourcc = V4L2_PIX_FMT_YUV420M, @@ -196,7 +196,7 @@ struct s5p_mfc_fmt enc_formats[] = { { .name = "H264 Encoded Stream", .fourcc = V4L2_PIX_FMT_H264, - .codec_mode = S5P_FIMV_CODEC_H264_ENC, + .codec_mode = MFC_REG_CODEC_H264_ENC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, @@ -204,7 +204,7 @@ struct s5p_mfc_fmt enc_formats[] = { { .name = "MPEG4 Encoded Stream", .fourcc = V4L2_PIX_FMT_MPEG4, - .codec_mode = S5P_FIMV_CODEC_MPEG4_ENC, + .codec_mode = MFC_REG_CODEC_MPEG4_ENC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, @@ -212,7 +212,7 @@ struct s5p_mfc_fmt enc_formats[] = { { .name = "H263 Encoded Stream", .fourcc = V4L2_PIX_FMT_H263, - .codec_mode = S5P_FIMV_CODEC_H263_ENC, + .codec_mode = MFC_REG_CODEC_H263_ENC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, @@ -220,7 +220,7 @@ struct s5p_mfc_fmt enc_formats[] = { { .name = "VP8 Encoded Stream", .fourcc = V4L2_PIX_FMT_VP8, - .codec_mode = S5P_FIMV_CODEC_VP8_ENC, + .codec_mode = MFC_REG_CODEC_VP8_ENC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, @@ -228,7 +228,7 @@ struct s5p_mfc_fmt enc_formats[] = { { .name = "VP9 Encoded Stream", .fourcc = V4L2_PIX_FMT_VP9, - .codec_mode = S5P_FIMV_CODEC_VP9_ENC, + .codec_mode = MFC_REG_CODEC_VP9_ENC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, @@ -236,7 +236,7 @@ struct s5p_mfc_fmt enc_formats[] = { { .name = "HEVC Encoded Stream", .fourcc = V4L2_PIX_FMT_HEVC, - .codec_mode = S5P_FIMV_CODEC_HEVC_ENC, + .codec_mode = MFC_REG_CODEC_HEVC_ENC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, @@ -244,7 +244,7 @@ struct s5p_mfc_fmt enc_formats[] = { { .name = "BPG Encoded Stream", .fourcc = V4L2_PIX_FMT_BPG, - .codec_mode = S5P_FIMV_CODEC_BPG_ENC, + .codec_mode = MFC_REG_CODEC_BPG_ENC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, diff --git a/drivers/media/platform/exynos/mfc/mfc_enc_ops.c b/drivers/media/platform/exynos/mfc/mfc_enc_ops.c index b688e73e4c29..824fe5330651 100644 --- a/drivers/media/platform/exynos/mfc/mfc_enc_ops.c +++ b/drivers/media/platform/exynos/mfc/mfc_enc_ops.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_enc_ops.c + * drivers/media/platform/exynos/mfc/mfc_enc_ops.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -14,11 +14,11 @@ #include "mfc_reg.h" -static int mfc_enc_ctrl_read_cst(struct s5p_mfc_ctx *ctx, - struct s5p_mfc_buf_ctrl *buf_ctrl) +static int __mfc_enc_ctrl_read_cst(struct mfc_ctx *ctx, + struct mfc_buf_ctrl *buf_ctrl) { int ret; - struct s5p_mfc_enc *enc = ctx->enc_priv; + struct mfc_enc *enc = ctx->enc_priv; switch (buf_ctrl->id) { case V4L2_CID_MPEG_MFC51_VIDEO_FRAME_STATUS: @@ -33,13 +33,13 @@ static int mfc_enc_ctrl_read_cst(struct s5p_mfc_ctx *ctx, return ret; } -static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { +static struct mfc_ctrl_cfg mfc_ctrl_list[] = { { /* set frame tag */ .type = MFC_CTRL_TYPE_SET, .id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_PICTURE_TAG, + .addr = MFC_REG_E_PICTURE_TAG, .mask = 0xFFFFFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -51,7 +51,7 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RET_PICTURE_TAG, + .addr = MFC_REG_E_RET_PICTURE_TAG, .mask = 0xFFFFFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -63,7 +63,7 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_MFC51_VIDEO_LUMA_ADDR, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_ENCODED_SOURCE_FIRST_ADDR, + .addr = MFC_REG_E_ENCODED_SOURCE_FIRST_ADDR, .mask = 0xFFFFFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -75,7 +75,7 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_MFC51_VIDEO_CHROMA_ADDR, .is_volatile = 0, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_ENCODED_SOURCE_SECOND_ADDR, + .addr = MFC_REG_E_ENCODED_SOURCE_SECOND_ADDR, .mask = 0xFFFFFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -87,7 +87,7 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_FRAME_INSERTION, + .addr = MFC_REG_E_FRAME_INSERTION, .mask = 0x3, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -99,11 +99,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_MFC51_VIDEO_I_PERIOD_CH, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_GOP_CONFIG, + .addr = MFC_REG_E_GOP_CONFIG, .mask = 0xFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 0, }, { /* frame rate change */ @@ -111,11 +111,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_MFC51_VIDEO_FRAME_RATE_CH, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_FRAME_RATE, + .addr = MFC_REG_E_RC_FRAME_RATE, .mask = 0xFFFFFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 1, }, { /* bit rate change */ @@ -123,11 +123,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_MFC51_VIDEO_BIT_RATE_CH, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_BIT_RATE, + .addr = MFC_REG_E_RC_BIT_RATE, .mask = 0xFFFFFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 2, }, { /* frame status (in slice or not) */ @@ -141,7 +141,7 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .flag_mode = MFC_CTRL_MODE_NONE, .flag_addr = 0, .flag_shft = 0, - .read_cst = mfc_enc_ctrl_read_cst, + .read_cst = __mfc_enc_ctrl_read_cst, .write_cst = NULL, }, { /* H.264 I frame QP Max change */ @@ -149,11 +149,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_H264_MAX_QP, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND, + .addr = MFC_REG_E_RC_QP_BOUND, .mask = 0xFF, .shft = 8, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* H.264 I frame QP Min change */ @@ -161,11 +161,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_H264_MIN_QP, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND, + .addr = MFC_REG_E_RC_QP_BOUND, .mask = 0xFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* H.263 I frame QP Max change */ @@ -173,11 +173,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_H263_MAX_QP, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND, + .addr = MFC_REG_E_RC_QP_BOUND, .mask = 0xFF, .shft = 8, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* H.263 I frame QP Min change */ @@ -185,11 +185,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_H263_MIN_QP, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND, + .addr = MFC_REG_E_RC_QP_BOUND, .mask = 0xFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* MPEG4 I frame QP Max change */ @@ -197,11 +197,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND, + .addr = MFC_REG_E_RC_QP_BOUND, .mask = 0xFF, .shft = 8, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* MPEG4 I frame QP Min change */ @@ -209,11 +209,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND, + .addr = MFC_REG_E_RC_QP_BOUND, .mask = 0xFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* VP8 I frame QP Max change */ @@ -221,11 +221,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_VP8_MAX_QP, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND, + .addr = MFC_REG_E_RC_QP_BOUND, .mask = 0xFF, .shft = 8, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* VP8 I frame QP Min change */ @@ -233,11 +233,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_VP8_MIN_QP, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND, + .addr = MFC_REG_E_RC_QP_BOUND, .mask = 0xFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* VP9 I frame QP Max change */ @@ -245,11 +245,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_VP9_MAX_QP, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND, + .addr = MFC_REG_E_RC_QP_BOUND, .mask = 0xFF, .shft = 8, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* VP9 I frame QP Min change */ @@ -257,11 +257,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_VP9_MIN_QP, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND, + .addr = MFC_REG_E_RC_QP_BOUND, .mask = 0xFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* HEVC I frame QP Max change */ @@ -269,11 +269,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND, + .addr = MFC_REG_E_RC_QP_BOUND, .mask = 0xFF, .shft = 8, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* HEVC I frame QP Min change */ @@ -281,11 +281,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND, + .addr = MFC_REG_E_RC_QP_BOUND, .mask = 0xFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* H.264 P frame QP Max change */ @@ -293,11 +293,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_H264_MAX_QP_P, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND_PB, + .addr = MFC_REG_E_RC_QP_BOUND_PB, .mask = 0xFF, .shft = 8, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* H.264 P frame QP Min change */ @@ -305,11 +305,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_H264_MIN_QP_P, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND_PB, + .addr = MFC_REG_E_RC_QP_BOUND_PB, .mask = 0xFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* H.263 P frame QP Max change */ @@ -317,11 +317,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_H263_MAX_QP_P, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND_PB, + .addr = MFC_REG_E_RC_QP_BOUND_PB, .mask = 0xFF, .shft = 8, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* H.263 P frame QP Min change */ @@ -329,11 +329,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_H263_MIN_QP_P, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND_PB, + .addr = MFC_REG_E_RC_QP_BOUND_PB, .mask = 0xFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* MPEG4 P frame QP Max change */ @@ -341,11 +341,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP_P, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND_PB, + .addr = MFC_REG_E_RC_QP_BOUND_PB, .mask = 0xFF, .shft = 8, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* MPEG4 P frame QP Min change */ @@ -353,11 +353,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP_P, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND_PB, + .addr = MFC_REG_E_RC_QP_BOUND_PB, .mask = 0xFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* VP8 P frame QP Max change */ @@ -365,11 +365,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_VP8_MAX_QP_P, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND_PB, + .addr = MFC_REG_E_RC_QP_BOUND_PB, .mask = 0xFF, .shft = 8, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* VP8 P frame QP Min change */ @@ -377,11 +377,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_VP8_MIN_QP_P, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND_PB, + .addr = MFC_REG_E_RC_QP_BOUND_PB, .mask = 0xFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* VP9 P frame QP Max change */ @@ -389,11 +389,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_VP9_MAX_QP_P, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND_PB, + .addr = MFC_REG_E_RC_QP_BOUND_PB, .mask = 0xFF, .shft = 8, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* VP9 P frame QP Min change */ @@ -401,11 +401,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_VP9_MIN_QP_P, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND_PB, + .addr = MFC_REG_E_RC_QP_BOUND_PB, .mask = 0xFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* HEVC P frame QP Max change */ @@ -413,11 +413,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP_P, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND_PB, + .addr = MFC_REG_E_RC_QP_BOUND_PB, .mask = 0xFF, .shft = 8, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* HEVC P frame QP Min change */ @@ -425,11 +425,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP_P, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND_PB, + .addr = MFC_REG_E_RC_QP_BOUND_PB, .mask = 0xFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* H.264 B frame QP Max change */ @@ -437,11 +437,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_H264_MAX_QP_B, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND_PB, + .addr = MFC_REG_E_RC_QP_BOUND_PB, .mask = 0xFF, .shft = 24, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* H.264 B frame QP Min change */ @@ -449,11 +449,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_H264_MIN_QP_B, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND_PB, + .addr = MFC_REG_E_RC_QP_BOUND_PB, .mask = 0xFF, .shft = 16, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* MPEG4 B frame QP Max change */ @@ -461,11 +461,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP_B, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND_PB, + .addr = MFC_REG_E_RC_QP_BOUND_PB, .mask = 0xFF, .shft = 24, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* MPEG4 B frame QP Min change */ @@ -473,11 +473,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP_B, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND_PB, + .addr = MFC_REG_E_RC_QP_BOUND_PB, .mask = 0xFF, .shft = 16, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* HEVC B frame QP Max change */ @@ -485,11 +485,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP_B, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND_PB, + .addr = MFC_REG_E_RC_QP_BOUND_PB, .mask = 0xFF, .shft = 24, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* HEVC B frame QP Min change */ @@ -497,11 +497,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP_B, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_QP_BOUND_PB, + .addr = MFC_REG_E_RC_QP_BOUND_PB, .mask = 0xFF, .shft = 16, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 4, }, { /* H.264 Dynamic Temporal Layer & bitrate change */ @@ -509,11 +509,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_CH, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0, + .addr = MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER0, .mask = 0xFFFFFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 10, }, { /* HEVC Dynamic Temporal Layer & bitrate change */ @@ -521,11 +521,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_CH, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0, + .addr = MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER0, .mask = 0xFFFFFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 10, }, { /* VP8 Dynamic Temporal Layer change */ @@ -533,11 +533,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_VP8_HIERARCHICAL_CODING_LAYER_CH, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0, + .addr = MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER0, .mask = 0xFFFFFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 10, }, { /* VP9 Dynamic Temporal Layer change */ @@ -545,11 +545,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_VP9_HIERARCHICAL_CODING_LAYER_CH, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0, + .addr = MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER0, .mask = 0xFFFFFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 10, }, { /* set level */ @@ -557,11 +557,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_H264_LEVEL, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_PICTURE_PROFILE, + .addr = MFC_REG_E_PICTURE_PROFILE, .mask = 0x000000FF, .shft = 8, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 5, }, { /* set profile */ @@ -569,11 +569,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_H264_PROFILE, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_PICTURE_PROFILE, + .addr = MFC_REG_E_PICTURE_PROFILE, .mask = 0x0000000F, .shft = 0, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 5, }, { /* set store LTR */ @@ -581,7 +581,7 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_MFC_H264_MARK_LTR, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_H264_NAL_CONTROL, + .addr = MFC_REG_E_H264_NAL_CONTROL, .mask = 0x00000003, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -593,7 +593,7 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_MFC_H264_USE_LTR, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_H264_NAL_CONTROL, + .addr = MFC_REG_E_H264_NAL_CONTROL, .mask = 0x00000003, .shft = 2, .flag_mode = MFC_CTRL_MODE_NONE, @@ -605,11 +605,11 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_MFC_H264_BASE_PRIORITY, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_H264_HD_SVC_EXTENSION_0, + .addr = MFC_REG_E_H264_HD_SVC_EXTENSION_0, .mask = 0x0000003F, .shft = 0, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 12, }, { /* set QP per each frame */ @@ -617,7 +617,7 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_MFC_CONFIG_QP, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_FIXED_PICTURE_QP, + .addr = MFC_REG_E_FIXED_PICTURE_QP, .mask = 0x000000FF, .shft = 24, .flag_mode = MFC_CTRL_MODE_NONE, @@ -629,7 +629,7 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_ROI_CONTROL, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_ROI_CTRL, + .addr = MFC_REG_E_RC_ROI_CTRL, .mask = 0xFFFFFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -641,7 +641,7 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_YSUM, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_WEIGHT_FOR_WEIGHTED_PREDICTION, + .addr = MFC_REG_E_WEIGHT_FOR_WEIGHTED_PREDICTION, .mask = 0xFFFFFFFF, .shft = 0, .flag_mode = MFC_CTRL_MODE_NONE, @@ -653,24 +653,24 @@ static struct s5p_mfc_ctrl_cfg mfc_ctrl_list[] = { .id = V4L2_CID_MPEG_VIDEO_RATIO_OF_INTRA, .is_volatile = 1, .mode = MFC_CTRL_MODE_SFR, - .addr = S5P_FIMV_E_RC_MODE, + .addr = MFC_REG_E_RC_MODE, .mask = 0x000000FF, .shft = 8, .flag_mode = MFC_CTRL_MODE_SFR, - .flag_addr = S5P_FIMV_E_PARAM_CHANGE, + .flag_addr = MFC_REG_E_PARAM_CHANGE, .flag_shft = 13, } }; #define NUM_CTRL_CFGS ARRAY_SIZE(mfc_ctrl_list) -static int s5p_mfc_enc_cleanup_ctx_ctrls(struct s5p_mfc_ctx *ctx) +static int mfc_enc_cleanup_ctx_ctrls(struct mfc_ctx *ctx) { - struct s5p_mfc_ctx_ctrl *ctx_ctrl; + struct mfc_ctx_ctrl *ctx_ctrl; while (!list_empty(&ctx->ctrls)) { ctx_ctrl = list_entry((&ctx->ctrls)->next, - struct s5p_mfc_ctx_ctrl, list); + struct mfc_ctx_ctrl, list); list_del(&ctx_ctrl->list); kfree(ctx_ctrl); } @@ -680,10 +680,10 @@ static int s5p_mfc_enc_cleanup_ctx_ctrls(struct s5p_mfc_ctx *ctx) return 0; } -static int s5p_mfc_enc_get_buf_update_val(struct s5p_mfc_ctx *ctx, +static int mfc_enc_get_buf_update_val(struct mfc_ctx *ctx, struct list_head *head, unsigned int id, int value) { - struct s5p_mfc_buf_ctrl *buf_ctrl; + struct mfc_buf_ctrl *buf_ctrl; list_for_each_entry(buf_ctrl, head, list) { if (buf_ctrl->id == id) { @@ -697,22 +697,22 @@ static int s5p_mfc_enc_get_buf_update_val(struct s5p_mfc_ctx *ctx, return 0; } -static int s5p_mfc_enc_init_ctx_ctrls(struct s5p_mfc_ctx *ctx) +static int mfc_enc_init_ctx_ctrls(struct mfc_ctx *ctx) { unsigned long i; - struct s5p_mfc_ctx_ctrl *ctx_ctrl; + struct mfc_ctx_ctrl *ctx_ctrl; INIT_LIST_HEAD(&ctx->ctrls); for (i = 0; i < NUM_CTRL_CFGS; i++) { - ctx_ctrl = kzalloc(sizeof(struct s5p_mfc_ctx_ctrl), GFP_KERNEL); + ctx_ctrl = kzalloc(sizeof(struct mfc_ctx_ctrl), GFP_KERNEL); if (ctx_ctrl == NULL) { mfc_err_dev("Failed to allocate context control "\ "id: 0x%08x, type: %d\n", mfc_ctrl_list[i].id, mfc_ctrl_list[i].type); - s5p_mfc_enc_cleanup_ctx_ctrls(ctx); + mfc_enc_cleanup_ctx_ctrls(ctx); return -ENOMEM; } @@ -728,9 +728,9 @@ static int s5p_mfc_enc_init_ctx_ctrls(struct s5p_mfc_ctx *ctx) return 0; } -static void s5p_mfc_enc_reset_buf_ctrls(struct list_head *head) +static void mfc_enc_reset_buf_ctrls(struct list_head *head) { - struct s5p_mfc_buf_ctrl *buf_ctrl; + struct mfc_buf_ctrl *buf_ctrl; list_for_each_entry(buf_ctrl, head, list) { buf_ctrl->has_new = 0; @@ -740,13 +740,13 @@ static void s5p_mfc_enc_reset_buf_ctrls(struct list_head *head) } } -static void mfc_enc_remove_buf_ctrls(struct list_head *head) +static void __mfc_enc_remove_buf_ctrls(struct list_head *head) { - struct s5p_mfc_buf_ctrl *buf_ctrl; + struct mfc_buf_ctrl *buf_ctrl; while (!list_empty(head)) { buf_ctrl = list_entry(head->next, - struct s5p_mfc_buf_ctrl, list); + struct mfc_buf_ctrl, list); list_del(&buf_ctrl->list); kfree(buf_ctrl); } @@ -754,11 +754,11 @@ static void mfc_enc_remove_buf_ctrls(struct list_head *head) INIT_LIST_HEAD(head); } -static int s5p_mfc_enc_init_buf_ctrls(struct s5p_mfc_ctx *ctx, - enum s5p_mfc_ctrl_type type, unsigned int index) +static int mfc_enc_init_buf_ctrls(struct mfc_ctx *ctx, + enum mfc_ctrl_type type, unsigned int index) { unsigned long i; - struct s5p_mfc_buf_ctrl *buf_ctrl; + struct mfc_buf_ctrl *buf_ctrl; struct list_head *head; if (index >= MFC_MAX_BUFFERS) { @@ -768,7 +768,7 @@ static int s5p_mfc_enc_init_buf_ctrls(struct s5p_mfc_ctx *ctx, if (type & MFC_CTRL_TYPE_SRC) { if (test_bit(index, &ctx->src_ctrls_avail)) { - s5p_mfc_enc_reset_buf_ctrls(&ctx->src_ctrls[index]); + mfc_enc_reset_buf_ctrls(&ctx->src_ctrls[index]); return 0; } @@ -776,7 +776,7 @@ static int s5p_mfc_enc_init_buf_ctrls(struct s5p_mfc_ctx *ctx, head = &ctx->src_ctrls[index]; } else if (type & MFC_CTRL_TYPE_DST) { if (test_bit(index, &ctx->dst_ctrls_avail)) { - s5p_mfc_enc_reset_buf_ctrls(&ctx->dst_ctrls[index]); + mfc_enc_reset_buf_ctrls(&ctx->dst_ctrls[index]); return 0; } @@ -793,14 +793,14 @@ static int s5p_mfc_enc_init_buf_ctrls(struct s5p_mfc_ctx *ctx, if (!(type & mfc_ctrl_list[i].type)) continue; - buf_ctrl = kzalloc(sizeof(struct s5p_mfc_buf_ctrl), GFP_KERNEL); + buf_ctrl = kzalloc(sizeof(struct mfc_buf_ctrl), GFP_KERNEL); if (buf_ctrl == NULL) { mfc_err_dev("Failed to allocate buffer control "\ "id: 0x%08x, type: %d\n", mfc_ctrl_list[i].id, mfc_ctrl_list[i].type); - mfc_enc_remove_buf_ctrls(head); + __mfc_enc_remove_buf_ctrls(head); return -ENOMEM; } @@ -823,7 +823,7 @@ static int s5p_mfc_enc_init_buf_ctrls(struct s5p_mfc_ctx *ctx, list_add_tail(&buf_ctrl->list, head); } - s5p_mfc_enc_reset_buf_ctrls(head); + mfc_enc_reset_buf_ctrls(head); if (type & MFC_CTRL_TYPE_SRC) set_bit(index, &ctx->src_ctrls_avail); @@ -833,8 +833,8 @@ static int s5p_mfc_enc_init_buf_ctrls(struct s5p_mfc_ctx *ctx, return 0; } -static int s5p_mfc_enc_cleanup_buf_ctrls(struct s5p_mfc_ctx *ctx, - enum s5p_mfc_ctrl_type type, unsigned int index) +static int mfc_enc_cleanup_buf_ctrls(struct mfc_ctx *ctx, + enum mfc_ctrl_type type, unsigned int index) { struct list_head *head; @@ -860,16 +860,16 @@ static int s5p_mfc_enc_cleanup_buf_ctrls(struct s5p_mfc_ctx *ctx, return -EINVAL; } - mfc_enc_remove_buf_ctrls(head); + __mfc_enc_remove_buf_ctrls(head); return 0; } -static int s5p_mfc_enc_to_buf_ctrls(struct s5p_mfc_ctx *ctx, struct list_head *head) +static int mfc_enc_to_buf_ctrls(struct mfc_ctx *ctx, struct list_head *head) { - struct s5p_mfc_ctx_ctrl *ctx_ctrl; - struct s5p_mfc_buf_ctrl *buf_ctrl; - struct s5p_mfc_enc *enc = ctx->enc_priv; + struct mfc_ctx_ctrl *ctx_ctrl; + struct mfc_buf_ctrl *buf_ctrl; + struct mfc_enc *enc = ctx->enc_priv; int index = 0; unsigned int reg = 0; @@ -918,10 +918,10 @@ static int s5p_mfc_enc_to_buf_ctrls(struct s5p_mfc_ctx *ctx, struct list_head *h return 0; } -static int s5p_mfc_enc_to_ctx_ctrls(struct s5p_mfc_ctx *ctx, struct list_head *head) +static int mfc_enc_to_ctx_ctrls(struct mfc_ctx *ctx, struct list_head *head) { - struct s5p_mfc_ctx_ctrl *ctx_ctrl; - struct s5p_mfc_buf_ctrl *buf_ctrl; + struct mfc_ctx_ctrl *ctx_ctrl; + struct mfc_buf_ctrl *buf_ctrl; list_for_each_entry(buf_ctrl, head, list) { if (!(buf_ctrl->type & MFC_CTRL_TYPE_GET) || !buf_ctrl->has_new) @@ -949,15 +949,15 @@ static int s5p_mfc_enc_to_ctx_ctrls(struct s5p_mfc_ctx *ctx, struct list_head *h return 0; } -static void mfc_enc_set_buf_ctrls_temporal_svc(struct s5p_mfc_ctx *ctx, - struct s5p_mfc_buf_ctrl *buf_ctrl) +static void __mfc_enc_set_buf_ctrls_temporal_svc(struct mfc_ctx *ctx, + struct mfc_buf_ctrl *buf_ctrl) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_enc *enc = ctx->enc_priv; + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; unsigned int value = 0, value2 = 0; struct temporal_layer_info temporal_LC; unsigned int i; - struct s5p_mfc_enc_params *p = &enc->params; + struct mfc_enc_params *p = &enc->params; if (buf_ctrl->id == V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_CH || @@ -998,13 +998,13 @@ static void mfc_enc_set_buf_ctrls_temporal_svc(struct s5p_mfc_ctx *ctx, mfc_debug(3, "[HIERARCHICAL] layer count %d, E_PARAM_CHANGE %#x\n", temporal_LC.temporal_layer_count & 0x7, value); - value = MFC_READL(S5P_FIMV_E_NUM_T_LAYER); + value = MFC_READL(MFC_REG_E_NUM_T_LAYER); buf_ctrl->old_val2 = value; value &= ~(0x7); value |= (temporal_LC.temporal_layer_count & 0x7); value &= ~(0x1 << 8); value |= (p->hier_bitrate_ctrl & 0x1) << 8; - MFC_WRITEL(value, S5P_FIMV_E_NUM_T_LAYER); + MFC_WRITEL(value, MFC_REG_E_NUM_T_LAYER); mfc_debug(3, "[HIERARCHICAL] E_NUM_T_LAYER %#x\n", value); for (i = 0; i < (temporal_LC.temporal_layer_count & 0x7); i++) { mfc_debug(3, "[HIERARCHICAL] layer bitrate[%d] %d (FW ctrl: %d)\n", @@ -1024,8 +1024,8 @@ static void mfc_enc_set_buf_ctrls_temporal_svc(struct s5p_mfc_ctx *ctx, value2 |= ((p->codec.h264.base_priority & 0x3F) + i) << (6 * (i - 5)); } - MFC_WRITEL(value, S5P_FIMV_E_H264_HD_SVC_EXTENSION_0); - MFC_WRITEL(value2, S5P_FIMV_E_H264_HD_SVC_EXTENSION_1); + MFC_WRITEL(value, MFC_REG_E_H264_HD_SVC_EXTENSION_0); + MFC_WRITEL(value2, MFC_REG_E_H264_HD_SVC_EXTENSION_1); mfc_debug(3, "[HIERARCHICAL] EXTENSION0 %#x, EXTENSION1 %#x\n", value, value2); @@ -1039,10 +1039,10 @@ static void mfc_enc_set_buf_ctrls_temporal_svc(struct s5p_mfc_ctx *ctx, /* temproral layer priority */ if (buf_ctrl->id == V4L2_CID_MPEG_MFC_H264_BASE_PRIORITY) { - value = MFC_READL(S5P_FIMV_E_H264_HD_SVC_EXTENSION_0); + value = MFC_READL(MFC_REG_E_H264_HD_SVC_EXTENSION_0); buf_ctrl->old_val |= value & 0x3FFFFFC0; value &= ~(0x3FFFFFC0); - value2 = MFC_READL(S5P_FIMV_E_H264_HD_SVC_EXTENSION_1); + value2 = MFC_READL(MFC_REG_E_H264_HD_SVC_EXTENSION_1); buf_ctrl->old_val2 = value2 & 0x0FFF; value2 &= ~(0x0FFF); for (i = 0; i < (p->codec.h264.num_hier_layer & 0x07); i++) { @@ -1051,67 +1051,67 @@ static void mfc_enc_set_buf_ctrls_temporal_svc(struct s5p_mfc_ctx *ctx, else value2 |= ((buf_ctrl->val & 0x3F) + i) << (6 * (i - 5)); } - MFC_WRITEL(value, S5P_FIMV_E_H264_HD_SVC_EXTENSION_0); - MFC_WRITEL(value2, S5P_FIMV_E_H264_HD_SVC_EXTENSION_1); + MFC_WRITEL(value, MFC_REG_E_H264_HD_SVC_EXTENSION_0); + MFC_WRITEL(value2, MFC_REG_E_H264_HD_SVC_EXTENSION_1); p->codec.h264.base_priority = buf_ctrl->val; mfc_debug(3, "[HIERARCHICAL] EXTENSION0 %#x, EXTENSION1 %#x\n", value, value2); } } -static void mfc_enc_set_buf_ctrls_exception(struct s5p_mfc_ctx *ctx, - struct s5p_mfc_buf_ctrl *buf_ctrl) +static void __mfc_enc_set_buf_ctrls_exception(struct mfc_ctx *ctx, + struct mfc_buf_ctrl *buf_ctrl) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_enc *enc = ctx->enc_priv; - struct s5p_mfc_enc_params *p = &enc->params; + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; unsigned int value = 0; if (buf_ctrl->id == V4L2_CID_MPEG_MFC51_VIDEO_FRAME_TAG) enc->stored_tag = buf_ctrl->val; /* temporal layer setting */ - mfc_enc_set_buf_ctrls_temporal_svc(ctx, buf_ctrl); + __mfc_enc_set_buf_ctrls_temporal_svc(ctx, buf_ctrl); if (buf_ctrl->id == V4L2_CID_MPEG_MFC_H264_MARK_LTR) { - value = MFC_READL(S5P_FIMV_E_H264_NAL_CONTROL); + value = MFC_READL(MFC_REG_E_H264_NAL_CONTROL); buf_ctrl->old_val2 = (value >> 8) & 0x7; value &= ~(0x7 << 8); value |= (buf_ctrl->val & 0x7) << 8; - MFC_WRITEL(value, S5P_FIMV_E_H264_NAL_CONTROL); + MFC_WRITEL(value, MFC_REG_E_H264_NAL_CONTROL); } if (buf_ctrl->id == V4L2_CID_MPEG_MFC_H264_USE_LTR) { - value = MFC_READL(S5P_FIMV_E_H264_NAL_CONTROL); + value = MFC_READL(MFC_REG_E_H264_NAL_CONTROL); buf_ctrl->old_val2 = (value >> 11) & 0xF; value &= ~(0xF << 11); value |= (buf_ctrl->val & 0xF) << 11; - MFC_WRITEL(value, S5P_FIMV_E_H264_NAL_CONTROL); + MFC_WRITEL(value, MFC_REG_E_H264_NAL_CONTROL); } if (buf_ctrl->id == V4L2_CID_MPEG_MFC51_VIDEO_I_PERIOD_CH) { - value = MFC_READL(S5P_FIMV_E_GOP_CONFIG2); + value = MFC_READL(MFC_REG_E_GOP_CONFIG2); buf_ctrl->old_val |= (value << 16) & 0x3FFF0000; value &= ~(0x3FFF); value |= (buf_ctrl->val >> 16) & 0x3FFF; - MFC_WRITEL(value, S5P_FIMV_E_GOP_CONFIG2); + MFC_WRITEL(value, MFC_REG_E_GOP_CONFIG2); } /* PROFILE & LEVEL have to be set up together */ if (buf_ctrl->id == V4L2_CID_MPEG_VIDEO_H264_LEVEL) { - value = MFC_READL(S5P_FIMV_E_PICTURE_PROFILE); + value = MFC_READL(MFC_REG_E_PICTURE_PROFILE); buf_ctrl->old_val |= (value & 0x000F) << 8; value &= ~(0x000F); value |= p->codec.h264.profile & 0x000F; - MFC_WRITEL(value, S5P_FIMV_E_PICTURE_PROFILE); + MFC_WRITEL(value, MFC_REG_E_PICTURE_PROFILE); p->codec.h264.level = buf_ctrl->val; } if (buf_ctrl->id == V4L2_CID_MPEG_VIDEO_H264_PROFILE) { - value = MFC_READL(S5P_FIMV_E_PICTURE_PROFILE); + value = MFC_READL(MFC_REG_E_PICTURE_PROFILE); buf_ctrl->old_val |= value & 0xFF00; value &= ~(0x00FF << 8); value |= (p->codec.h264.level << 8) & 0xFF00; - MFC_WRITEL(value, S5P_FIMV_E_PICTURE_PROFILE); + MFC_WRITEL(value, MFC_REG_E_PICTURE_PROFILE); p->codec.h264.profile = buf_ctrl->val; } @@ -1122,7 +1122,7 @@ static void mfc_enc_set_buf_ctrls_exception(struct s5p_mfc_ctx *ctx, /* set the ROI buffer DVA */ if (buf_ctrl->id == V4L2_CID_MPEG_VIDEO_ROI_CONTROL) { MFC_WRITEL(enc->roi_buf[buf_ctrl->old_val2].daddr, - S5P_FIMV_E_ROI_BUFFER_ADDR); + MFC_REG_E_ROI_BUFFER_ADDR); mfc_debug(3, "[ROI] buffer[%d] addr %#llx, QP val: %#x\n", buf_ctrl->old_val2, enc->roi_buf[buf_ctrl->old_val2].daddr, @@ -1130,13 +1130,13 @@ static void mfc_enc_set_buf_ctrls_exception(struct s5p_mfc_ctx *ctx, } } -static int s5p_mfc_enc_set_buf_ctrls_val(struct s5p_mfc_ctx *ctx, struct list_head *head) +static int mfc_enc_set_buf_ctrls_val(struct mfc_ctx *ctx, struct list_head *head) { - struct s5p_mfc_buf_ctrl *buf_ctrl; - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_enc *enc = ctx->enc_priv; + struct mfc_buf_ctrl *buf_ctrl; + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; unsigned int value = 0; - struct s5p_mfc_enc_params *p = &enc->params; + struct mfc_enc_params *p = &enc->params; list_for_each_entry(buf_ctrl, head, list) { if (!(buf_ctrl->type & MFC_CTRL_TYPE_SET) || !buf_ctrl->has_new) @@ -1164,28 +1164,28 @@ static int s5p_mfc_enc_set_buf_ctrls_val(struct s5p_mfc_ctx *ctx, struct list_he buf_ctrl->has_new = 0; buf_ctrl->updated = 1; - mfc_enc_set_buf_ctrls_exception(ctx, buf_ctrl); + __mfc_enc_set_buf_ctrls_exception(ctx, buf_ctrl); mfc_debug(6, "[CTRLS] Set buffer control id: 0x%08x, val: %d\n", buf_ctrl->id, buf_ctrl->val); } if (!p->rc_frame && !p->rc_mb && p->dynamic_qp) { - value = MFC_READL(S5P_FIMV_E_FIXED_PICTURE_QP); + value = MFC_READL(MFC_REG_E_FIXED_PICTURE_QP); value &= ~(0xFF000000); value |= (p->config_qp & 0xFF) << 24; - MFC_WRITEL(value, S5P_FIMV_E_FIXED_PICTURE_QP); + MFC_WRITEL(value, MFC_REG_E_FIXED_PICTURE_QP); mfc_debug(6, "[CTRLS] Dynamic QP changed %#x\n", - MFC_READL(S5P_FIMV_E_FIXED_PICTURE_QP)); + MFC_READL(MFC_REG_E_FIXED_PICTURE_QP)); } return 0; } -static int s5p_mfc_enc_get_buf_ctrls_val(struct s5p_mfc_ctx *ctx, struct list_head *head) +static int mfc_enc_get_buf_ctrls_val(struct mfc_ctx *ctx, struct list_head *head) { - struct s5p_mfc_buf_ctrl *buf_ctrl; - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_buf_ctrl *buf_ctrl; + struct mfc_dev *dev = ctx->dev; unsigned int value = 0; list_for_each_entry(buf_ctrl, head, list) { @@ -1209,14 +1209,14 @@ static int s5p_mfc_enc_get_buf_ctrls_val(struct s5p_mfc_ctx *ctx, struct list_he return 0; } -static int s5p_mfc_enc_set_buf_ctrls_val_nal_q_enc(struct s5p_mfc_ctx *ctx, +static int mfc_enc_set_buf_ctrls_val_nal_q_enc(struct mfc_ctx *ctx, struct list_head *head, EncoderInputStr *pInStr) { - struct s5p_mfc_buf_ctrl *buf_ctrl; - struct s5p_mfc_enc *enc = ctx->enc_priv; + struct mfc_buf_ctrl *buf_ctrl; + struct mfc_enc *enc = ctx->enc_priv; struct temporal_layer_info temporal_LC; unsigned int i, param_change; - struct s5p_mfc_enc_params *p = &enc->params; + struct mfc_enc_params *p = &enc->params; mfc_debug_enter(); @@ -1455,11 +1455,11 @@ static int s5p_mfc_enc_set_buf_ctrls_val_nal_q_enc(struct s5p_mfc_ctx *ctx, return 0; } -static int s5p_mfc_enc_get_buf_ctrls_val_nal_q_enc(struct s5p_mfc_ctx *ctx, +static int mfc_enc_get_buf_ctrls_val_nal_q_enc(struct mfc_ctx *ctx, struct list_head *head, EncoderOutputStr *pOutStr) { - struct s5p_mfc_buf_ctrl *buf_ctrl; - struct s5p_mfc_enc *enc = ctx->enc_priv; + struct mfc_buf_ctrl *buf_ctrl; + struct mfc_enc *enc = ctx->enc_priv; unsigned int value = 0; mfc_debug_enter(); @@ -1499,11 +1499,11 @@ static int s5p_mfc_enc_get_buf_ctrls_val_nal_q_enc(struct s5p_mfc_ctx *ctx, return 0; } -static int s5p_mfc_enc_recover_buf_ctrls_val(struct s5p_mfc_ctx *ctx, +static int mfc_enc_recover_buf_ctrls_val(struct mfc_ctx *ctx, struct list_head *head) { - struct s5p_mfc_buf_ctrl *buf_ctrl; - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_buf_ctrl *buf_ctrl; + struct mfc_dev *dev = ctx->dev; unsigned int value = 0; list_for_each_entry(buf_ctrl, head, list) { @@ -1533,26 +1533,26 @@ static int s5p_mfc_enc_recover_buf_ctrls_val(struct s5p_mfc_ctx *ctx, buf_ctrl->id, buf_ctrl->old_val); if (buf_ctrl->id == V4L2_CID_MPEG_MFC51_VIDEO_I_PERIOD_CH) { - value = MFC_READL(S5P_FIMV_E_GOP_CONFIG2); + value = MFC_READL(MFC_REG_E_GOP_CONFIG2); value &= ~(0x3FFF); value |= (buf_ctrl->old_val >> 16) & 0x3FFF; - MFC_WRITEL(value, S5P_FIMV_E_GOP_CONFIG2); + MFC_WRITEL(value, MFC_REG_E_GOP_CONFIG2); } if (buf_ctrl->id == V4L2_CID_MPEG_VIDEO_H264_LEVEL) { - value = MFC_READL(S5P_FIMV_E_PICTURE_PROFILE); + value = MFC_READL(MFC_REG_E_PICTURE_PROFILE); value &= ~(0x000F); value |= (buf_ctrl->old_val >> 8) & 0x000F; - MFC_WRITEL(value, S5P_FIMV_E_PICTURE_PROFILE); + MFC_WRITEL(value, MFC_REG_E_PICTURE_PROFILE); } if (buf_ctrl->id == V4L2_CID_MPEG_VIDEO_H264_PROFILE) { - value = MFC_READL(S5P_FIMV_E_PICTURE_PROFILE); + value = MFC_READL(MFC_REG_E_PICTURE_PROFILE); value &= ~(0xFF00); value |= buf_ctrl->old_val & 0xFF00; - MFC_WRITEL(value, S5P_FIMV_E_PICTURE_PROFILE); + MFC_WRITEL(value, MFC_REG_E_PICTURE_PROFILE); } if (buf_ctrl->id == V4L2_CID_MPEG_MFC_H264_BASE_PRIORITY) { - MFC_WRITEL(buf_ctrl->old_val, S5P_FIMV_E_H264_HD_SVC_EXTENSION_0); - MFC_WRITEL(buf_ctrl->old_val2, S5P_FIMV_E_H264_HD_SVC_EXTENSION_1); + MFC_WRITEL(buf_ctrl->old_val, MFC_REG_E_H264_HD_SVC_EXTENSION_0); + MFC_WRITEL(buf_ctrl->old_val2, MFC_REG_E_H264_HD_SVC_EXTENSION_1); } if (buf_ctrl->id == V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_CH || @@ -1560,23 +1560,23 @@ static int s5p_mfc_enc_recover_buf_ctrls_val(struct s5p_mfc_ctx *ctx, == V4L2_CID_MPEG_VIDEO_VP8_HIERARCHICAL_CODING_LAYER_CH || buf_ctrl->id == V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_CH) { - MFC_WRITEL(buf_ctrl->old_val2, S5P_FIMV_E_NUM_T_LAYER); + MFC_WRITEL(buf_ctrl->old_val2, MFC_REG_E_NUM_T_LAYER); /* clear RC_BIT_RATE_CHANGE */ value = MFC_READL(buf_ctrl->flag_addr); value &= ~(1 << 2); MFC_WRITEL(value, buf_ctrl->flag_addr); } if (buf_ctrl->id == V4L2_CID_MPEG_MFC_H264_MARK_LTR) { - value = MFC_READL(S5P_FIMV_E_H264_NAL_CONTROL); + value = MFC_READL(MFC_REG_E_H264_NAL_CONTROL); value &= ~(0x7 << 8); value |= (buf_ctrl->old_val2 & 0x7) << 8; - MFC_WRITEL(value, S5P_FIMV_E_H264_NAL_CONTROL); + MFC_WRITEL(value, MFC_REG_E_H264_NAL_CONTROL); } if (buf_ctrl->id == V4L2_CID_MPEG_MFC_H264_USE_LTR) { - value = MFC_READL(S5P_FIMV_E_H264_NAL_CONTROL); + value = MFC_READL(MFC_REG_E_H264_NAL_CONTROL); value &= ~(0xF << 11); value |= (buf_ctrl->old_val2 & 0xF) << 11; - MFC_WRITEL(value, S5P_FIMV_E_H264_NAL_CONTROL); + MFC_WRITEL(value, MFC_REG_E_H264_NAL_CONTROL); } buf_ctrl->updated = 0; } @@ -1584,10 +1584,10 @@ static int s5p_mfc_enc_recover_buf_ctrls_val(struct s5p_mfc_ctx *ctx, return 0; } -static int s5p_mfc_enc_recover_buf_ctrls_nal_q(struct s5p_mfc_ctx *ctx, +static int mfc_enc_recover_buf_ctrls_nal_q(struct mfc_ctx *ctx, struct list_head *head) { - struct s5p_mfc_buf_ctrl *buf_ctrl; + struct mfc_buf_ctrl *buf_ctrl; list_for_each_entry(buf_ctrl, head, list) { if (!(buf_ctrl->type & MFC_CTRL_TYPE_SET) @@ -1604,19 +1604,19 @@ static int s5p_mfc_enc_recover_buf_ctrls_nal_q(struct s5p_mfc_ctx *ctx, return 0; } -struct s5p_mfc_ctrls_ops encoder_ctrls_ops = { - .init_ctx_ctrls = s5p_mfc_enc_init_ctx_ctrls, - .cleanup_ctx_ctrls = s5p_mfc_enc_cleanup_ctx_ctrls, - .init_buf_ctrls = s5p_mfc_enc_init_buf_ctrls, - .reset_buf_ctrls = s5p_mfc_enc_reset_buf_ctrls, - .cleanup_buf_ctrls = s5p_mfc_enc_cleanup_buf_ctrls, - .to_buf_ctrls = s5p_mfc_enc_to_buf_ctrls, - .to_ctx_ctrls = s5p_mfc_enc_to_ctx_ctrls, - .set_buf_ctrls_val = s5p_mfc_enc_set_buf_ctrls_val, - .get_buf_ctrls_val = s5p_mfc_enc_get_buf_ctrls_val, - .recover_buf_ctrls_val = s5p_mfc_enc_recover_buf_ctrls_val, - .get_buf_update_val = s5p_mfc_enc_get_buf_update_val, - .set_buf_ctrls_val_nal_q_enc = s5p_mfc_enc_set_buf_ctrls_val_nal_q_enc, - .get_buf_ctrls_val_nal_q_enc = s5p_mfc_enc_get_buf_ctrls_val_nal_q_enc, - .recover_buf_ctrls_nal_q = s5p_mfc_enc_recover_buf_ctrls_nal_q, +struct mfc_ctrls_ops encoder_ctrls_ops = { + .init_ctx_ctrls = mfc_enc_init_ctx_ctrls, + .cleanup_ctx_ctrls = mfc_enc_cleanup_ctx_ctrls, + .init_buf_ctrls = mfc_enc_init_buf_ctrls, + .reset_buf_ctrls = mfc_enc_reset_buf_ctrls, + .cleanup_buf_ctrls = mfc_enc_cleanup_buf_ctrls, + .to_buf_ctrls = mfc_enc_to_buf_ctrls, + .to_ctx_ctrls = mfc_enc_to_ctx_ctrls, + .set_buf_ctrls_val = mfc_enc_set_buf_ctrls_val, + .get_buf_ctrls_val = mfc_enc_get_buf_ctrls_val, + .recover_buf_ctrls_val = mfc_enc_recover_buf_ctrls_val, + .get_buf_update_val = mfc_enc_get_buf_update_val, + .set_buf_ctrls_val_nal_q_enc = mfc_enc_set_buf_ctrls_val_nal_q_enc, + .get_buf_ctrls_val_nal_q_enc = mfc_enc_get_buf_ctrls_val_nal_q_enc, + .recover_buf_ctrls_nal_q = mfc_enc_recover_buf_ctrls_nal_q, }; diff --git a/drivers/media/platform/exynos/mfc/mfc_enc_param.c b/drivers/media/platform/exynos/mfc/mfc_enc_param.c index e6ce770fb382..aaea80deb188 100644 --- a/drivers/media/platform/exynos/mfc/mfc_enc_param.c +++ b/drivers/media/platform/exynos/mfc/mfc_enc_param.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_enc_param.c + * drivers/media/platform/exynos/mfc/mfc_enc_param.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -20,39 +20,39 @@ #define CBR_I_LIMIT_MAX 5 #define BPG_EXTENSION_TAG_SIZE 5 -void s5p_mfc_set_slice_mode(struct s5p_mfc_ctx *ctx) +void mfc_set_slice_mode(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_enc *enc = ctx->enc_priv; + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; /* multi-slice control */ if (enc->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) - MFC_WRITEL((enc->slice_mode + 0x4), S5P_FIMV_E_MSLICE_MODE); + MFC_WRITEL((enc->slice_mode + 0x4), MFC_REG_E_MSLICE_MODE); else if (enc->slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB_ROW) - MFC_WRITEL((enc->slice_mode - 0x2), S5P_FIMV_E_MSLICE_MODE); + MFC_WRITEL((enc->slice_mode - 0x2), MFC_REG_E_MSLICE_MODE); else if (enc->slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_FIXED_BYTES) - MFC_WRITEL((enc->slice_mode + 0x3), S5P_FIMV_E_MSLICE_MODE); + MFC_WRITEL((enc->slice_mode + 0x3), MFC_REG_E_MSLICE_MODE); else - MFC_WRITEL(enc->slice_mode, S5P_FIMV_E_MSLICE_MODE); + MFC_WRITEL(enc->slice_mode, MFC_REG_E_MSLICE_MODE); /* multi-slice MB number or bit size */ if ((enc->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) || (enc->slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB_ROW)) { - MFC_WRITEL(enc->slice_size.mb, S5P_FIMV_E_MSLICE_SIZE_MB); + MFC_WRITEL(enc->slice_size.mb, MFC_REG_E_MSLICE_SIZE_MB); } else if ((enc->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) || (enc->slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_FIXED_BYTES)){ - MFC_WRITEL(enc->slice_size.bits, S5P_FIMV_E_MSLICE_SIZE_BITS); + MFC_WRITEL(enc->slice_size.bits, MFC_REG_E_MSLICE_SIZE_BITS); } else { - MFC_WRITEL(0x0, S5P_FIMV_E_MSLICE_SIZE_MB); - MFC_WRITEL(0x0, S5P_FIMV_E_MSLICE_SIZE_BITS); + MFC_WRITEL(0x0, MFC_REG_E_MSLICE_SIZE_MB); + MFC_WRITEL(0x0, MFC_REG_E_MSLICE_SIZE_BITS); } } -static void mfc_set_gop_size(struct s5p_mfc_ctx *ctx, int ctrl_mode) +static void __mfc_set_gop_size(struct mfc_ctx *ctx, int ctrl_mode) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_enc *enc = ctx->enc_priv; - struct s5p_mfc_enc_params *p = &enc->params; + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; unsigned int reg = 0; if (ctrl_mode) { @@ -73,7 +73,7 @@ static void mfc_set_gop_size(struct s5p_mfc_ctx *ctx, int ctrl_mode) p->num_b_frame, p->i_frm_ctrl_mode); /* pictype : IDR period, number of B */ - reg = MFC_READL(S5P_FIMV_E_GOP_CONFIG); + reg = MFC_READL(MFC_REG_E_GOP_CONFIG); reg &= ~(0xFFFF); reg |= p->i_frm_ctrl & 0xFFFF; reg &= ~(0x1 << 19); @@ -81,17 +81,17 @@ static void mfc_set_gop_size(struct s5p_mfc_ctx *ctx, int ctrl_mode) reg &= ~(0x3 << 16); /* if B frame is used, the performance falls by half */ reg |= (p->num_b_frame << 16); - MFC_WRITEL(reg, S5P_FIMV_E_GOP_CONFIG); + MFC_WRITEL(reg, MFC_REG_E_GOP_CONFIG); - reg = MFC_READL(S5P_FIMV_E_GOP_CONFIG2); + reg = MFC_READL(MFC_REG_E_GOP_CONFIG2); reg &= ~(0x3FFF); reg |= (p->i_frm_ctrl >> 16) & 0x3FFF; - MFC_WRITEL(reg, S5P_FIMV_E_GOP_CONFIG2); + MFC_WRITEL(reg, MFC_REG_E_GOP_CONFIG2); } -static void mfc_set_default_params(struct s5p_mfc_ctx *ctx) +static void __mfc_set_default_params(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; int i; mfc_debug(2, "Set default param - enc_param_num: %d\n", dev->pdata->enc_param_num); @@ -107,41 +107,41 @@ static void mfc_set_default_params(struct s5p_mfc_ctx *ctx) } } -static void mfc_init_regs(struct s5p_mfc_ctx *ctx) +static void __mfc_init_regs(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; /* Register initialization */ - MFC_WRITEL(0x0, S5P_FIMV_E_FRAME_INSERTION); - MFC_WRITEL(0x0, S5P_FIMV_E_ROI_BUFFER_ADDR); - MFC_WRITEL(0x0, S5P_FIMV_E_PARAM_CHANGE); - MFC_WRITEL(0x0, S5P_FIMV_E_PICTURE_TAG); - MFC_WRITEL(0x0, S5P_FIMV_E_METADATA_BUFFER_ADDR); - MFC_WRITEL(0x0, S5P_FIMV_E_METADATA_BUFFER_SIZE); + MFC_WRITEL(0x0, MFC_REG_E_FRAME_INSERTION); + MFC_WRITEL(0x0, MFC_REG_E_ROI_BUFFER_ADDR); + MFC_WRITEL(0x0, MFC_REG_E_PARAM_CHANGE); + MFC_WRITEL(0x0, MFC_REG_E_PICTURE_TAG); + MFC_WRITEL(0x0, MFC_REG_E_METADATA_BUFFER_ADDR); + MFC_WRITEL(0x0, MFC_REG_E_METADATA_BUFFER_SIZE); } -static void mfc_set_enc_params(struct s5p_mfc_ctx *ctx) +static void __mfc_set_enc_params(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_enc *enc = ctx->enc_priv; - struct s5p_mfc_enc_params *p = &enc->params; + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; unsigned int reg = 0; mfc_debug_enter(); - mfc_init_regs(ctx); - mfc_set_default_params(ctx); + __mfc_init_regs(ctx); + __mfc_set_default_params(ctx); /* width */ - MFC_WRITEL(ctx->crop_width, S5P_FIMV_E_CROPPED_FRAME_WIDTH); + MFC_WRITEL(ctx->crop_width, MFC_REG_E_CROPPED_FRAME_WIDTH); /* height */ - MFC_WRITEL(ctx->crop_height, S5P_FIMV_E_CROPPED_FRAME_HEIGHT); + MFC_WRITEL(ctx->crop_height, MFC_REG_E_CROPPED_FRAME_HEIGHT); /* cropped offset */ - reg |= (ctx->crop_left & S5P_FIMV_E_FRAME_CROP_OFFSET_MASK) - << S5P_FIMV_E_FRAME_CROP_OFFSET_LEFT; - reg |= (ctx->crop_top & S5P_FIMV_E_FRAME_CROP_OFFSET_MASK) - << S5P_FIMV_E_FRAME_CROP_OFFSET_TOP; - MFC_WRITEL(reg, S5P_FIMV_E_FRAME_CROP_OFFSET); + reg |= (ctx->crop_left & MFC_REG_E_FRAME_CROP_OFFSET_MASK) + << MFC_REG_E_FRAME_CROP_OFFSET_LEFT; + reg |= (ctx->crop_top & MFC_REG_E_FRAME_CROP_OFFSET_MASK) + << MFC_REG_E_FRAME_CROP_OFFSET_TOP; + MFC_WRITEL(reg, MFC_REG_E_FRAME_CROP_OFFSET); /* multi-slice control */ /* multi-slice MB number or bit size */ @@ -159,12 +159,12 @@ static void mfc_set_enc_params(struct s5p_mfc_ctx *ctx) enc->slice_size.bits = 0; } - s5p_mfc_set_slice_mode(ctx); + mfc_set_slice_mode(ctx); /* cyclic intra refresh */ - MFC_WRITEL(p->intra_refresh_mb, S5P_FIMV_E_IR_SIZE); + MFC_WRITEL(p->intra_refresh_mb, MFC_REG_E_IR_SIZE); - reg = MFC_READL(S5P_FIMV_E_ENC_OPTIONS); + reg = MFC_READL(MFC_REG_E_ENC_OPTIONS); /* frame skip mode */ reg &= ~(0x3); reg |= (p->frame_skip_mode & 0x3); @@ -187,12 +187,12 @@ static void mfc_set_enc_params(struct s5p_mfc_ctx *ctx) reg &= ~(0x1 << 18); if (nal_q_parallel_disable) reg |= (0x1 << 18); - MFC_WRITEL(reg, S5P_FIMV_E_ENC_OPTIONS); + MFC_WRITEL(reg, MFC_REG_E_ENC_OPTIONS); - s5p_mfc_set_pixel_format(dev, ctx->src_fmt->fourcc); + mfc_set_pixel_format(dev, ctx->src_fmt->fourcc); /* padding control & value */ - MFC_WRITEL(0x0, S5P_FIMV_E_PADDING_CTRL); + MFC_WRITEL(0x0, MFC_REG_E_PADDING_CTRL); if (p->pad) { reg = 0; /** enable */ @@ -206,11 +206,11 @@ static void mfc_set_enc_params(struct s5p_mfc_ctx *ctx) /** y value */ reg &= ~(0xFF); reg |= (p->pad_luma); - MFC_WRITEL(reg, S5P_FIMV_E_PADDING_CTRL); + MFC_WRITEL(reg, MFC_REG_E_PADDING_CTRL); } /* rate control config. */ - reg = MFC_READL(S5P_FIMV_E_RC_CONFIG); + reg = MFC_READL(MFC_REG_E_RC_CONFIG); /* macroblock level rate control */ reg &= ~(0x1 << 8); reg |= ((p->rc_mb & 0x1) << 8); @@ -219,17 +219,17 @@ static void mfc_set_enc_params(struct s5p_mfc_ctx *ctx) reg |= ((p->rc_frame & 0x1) << 9); /* 'DROP_CONTROL_ENABLE', disable */ reg &= ~(0x1 << 10); - MFC_WRITEL(reg, S5P_FIMV_E_RC_CONFIG); + MFC_WRITEL(reg, MFC_REG_E_RC_CONFIG); /* bit rate */ - MFC_WRITEL(p->rc_bitrate, S5P_FIMV_E_RC_BIT_RATE); + MFC_WRITEL(p->rc_bitrate, MFC_REG_E_RC_BIT_RATE); - reg = MFC_READL(S5P_FIMV_E_RC_MODE); + reg = MFC_READL(MFC_REG_E_RC_MODE); reg &= ~(0x3 | (0x3 << 4) | (0xFF << 8)); if (p->rc_frame) { if (p->rc_reaction_coeff <= CBR_I_LIMIT_MAX) { - reg |= S5P_FIMV_E_RC_CBR_I_LIMIT; + reg |= MFC_REG_E_RC_CBR_I_LIMIT; /* * Ratio of intra for max frame size * is controled when only CBR_I_LIMIT mode. @@ -238,36 +238,36 @@ static void mfc_set_enc_params(struct s5p_mfc_ctx *ctx) if (p->ratio_intra) reg |= ((p->ratio_intra & 0xFF) << 8); } else if (p->rc_reaction_coeff <= CBR_FIX_MAX) { - reg |= S5P_FIMV_E_RC_CBR_FIX; + reg |= MFC_REG_E_RC_CBR_FIX; } else { - reg |= S5P_FIMV_E_RC_VBR; + reg |= MFC_REG_E_RC_VBR; } if (p->rc_mb) reg |= ((p->rc_pvc & 0x3) << 4); } - MFC_WRITEL(reg, S5P_FIMV_E_RC_MODE); + MFC_WRITEL(reg, MFC_REG_E_RC_MODE); /* extended encoder ctrl */ /** vbv buffer size */ - reg = MFC_READL(S5P_FIMV_E_VBV_BUFFER_SIZE); + reg = MFC_READL(MFC_REG_E_VBV_BUFFER_SIZE); reg &= ~(0xFF); if (p->frame_skip_mode == V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) reg |= p->vbv_buf_size & 0xFF; - MFC_WRITEL(reg, S5P_FIMV_E_VBV_BUFFER_SIZE); + MFC_WRITEL(reg, MFC_REG_E_VBV_BUFFER_SIZE); mfc_debug_leave(); } -static void mfc_set_temporal_svc_h264(struct s5p_mfc_ctx *ctx, struct s5p_mfc_h264_enc_params *p_264) +static void __mfc_set_temporal_svc_h264(struct mfc_ctx *ctx, struct mfc_h264_enc_params *p_264) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_enc *enc = ctx->enc_priv; - struct s5p_mfc_enc_params *p = &enc->params; + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; unsigned int reg = 0, reg2 = 0; int i; - reg = MFC_READL(S5P_FIMV_E_H264_OPTIONS_2); + reg = MFC_READL(MFC_REG_E_H264_OPTIONS_2); /* pic_order_cnt_type = 0 for backward compatibilities */ reg &= ~(0x3); /* Enable LTR */ @@ -278,10 +278,10 @@ static void mfc_set_temporal_svc_h264(struct s5p_mfc_ctx *ctx, struct s5p_mfc_h2 reg &= ~(0x3 << 7); if (p_264->num_of_ltr > 2) reg |= (((p_264->num_of_ltr - 2) & 0x3) << 7); - MFC_WRITEL(reg, S5P_FIMV_E_H264_OPTIONS_2); + MFC_WRITEL(reg, MFC_REG_E_H264_OPTIONS_2); /* Temporal SVC - qp type, layer number */ - reg = MFC_READL(S5P_FIMV_E_NUM_T_LAYER); + reg = MFC_READL(MFC_REG_E_NUM_T_LAYER); reg &= ~(0x1 << 3); reg |= (p_264->hier_qp_type & 0x1) << 3; reg &= ~(0x7); @@ -296,7 +296,7 @@ static void mfc_set_temporal_svc_h264(struct s5p_mfc_ctx *ctx, struct s5p_mfc_h2 } reg &= ~(0x1 << 8); reg |= (p->hier_bitrate_ctrl & 0x1) << 8; - MFC_WRITEL(reg, S5P_FIMV_E_NUM_T_LAYER); + MFC_WRITEL(reg, MFC_REG_E_NUM_T_LAYER); mfc_debug(3, "[HIERARCHICAL] hier_qp_enable %d, enable_ltr %d, " "num_hier_layer %d, max_layer %d, hier_ref_type %d, NUM_T_LAYER 0x%x\n", p_264->hier_qp_enable, p_264->enable_ltr, p_264->num_hier_layer, @@ -304,10 +304,10 @@ static void mfc_set_temporal_svc_h264(struct s5p_mfc_ctx *ctx, struct s5p_mfc_h2 /* QP & Bitrate for each layer */ for (i = 0; i < 7; i++) { MFC_WRITEL(p_264->hier_qp_layer[i], - S5P_FIMV_E_HIERARCHICAL_QP_LAYER0 + i * 4); + MFC_REG_E_HIERARCHICAL_QP_LAYER0 + i * 4); /* If hier_bitrate_ctrl is set to 1, this is meaningless */ MFC_WRITEL(p_264->hier_bit_layer[i], - S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0 + i * 4); + MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER0 + i * 4); mfc_debug(3, "[HIERARCHICAL] layer[%d] QP: %#x, bitrate: %d(FW ctrl: %d)\n", i, p_264->hier_qp_layer[i], p_264->hier_bit_layer[i], p->hier_bitrate_ctrl); @@ -321,16 +321,16 @@ static void mfc_set_temporal_svc_h264(struct s5p_mfc_ctx *ctx, struct s5p_mfc_h2 else reg2 |= ((p_264->base_priority & 0x3F) + i) << (6 * (i - 5)); } - MFC_WRITEL(reg, S5P_FIMV_E_H264_HD_SVC_EXTENSION_0); - MFC_WRITEL(reg2, S5P_FIMV_E_H264_HD_SVC_EXTENSION_1); + MFC_WRITEL(reg, MFC_REG_E_H264_HD_SVC_EXTENSION_0); + MFC_WRITEL(reg2, MFC_REG_E_H264_HD_SVC_EXTENSION_1); mfc_debug(3, "[HIERARCHICAL] priority EXTENSION0: %#x, EXTENSION1: %#x\n", reg, reg2); } } -static void mfc_set_fmo_slice_map_h264(struct s5p_mfc_ctx *ctx, struct s5p_mfc_h264_enc_params *p_264) +static void __mfc_set_fmo_slice_map_h264(struct mfc_ctx *ctx, struct mfc_h264_enc_params *p_264) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; int i; if (p_264->fmo_enable) { @@ -340,7 +340,7 @@ static void mfc_set_fmo_slice_map_h264(struct s5p_mfc_ctx *ctx, struct s5p_mfc_h p_264->fmo_slice_num_grp = 4; for (i = 0; i < (p_264->fmo_slice_num_grp & 0xF); i++) MFC_WRITEL(p_264->fmo_run_length[i] - 1, - S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_0 + i*4); + MFC_REG_E_H264_FMO_RUN_LENGTH_MINUS1_0 + i*4); break; case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES: if (p_264->fmo_slice_num_grp > 4) @@ -351,9 +351,9 @@ static void mfc_set_fmo_slice_map_h264(struct s5p_mfc_ctx *ctx, struct s5p_mfc_h if (p_264->fmo_slice_num_grp > 2) p_264->fmo_slice_num_grp = 2; MFC_WRITEL(p_264->fmo_sg_dir & 0x1, - S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_DIR); + MFC_REG_E_H264_FMO_SLICE_GRP_CHANGE_DIR); /* the valid range is 0 ~ number of macroblocks -1 */ - MFC_WRITEL(p_264->fmo_sg_rate, S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_RATE_MINUS1); + MFC_WRITEL(p_264->fmo_sg_rate, MFC_REG_E_H264_FMO_SLICE_GRP_CHANGE_RATE_MINUS1); break; default: mfc_err_ctx("Unsupported map type for FMO: %d\n", @@ -363,31 +363,31 @@ static void mfc_set_fmo_slice_map_h264(struct s5p_mfc_ctx *ctx, struct s5p_mfc_h break; } - MFC_WRITEL(p_264->fmo_slice_map_type, S5P_FIMV_E_H264_FMO_SLICE_GRP_MAP_TYPE); - MFC_WRITEL(p_264->fmo_slice_num_grp - 1, S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1); + MFC_WRITEL(p_264->fmo_slice_map_type, MFC_REG_E_H264_FMO_SLICE_GRP_MAP_TYPE); + MFC_WRITEL(p_264->fmo_slice_num_grp - 1, MFC_REG_E_H264_FMO_NUM_SLICE_GRP_MINUS1); } else { - MFC_WRITEL(0, S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1); + MFC_WRITEL(0, MFC_REG_E_H264_FMO_NUM_SLICE_GRP_MINUS1); } } -void s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) +void mfc_set_enc_params_h264(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_enc *enc = ctx->enc_priv; - struct s5p_mfc_enc_params *p = &enc->params; - struct s5p_mfc_h264_enc_params *p_264 = &p->codec.h264; + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + struct mfc_h264_enc_params *p_264 = &p->codec.h264; unsigned int reg = 0; mfc_debug_enter(); - mfc_set_enc_params(ctx); + __mfc_set_enc_params(ctx); if (p_264->num_hier_layer & 0x7) { /* set gop_size without i_frm_ctrl mode */ - mfc_set_gop_size(ctx, 0); + __mfc_set_gop_size(ctx, 0); } else { /* set gop_size with i_frm_ctrl mode */ - mfc_set_gop_size(ctx, 1); + __mfc_set_gop_size(ctx, 1); } /* UHD encoding case */ @@ -410,9 +410,9 @@ void s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) /** profile - 0 ~ 3 */ reg &= ~(0x3F); reg |= p_264->profile; - MFC_WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE); + MFC_WRITEL(reg, MFC_REG_E_PICTURE_PROFILE); - reg = MFC_READL(S5P_FIMV_E_H264_OPTIONS); + reg = MFC_READL(MFC_REG_E_H264_OPTIONS); /* entropy coding mode */ reg &= ~(0x1); reg |= (p_264->entropy_mode & 0x1); @@ -463,56 +463,56 @@ void s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) /* VUI parameter disable */ reg &= ~(0x1 << 30); reg |= ((p_264->vui_enable & 0x1) << 30); - MFC_WRITEL(reg, S5P_FIMV_E_H264_OPTIONS); + MFC_WRITEL(reg, MFC_REG_E_H264_OPTIONS); /* cropped height */ if (p_264->interlace) - MFC_WRITEL(ctx->crop_height >> 1, S5P_FIMV_E_CROPPED_FRAME_HEIGHT); + MFC_WRITEL(ctx->crop_height >> 1, MFC_REG_E_CROPPED_FRAME_HEIGHT); /* loopfilter alpha offset */ - reg = MFC_READL(S5P_FIMV_E_H264_LF_ALPHA_OFFSET); + reg = MFC_READL(MFC_REG_E_H264_LF_ALPHA_OFFSET); reg &= ~(0x1F); reg |= (p_264->loop_filter_alpha & 0x1F); - MFC_WRITEL(reg, S5P_FIMV_E_H264_LF_ALPHA_OFFSET); + MFC_WRITEL(reg, MFC_REG_E_H264_LF_ALPHA_OFFSET); /* loopfilter beta offset */ - reg = MFC_READL(S5P_FIMV_E_H264_LF_BETA_OFFSET); + reg = MFC_READL(MFC_REG_E_H264_LF_BETA_OFFSET); reg &= ~(0x1F); reg |= (p_264->loop_filter_beta & 0x1F); - MFC_WRITEL(reg, S5P_FIMV_E_H264_LF_BETA_OFFSET); + MFC_WRITEL(reg, MFC_REG_E_H264_LF_BETA_OFFSET); /* rate control config. */ - reg = MFC_READL(S5P_FIMV_E_RC_CONFIG); + reg = MFC_READL(MFC_REG_E_RC_CONFIG); /** frame QP */ reg &= ~(0xFF); reg |= (p_264->rc_frame_qp & 0xFF); reg &= ~(0x1 << 11); if (!p->rc_frame && !p->rc_mb && p->dynamic_qp) reg |= (0x1 << 11); - MFC_WRITEL(reg, S5P_FIMV_E_RC_CONFIG); + MFC_WRITEL(reg, MFC_REG_E_RC_CONFIG); /* frame rate */ /* Fix value for H.264, H.263 in the driver */ p->rc_frame_delta = FRAME_DELTA_DEFAULT; - reg = MFC_READL(S5P_FIMV_E_RC_FRAME_RATE); + reg = MFC_READL(MFC_REG_E_RC_FRAME_RATE); reg &= ~(0xFFFF << 16); reg |= (p->rc_framerate << 16); reg &= ~(0xFFFF); reg |= p->rc_frame_delta & 0xFFFF; - MFC_WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE); + MFC_WRITEL(reg, MFC_REG_E_RC_FRAME_RATE); /* max & min value of QP for I frame */ - reg = MFC_READL(S5P_FIMV_E_RC_QP_BOUND); + reg = MFC_READL(MFC_REG_E_RC_QP_BOUND); /** max I frame QP */ reg &= ~(0xFF << 8); reg |= ((p_264->rc_max_qp & 0xFF) << 8); /** min I frame QP */ reg &= ~(0xFF); reg |= p_264->rc_min_qp & 0xFF; - MFC_WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND); + MFC_WRITEL(reg, MFC_REG_E_RC_QP_BOUND); /* max & min value of QP for P/B frame */ - reg = MFC_READL(S5P_FIMV_E_RC_QP_BOUND_PB); + reg = MFC_READL(MFC_REG_E_RC_QP_BOUND_PB); /** max B frame QP */ reg &= ~(0xFF << 24); reg |= ((p_264->rc_max_qp_b & 0xFF) << 24); @@ -525,9 +525,9 @@ void s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) /** min P frame QP */ reg &= ~(0xFF); reg |= p_264->rc_min_qp_p & 0xFF; - MFC_WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND_PB); + MFC_WRITEL(reg, MFC_REG_E_RC_QP_BOUND_PB); - reg = MFC_READL(S5P_FIMV_E_FIXED_PICTURE_QP); + reg = MFC_READL(MFC_REG_E_FIXED_PICTURE_QP); reg &= ~(0xFF << 24); reg |= ((p->config_qp & 0xFF) << 24); reg &= ~(0xFF << 16); @@ -536,41 +536,41 @@ void s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) reg |= ((p_264->rc_p_frame_qp & 0xFF) << 8); reg &= ~(0xFF); reg |= (p_264->rc_frame_qp & 0xFF); - MFC_WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP); + MFC_WRITEL(reg, MFC_REG_E_FIXED_PICTURE_QP); - MFC_WRITEL(0x0, S5P_FIMV_E_ASPECT_RATIO); - MFC_WRITEL(0x0, S5P_FIMV_E_EXTENDED_SAR); + MFC_WRITEL(0x0, MFC_REG_E_ASPECT_RATIO); + MFC_WRITEL(0x0, MFC_REG_E_EXTENDED_SAR); if (p_264->ar_vui) { /* aspect ration IDC */ reg = 0; reg &= ~(0xff); reg |= p_264->ar_vui_idc; - MFC_WRITEL(reg, S5P_FIMV_E_ASPECT_RATIO); + MFC_WRITEL(reg, MFC_REG_E_ASPECT_RATIO); if (p_264->ar_vui_idc == 0xFF) { /* sample AR info. */ reg = 0; reg &= ~(0xffffffff); reg |= p_264->ext_sar_width << 16; reg |= p_264->ext_sar_height; - MFC_WRITEL(reg, S5P_FIMV_E_EXTENDED_SAR); + MFC_WRITEL(reg, MFC_REG_E_EXTENDED_SAR); } } /* intra picture period for H.264 open GOP, value */ - reg = MFC_READL(S5P_FIMV_E_H264_REFRESH_PERIOD); + reg = MFC_READL(MFC_REG_E_H264_REFRESH_PERIOD); reg &= ~(0xFFFF); if (p_264->open_gop) reg |= (p_264->open_gop_size & 0xFFFF); - MFC_WRITEL(reg, S5P_FIMV_E_H264_REFRESH_PERIOD); + MFC_WRITEL(reg, MFC_REG_E_H264_REFRESH_PERIOD); /* Temporal SVC */ - mfc_set_temporal_svc_h264(ctx, p_264); + __mfc_set_temporal_svc_h264(ctx, p_264); /* set frame pack sei generation */ if (p_264->sei_gen_enable) { /* frame packing enable */ - reg = MFC_READL(S5P_FIMV_E_H264_OPTIONS); + reg = MFC_READL(MFC_REG_E_H264_OPTIONS); reg |= (1 << 25); - MFC_WRITEL(reg, S5P_FIMV_E_H264_OPTIONS); + MFC_WRITEL(reg, MFC_REG_E_H264_OPTIONS); /* set current frame0 flag & arrangement type */ reg = 0; @@ -578,11 +578,11 @@ void s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) reg |= ((p_264->sei_fp_curr_frame_0 & 0x1) << 2); /** arrangement type */ reg |= (p_264->sei_fp_arrangement_type - 3) & 0x3; - MFC_WRITEL(reg, S5P_FIMV_E_H264_FRAME_PACKING_SEI_INFO); + MFC_WRITEL(reg, MFC_REG_E_H264_FRAME_PACKING_SEI_INFO); } if (MFC_FEATURE_SUPPORT(dev, dev->pdata->color_aspect_enc) && p->check_color_range) { - reg = MFC_READL(S5P_FIMV_E_VIDEO_SIGNAL_TYPE); + reg = MFC_READL(MFC_REG_E_VIDEO_SIGNAL_TYPE); /* VIDEO_SIGNAL_TYPE_FLAG */ reg |= 0x1 << 31; /* COLOR_RANGE */ @@ -604,33 +604,33 @@ void s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) } else { reg &= ~(0x1 << 24); } - MFC_WRITEL(reg, S5P_FIMV_E_VIDEO_SIGNAL_TYPE); + MFC_WRITEL(reg, MFC_REG_E_VIDEO_SIGNAL_TYPE); mfc_debug(2, "[HDR] H264 ENC Color aspect: range(%s), pri(%d), trans(%d), mat(%d)\n", p->color_range ? "Full" : "Limited", p->colour_primaries, p->transfer_characteristics, p->matrix_coefficients); } else { - MFC_WRITEL(0, S5P_FIMV_E_VIDEO_SIGNAL_TYPE); + MFC_WRITEL(0, MFC_REG_E_VIDEO_SIGNAL_TYPE); } - mfc_set_fmo_slice_map_h264(ctx, p_264); + __mfc_set_fmo_slice_map_h264(ctx, p_264); mfc_debug_leave(); } -void s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx) +void mfc_set_enc_params_mpeg4(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_enc *enc = ctx->enc_priv; - struct s5p_mfc_enc_params *p = &enc->params; - struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4; + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + struct mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4; unsigned int reg = 0; mfc_debug_enter(); - mfc_set_enc_params(ctx); + __mfc_set_enc_params(ctx); /* set gop_size with I_FRM_CTRL mode */ - mfc_set_gop_size(ctx, 1); + __mfc_set_gop_size(ctx, 1); /* profile & level */ reg = 0; @@ -640,13 +640,13 @@ void s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx) /** profile - 0 ~ 1 */ reg &= ~(0x3F); reg |= p_mpeg4->profile; - MFC_WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE); + MFC_WRITEL(reg, MFC_REG_E_PICTURE_PROFILE); /* quarter_pixel */ - /* MFC_WRITEL(p_mpeg4->quarter_pixel, S5P_FIMV_ENC_MPEG4_QUART_PXL); */ + /* MFC_WRITEL(p_mpeg4->quarter_pixel, MFC_REG_ENC_MPEG4_QUART_PXL); */ /* qp */ - reg = MFC_READL(S5P_FIMV_E_FIXED_PICTURE_QP); + reg = MFC_READL(MFC_REG_E_FIXED_PICTURE_QP); reg &= ~(0xFF << 24); reg |= ((p->config_qp & 0xFF) << 24); reg &= ~(0xFF << 16); @@ -655,36 +655,36 @@ void s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx) reg |= ((p_mpeg4->rc_p_frame_qp & 0xFF) << 8); reg &= ~(0xFF); reg |= (p_mpeg4->rc_frame_qp & 0xFF); - MFC_WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP); + MFC_WRITEL(reg, MFC_REG_E_FIXED_PICTURE_QP); /* frame rate */ p->rc_frame_delta = p_mpeg4->vop_frm_delta; - reg = MFC_READL(S5P_FIMV_E_RC_FRAME_RATE); + reg = MFC_READL(MFC_REG_E_RC_FRAME_RATE); reg &= ~(0xFFFF << 16); reg |= (p_mpeg4->vop_time_res << 16); reg &= ~(0xFFFF); reg |= (p_mpeg4->vop_frm_delta & 0xFFFF); - MFC_WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE); + MFC_WRITEL(reg, MFC_REG_E_RC_FRAME_RATE); /* rate control config. */ - reg = MFC_READL(S5P_FIMV_E_RC_CONFIG); + reg = MFC_READL(MFC_REG_E_RC_CONFIG); /** frame QP */ reg &= ~(0xFF); reg |= (p_mpeg4->rc_frame_qp & 0xFF); - MFC_WRITEL(reg, S5P_FIMV_E_RC_CONFIG); + MFC_WRITEL(reg, MFC_REG_E_RC_CONFIG); /* max & min value of QP for I frame */ - reg = MFC_READL(S5P_FIMV_E_RC_QP_BOUND); + reg = MFC_READL(MFC_REG_E_RC_QP_BOUND); /** max I frame QP */ reg &= ~(0xFF << 8); reg |= ((p_mpeg4->rc_max_qp & 0xFF) << 8); /** min I frame QP */ reg &= ~(0xFF); reg |= (p_mpeg4->rc_min_qp & 0xFF); - MFC_WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND); + MFC_WRITEL(reg, MFC_REG_E_RC_QP_BOUND); /* max & min value of QP for P/B frame */ - reg = MFC_READL(S5P_FIMV_E_RC_QP_BOUND_PB); + reg = MFC_READL(MFC_REG_E_RC_QP_BOUND_PB); /** max B frame QP */ reg &= ~(0xFF << 24); reg |= ((p_mpeg4->rc_max_qp_b & 0xFF) << 24); @@ -697,109 +697,109 @@ void s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx) /** min P frame QP */ reg &= ~(0xFF); reg |= p_mpeg4->rc_min_qp_p & 0xFF; - MFC_WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND_PB); + MFC_WRITEL(reg, MFC_REG_E_RC_QP_BOUND_PB); /* initialize for '0' only setting*/ - MFC_WRITEL(0x0, S5P_FIMV_E_MPEG4_OPTIONS); /* SEQ_start only */ - MFC_WRITEL(0x0, S5P_FIMV_E_MPEG4_HEC_PERIOD); /* SEQ_start only */ + MFC_WRITEL(0x0, MFC_REG_E_MPEG4_OPTIONS); /* SEQ_start only */ + MFC_WRITEL(0x0, MFC_REG_E_MPEG4_HEC_PERIOD); /* SEQ_start only */ mfc_debug_leave(); } -void s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx) +void mfc_set_enc_params_h263(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_enc *enc = ctx->enc_priv; - struct s5p_mfc_enc_params *p = &enc->params; - struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4; + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + struct mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4; unsigned int reg = 0; mfc_debug_enter(); - mfc_set_enc_params(ctx); + __mfc_set_enc_params(ctx); /* set gop_size with I_FRM_CTRL mode */ - mfc_set_gop_size(ctx, 1); + __mfc_set_gop_size(ctx, 1); /* profile & level: supports only baseline profile Level 70 */ /* qp */ - reg = MFC_READL(S5P_FIMV_E_FIXED_PICTURE_QP); + reg = MFC_READL(MFC_REG_E_FIXED_PICTURE_QP); reg &= ~(0xFF << 24); reg |= ((p->config_qp & 0xFF) << 24); reg &= ~(0xFF << 8); reg |= ((p_mpeg4->rc_p_frame_qp & 0xFF) << 8); reg &= ~(0xFF); reg |= (p_mpeg4->rc_frame_qp & 0xFF); - MFC_WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP); + MFC_WRITEL(reg, MFC_REG_E_FIXED_PICTURE_QP); /* frame rate */ /* Fix value for H.264, H.263 in the driver */ p->rc_frame_delta = FRAME_DELTA_DEFAULT; - reg = MFC_READL(S5P_FIMV_E_RC_FRAME_RATE); + reg = MFC_READL(MFC_REG_E_RC_FRAME_RATE); reg &= ~(0xFFFF << 16); reg |= (p->rc_framerate << 16); reg &= ~(0xFFFF); reg |= (p->rc_frame_delta & 0xFFFF); - MFC_WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE); + MFC_WRITEL(reg, MFC_REG_E_RC_FRAME_RATE); /* rate control config. */ - reg = MFC_READL(S5P_FIMV_E_RC_CONFIG); + reg = MFC_READL(MFC_REG_E_RC_CONFIG); /** frame QP */ reg &= ~(0xFF); reg |= (p_mpeg4->rc_frame_qp & 0xFF); - MFC_WRITEL(reg, S5P_FIMV_E_RC_CONFIG); + MFC_WRITEL(reg, MFC_REG_E_RC_CONFIG); /* max & min value of QP for I frame */ - reg = MFC_READL(S5P_FIMV_E_RC_QP_BOUND); + reg = MFC_READL(MFC_REG_E_RC_QP_BOUND); /** max I frame QP */ reg &= ~(0xFF << 8); reg |= ((p_mpeg4->rc_max_qp & 0xFF) << 8); /** min I frame QP */ reg &= ~(0xFF); reg |= (p_mpeg4->rc_min_qp & 0xFF); - MFC_WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND); + MFC_WRITEL(reg, MFC_REG_E_RC_QP_BOUND); /* max & min value of QP for P/B frame */ - reg = MFC_READL(S5P_FIMV_E_RC_QP_BOUND_PB); + reg = MFC_READL(MFC_REG_E_RC_QP_BOUND_PB); /** max P frame QP */ reg &= ~(0xFF << 8); reg |= ((p_mpeg4->rc_max_qp_p & 0xFF) << 8); /** min P frame QP */ reg &= ~(0xFF); reg |= p_mpeg4->rc_min_qp_p & 0xFF; - MFC_WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND_PB); + MFC_WRITEL(reg, MFC_REG_E_RC_QP_BOUND_PB); mfc_debug_leave(); } -void s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx) +void mfc_set_enc_params_vp8(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_enc *enc = ctx->enc_priv; - struct s5p_mfc_enc_params *p = &enc->params; - struct s5p_mfc_vp8_enc_params *p_vp8 = &p->codec.vp8; + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + struct mfc_vp8_enc_params *p_vp8 = &p->codec.vp8; unsigned int reg = 0; int i; mfc_debug_enter(); - mfc_set_enc_params(ctx); + __mfc_set_enc_params(ctx); if (p_vp8->num_hier_layer & 0x3) { /* set gop_size without i_frm_ctrl mode */ - mfc_set_gop_size(ctx, 0); + __mfc_set_gop_size(ctx, 0); } else { /* set gop_size with i_frm_ctrl mode */ - mfc_set_gop_size(ctx, 1); + __mfc_set_gop_size(ctx, 1); } /* profile*/ reg = 0; reg |= (p_vp8->vp8_version) ; - MFC_WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE); + MFC_WRITEL(reg, MFC_REG_E_PICTURE_PROFILE); - reg = MFC_READL(S5P_FIMV_E_VP8_OPTION); + reg = MFC_READL(MFC_REG_E_VP8_OPTION); /* if num_refs_for_p is 2, the performance falls by half */ reg &= ~(0x1); reg |= (p->num_refs_for_p - 1) & 0x1; @@ -820,34 +820,34 @@ void s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx) /* Disable IVF header */ reg &= ~(0x1 << 12); reg |= ((p->ivf_header_disable & 0x1) << 12); - MFC_WRITEL(reg, S5P_FIMV_E_VP8_OPTION); + MFC_WRITEL(reg, MFC_REG_E_VP8_OPTION); - reg = MFC_READL(S5P_FIMV_E_VP8_GOLDEN_FRAME_OPTION); + reg = MFC_READL(MFC_REG_E_VP8_GOLDEN_FRAME_OPTION); reg &= ~(0x1); reg |= (p_vp8->vp8_goldenframesel & 0x1); reg &= ~(0xFFFF << 1); reg |= (p_vp8->vp8_gfrefreshperiod & 0xFFFF) << 1; - MFC_WRITEL(reg, S5P_FIMV_E_VP8_GOLDEN_FRAME_OPTION); + MFC_WRITEL(reg, MFC_REG_E_VP8_GOLDEN_FRAME_OPTION); /* Temporal SVC - layer number */ - reg = MFC_READL(S5P_FIMV_E_NUM_T_LAYER); + reg = MFC_READL(MFC_REG_E_NUM_T_LAYER); reg &= ~(0x7); reg |= p_vp8->num_hier_layer & 0x3; reg &= ~(0x7 << 4); reg |= 0x3 << 4; reg &= ~(0x1 << 8); reg |= (p->hier_bitrate_ctrl & 0x1) << 8; - MFC_WRITEL(reg, S5P_FIMV_E_NUM_T_LAYER); + MFC_WRITEL(reg, MFC_REG_E_NUM_T_LAYER); mfc_debug(3, "[HIERARCHICAL] hier_qp_enable %d, num_hier_layer %d, NUM_T_LAYER 0x%x\n", p_vp8->hier_qp_enable, p_vp8->num_hier_layer, reg); /* QP & Bitrate for each layer */ for (i = 0; i < 3; i++) { MFC_WRITEL(p_vp8->hier_qp_layer[i], - S5P_FIMV_E_HIERARCHICAL_QP_LAYER0 + i * 4); + MFC_REG_E_HIERARCHICAL_QP_LAYER0 + i * 4); /* If hier_bitrate_ctrl is set to 1, this is meaningless */ MFC_WRITEL(p_vp8->hier_bit_layer[i], - S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0 + i * 4); + MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER0 + i * 4); mfc_debug(3, "[HIERARCHICAL] layer[%d] QP: %#x, bitrate: %#x(FW ctrl: %d)\n", i, p_vp8->hier_qp_layer[i], p_vp8->hier_bit_layer[i], p->hier_bitrate_ctrl); @@ -856,76 +856,76 @@ void s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx) reg = 0; reg |= (p_vp8->vp8_filtersharpness & 0x7); reg |= (p_vp8->vp8_filterlevel & 0x3f) << 8; - MFC_WRITEL(reg, S5P_FIMV_E_VP8_FILTER_OPTION); + MFC_WRITEL(reg, MFC_REG_E_VP8_FILTER_OPTION); /* qp */ - reg = MFC_READL(S5P_FIMV_E_FIXED_PICTURE_QP); + reg = MFC_READL(MFC_REG_E_FIXED_PICTURE_QP); reg &= ~(0xFF << 24); reg |= ((p->config_qp & 0xFF) << 24); reg &= ~(0xFF << 8); reg |= ((p_vp8->rc_p_frame_qp & 0xFF) << 8); reg &= ~(0xFF); reg |= (p_vp8->rc_frame_qp & 0xFF); - MFC_WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP); + MFC_WRITEL(reg, MFC_REG_E_FIXED_PICTURE_QP); /* frame rate */ p->rc_frame_delta = FRAME_DELTA_DEFAULT; - reg = MFC_READL(S5P_FIMV_E_RC_FRAME_RATE); + reg = MFC_READL(MFC_REG_E_RC_FRAME_RATE); reg &= ~(0xFFFF << 16); reg |= (p->rc_framerate << 16); reg &= ~(0xFFFF); reg |= (p->rc_frame_delta & 0xFFFF); - MFC_WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE); + MFC_WRITEL(reg, MFC_REG_E_RC_FRAME_RATE); /* rate control config. */ - reg = MFC_READL(S5P_FIMV_E_RC_CONFIG); + reg = MFC_READL(MFC_REG_E_RC_CONFIG); /** frame QP */ reg &= ~(0xFF); reg |= (p_vp8->rc_frame_qp & 0xFF); - MFC_WRITEL(reg, S5P_FIMV_E_RC_CONFIG); + MFC_WRITEL(reg, MFC_REG_E_RC_CONFIG); /* max & min value of QP for I frame */ - reg = MFC_READL(S5P_FIMV_E_RC_QP_BOUND); + reg = MFC_READL(MFC_REG_E_RC_QP_BOUND); /** max I frame QP */ reg &= ~(0xFF << 8); reg |= ((p_vp8->rc_max_qp & 0xFF) << 8); /** min I frame QP */ reg &= ~(0xFF); reg |= (p_vp8->rc_min_qp & 0xFF); - MFC_WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND); + MFC_WRITEL(reg, MFC_REG_E_RC_QP_BOUND); /* max & min value of QP for P/B frame */ - reg = MFC_READL(S5P_FIMV_E_RC_QP_BOUND_PB); + reg = MFC_READL(MFC_REG_E_RC_QP_BOUND_PB); /** max P frame QP */ reg &= ~(0xFF << 8); reg |= ((p_vp8->rc_max_qp_p & 0xFF) << 8); /** min P frame QP */ reg &= ~(0xFF); reg |= p_vp8->rc_min_qp_p & 0xFF; - MFC_WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND_PB); + MFC_WRITEL(reg, MFC_REG_E_RC_QP_BOUND_PB); mfc_debug_leave(); } -void s5p_mfc_set_enc_params_vp9(struct s5p_mfc_ctx *ctx) +void mfc_set_enc_params_vp9(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_enc *enc = ctx->enc_priv; - struct s5p_mfc_enc_params *p = &enc->params; - struct s5p_mfc_vp9_enc_params *p_vp9 = &p->codec.vp9; + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + struct mfc_vp9_enc_params *p_vp9 = &p->codec.vp9; unsigned int reg = 0; int i; mfc_debug_enter(); - mfc_set_enc_params(ctx); + __mfc_set_enc_params(ctx); if (p_vp9->num_hier_layer & 0x3) { /* set gop_size without i_frm_ctrl mode */ - mfc_set_gop_size(ctx, 0); + __mfc_set_gop_size(ctx, 0); } else { /* set gop_size with i_frm_ctrl mode */ - mfc_set_gop_size(ctx, 1); + __mfc_set_gop_size(ctx, 1); } /* profile*/ @@ -937,25 +937,25 @@ void s5p_mfc_set_enc_params_vp9(struct s5p_mfc_ctx *ctx) reg |= (0x2 << 17); reg |= (0x2 << 20); } - MFC_WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE); + MFC_WRITEL(reg, MFC_REG_E_PICTURE_PROFILE); /* for only information about wrong setting */ if (ctx->is_422) { - if ((p_vp9->vp9_version != S5P_FIMV_E_PROFILE_VP9_PROFILE1) && - (p_vp9->vp9_version != S5P_FIMV_E_PROFILE_VP9_PROFILE3)) { + if ((p_vp9->vp9_version != MFC_REG_E_PROFILE_VP9_PROFILE1) && + (p_vp9->vp9_version != MFC_REG_E_PROFILE_VP9_PROFILE3)) { mfc_err_ctx("4:2:2 format is not matched with profile(%d)\n", p_vp9->vp9_version); } } if (ctx->is_10bit) { - if ((p_vp9->vp9_version != S5P_FIMV_E_PROFILE_VP9_PROFILE2) && - (p_vp9->vp9_version != S5P_FIMV_E_PROFILE_VP9_PROFILE3)) { + if ((p_vp9->vp9_version != MFC_REG_E_PROFILE_VP9_PROFILE2) && + (p_vp9->vp9_version != MFC_REG_E_PROFILE_VP9_PROFILE3)) { mfc_err_ctx("[10BIT] format is not matched with profile(%d)\n", p_vp9->vp9_version); } } - reg = MFC_READL(S5P_FIMV_E_VP9_OPTION); + reg = MFC_READL(MFC_REG_E_VP9_OPTION); /* if num_refs_for_p is 2, the performance falls by half */ reg &= ~(0x1); reg |= (p->num_refs_for_p - 1) & 0x1; @@ -969,87 +969,87 @@ void s5p_mfc_set_enc_params_vp9(struct s5p_mfc_ctx *ctx) /* Disable IVF header */ reg &= ~(0x1 << 12); reg |= ((p->ivf_header_disable & 0x1) << 12); - MFC_WRITEL(reg, S5P_FIMV_E_VP9_OPTION); + MFC_WRITEL(reg, MFC_REG_E_VP9_OPTION); - reg = MFC_READL(S5P_FIMV_E_VP9_GOLDEN_FRAME_OPTION); + reg = MFC_READL(MFC_REG_E_VP9_GOLDEN_FRAME_OPTION); reg &= ~(0x1); reg |= (p_vp9->vp9_goldenframesel & 0x1); reg &= ~(0xFFFF << 1); reg |= (p_vp9->vp9_gfrefreshperiod & 0xFFFF) << 1; - MFC_WRITEL(reg, S5P_FIMV_E_VP9_GOLDEN_FRAME_OPTION); + MFC_WRITEL(reg, MFC_REG_E_VP9_GOLDEN_FRAME_OPTION); /* Temporal SVC - layer number */ - reg = MFC_READL(S5P_FIMV_E_NUM_T_LAYER); + reg = MFC_READL(MFC_REG_E_NUM_T_LAYER); reg &= ~(0x7); reg |= p_vp9->num_hier_layer & 0x3; reg &= ~(0x7 << 4); reg |= 0x3 << 4; reg &= ~(0x1 << 8); reg |= (p->hier_bitrate_ctrl & 0x1) << 8; - MFC_WRITEL(reg, S5P_FIMV_E_NUM_T_LAYER); + MFC_WRITEL(reg, MFC_REG_E_NUM_T_LAYER); mfc_debug(3, "[HIERARCHICAL] hier_qp_enable %d, num_hier_layer %d, NUM_T_LAYER 0x%x\n", p_vp9->hier_qp_enable, p_vp9->num_hier_layer, reg); /* QP & Bitrate for each layer */ for (i = 0; i < 3; i++) { MFC_WRITEL(p_vp9->hier_qp_layer[i], - S5P_FIMV_E_HIERARCHICAL_QP_LAYER0 + i * 4); + MFC_REG_E_HIERARCHICAL_QP_LAYER0 + i * 4); /* If hier_bitrate_ctrl is set to 1, this is meaningless */ MFC_WRITEL(p_vp9->hier_bit_layer[i], - S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0 + i * 4); + MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER0 + i * 4); mfc_debug(3, "[HIERARCHICAL] layer[%d] QP: %#x, bitrate: %#x (FW ctrl: %d)\n", i, p_vp9->hier_qp_layer[i], p_vp9->hier_bit_layer[i], p->hier_bitrate_ctrl); } /* qp */ - reg = MFC_READL(S5P_FIMV_E_FIXED_PICTURE_QP); + reg = MFC_READL(MFC_REG_E_FIXED_PICTURE_QP); reg &= ~(0xFF << 24); reg |= ((p->config_qp & 0xFF) << 24); reg &= ~(0xFF << 8); reg |= ((p_vp9->rc_p_frame_qp & 0xFF) << 8); reg &= ~(0xFF); reg |= (p_vp9->rc_frame_qp & 0xFF); - MFC_WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP); + MFC_WRITEL(reg, MFC_REG_E_FIXED_PICTURE_QP); /* frame rate */ p->rc_frame_delta = FRAME_DELTA_DEFAULT; - reg = MFC_READL(S5P_FIMV_E_RC_FRAME_RATE); + reg = MFC_READL(MFC_REG_E_RC_FRAME_RATE); reg &= ~(0xFFFF << 16); reg |= (p->rc_framerate << 16); reg &= ~(0xFFFF); reg |= (p->rc_frame_delta & 0xFFFF); - MFC_WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE); + MFC_WRITEL(reg, MFC_REG_E_RC_FRAME_RATE); /* rate control config. */ - reg = MFC_READL(S5P_FIMV_E_RC_CONFIG); + reg = MFC_READL(MFC_REG_E_RC_CONFIG); /** frame QP */ reg &= ~(0xFF); reg |= (p_vp9->rc_frame_qp & 0xFF); - MFC_WRITEL(reg, S5P_FIMV_E_RC_CONFIG); + MFC_WRITEL(reg, MFC_REG_E_RC_CONFIG); /* max & min value of QP for I frame */ - reg = MFC_READL(S5P_FIMV_E_RC_QP_BOUND); + reg = MFC_READL(MFC_REG_E_RC_QP_BOUND); /** max I frame QP */ reg &= ~(0xFF << 8); reg |= ((p_vp9->rc_max_qp & 0xFF) << 8); /** min I frame QP */ reg &= ~(0xFF); reg |= (p_vp9->rc_min_qp & 0xFF); - MFC_WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND); + MFC_WRITEL(reg, MFC_REG_E_RC_QP_BOUND); /* max & min value of QP for P/B frame */ - reg = MFC_READL(S5P_FIMV_E_RC_QP_BOUND_PB); + reg = MFC_READL(MFC_REG_E_RC_QP_BOUND_PB); /** max P frame QP */ reg &= ~(0xFF << 8); reg |= ((p_vp9->rc_max_qp_p & 0xFF) << 8); /** min P frame QP */ reg &= ~(0xFF); reg |= p_vp9->rc_min_qp_p & 0xFF; - MFC_WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND_PB); + MFC_WRITEL(reg, MFC_REG_E_RC_QP_BOUND_PB); if (MFC_FEATURE_SUPPORT(dev, dev->pdata->color_aspect_enc) && p->check_color_range) { - reg = MFC_READL(S5P_FIMV_E_VIDEO_SIGNAL_TYPE); + reg = MFC_READL(MFC_REG_E_VIDEO_SIGNAL_TYPE); /* VIDEO_SIGNAL_TYPE_FLAG */ reg |= 0x1 << 31; /* COLOR_SPACE: VP9 uses colour_primaries interface for color space */ @@ -1058,35 +1058,35 @@ void s5p_mfc_set_enc_params_vp9(struct s5p_mfc_ctx *ctx) /* COLOR_RANGE */ reg &= ~(0x1 << 25); reg |= p->color_range << 25; - MFC_WRITEL(reg, S5P_FIMV_E_VIDEO_SIGNAL_TYPE); + MFC_WRITEL(reg, MFC_REG_E_VIDEO_SIGNAL_TYPE); mfc_debug(2, "[HDR] VP9 ENC Color aspect: range(%s), space(%d)\n", p->color_range ? "Full" : "Limited", p->colour_primaries); } else { - MFC_WRITEL(0, S5P_FIMV_E_VIDEO_SIGNAL_TYPE); + MFC_WRITEL(0, MFC_REG_E_VIDEO_SIGNAL_TYPE); } mfc_debug_leave(); } -void s5p_mfc_set_enc_params_hevc(struct s5p_mfc_ctx *ctx) +void mfc_set_enc_params_hevc(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_enc *enc = ctx->enc_priv; - struct s5p_mfc_enc_params *p = &enc->params; - struct s5p_mfc_hevc_enc_params *p_hevc = &p->codec.hevc; + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + struct mfc_hevc_enc_params *p_hevc = &p->codec.hevc; unsigned int reg = 0; int i; mfc_debug_enter(); - mfc_set_enc_params(ctx); + __mfc_set_enc_params(ctx); if (p_hevc->num_hier_layer & 0x7) { /* set gop_size without i_frm_ctrl mode */ - mfc_set_gop_size(ctx, 0); + __mfc_set_gop_size(ctx, 0); } else { /* set gop_size with i_frm_ctrl mode */ - mfc_set_gop_size(ctx, 1); + __mfc_set_gop_size(ctx, 1); } /* UHD encoding case */ @@ -1111,27 +1111,27 @@ void s5p_mfc_set_enc_params_hevc(struct s5p_mfc_ctx *ctx) reg |= (0x2 << 17); reg |= (0x2 << 20); } - MFC_WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE); + MFC_WRITEL(reg, MFC_REG_E_PICTURE_PROFILE); /* for only information about wrong setting */ if (ctx->is_422) { - if ((p_hevc->profile != S5P_FIMV_E_PROFILE_HEVC_MAIN_422_10_INTRA) && - (p_hevc->profile != S5P_FIMV_E_PROFILE_HEVC_MAIN_422_10)) { + if ((p_hevc->profile != MFC_REG_E_PROFILE_HEVC_MAIN_422_10_INTRA) && + (p_hevc->profile != MFC_REG_E_PROFILE_HEVC_MAIN_422_10)) { mfc_err_ctx("4:2:2 format is not matched with profile(%d)\n", p_hevc->profile); } } if (ctx->is_10bit) { - if ((p_hevc->profile != S5P_FIMV_E_PROFILE_HEVC_MAIN_422_10_INTRA) && - (p_hevc->profile != S5P_FIMV_E_PROFILE_HEVC_MAIN_10) && - (p_hevc->profile != S5P_FIMV_E_PROFILE_HEVC_MAIN_422_10)) { + if ((p_hevc->profile != MFC_REG_E_PROFILE_HEVC_MAIN_422_10_INTRA) && + (p_hevc->profile != MFC_REG_E_PROFILE_HEVC_MAIN_10) && + (p_hevc->profile != MFC_REG_E_PROFILE_HEVC_MAIN_422_10)) { mfc_err_ctx("[10BIT] format is not matched with profile(%d)\n", p_hevc->profile); } } /* max partition depth */ - reg = MFC_READL(S5P_FIMV_E_HEVC_OPTIONS); + reg = MFC_READL(MFC_REG_E_HEVC_OPTIONS); reg &= ~(0x3); reg |= (p_hevc->max_partition_depth & 0x1); /* if num_refs_for_p is 2, the performance falls by half */ @@ -1179,18 +1179,18 @@ void s5p_mfc_set_enc_params_hevc(struct s5p_mfc_ctx *ctx) reg |= ((p->weighted_enable & 0x1) << 28); /* 30bit is 32x32 transform. If it is enabled, the performance falls by half */ reg &= ~(0x1 << 30); - MFC_WRITEL(reg, S5P_FIMV_E_HEVC_OPTIONS); + MFC_WRITEL(reg, MFC_REG_E_HEVC_OPTIONS); /* refresh period */ - reg = MFC_READL(S5P_FIMV_E_HEVC_REFRESH_PERIOD); + reg = MFC_READL(MFC_REG_E_HEVC_REFRESH_PERIOD); reg &= ~(0xFFFF); reg |= (p_hevc->refreshperiod & 0xFFFF); - MFC_WRITEL(reg, S5P_FIMV_E_HEVC_REFRESH_PERIOD); + MFC_WRITEL(reg, MFC_REG_E_HEVC_REFRESH_PERIOD); /* loop filter setting */ - MFC_WRITEL(0, S5P_FIMV_E_HEVC_LF_BETA_OFFSET_DIV2); - MFC_WRITEL(0, S5P_FIMV_E_HEVC_LF_TC_OFFSET_DIV2); + MFC_WRITEL(0, MFC_REG_E_HEVC_LF_BETA_OFFSET_DIV2); + MFC_WRITEL(0, MFC_REG_E_HEVC_LF_TC_OFFSET_DIV2); if (!p_hevc->loopfilter_disable) { - MFC_WRITEL(p_hevc->lf_beta_offset_div2, S5P_FIMV_E_HEVC_LF_BETA_OFFSET_DIV2); - MFC_WRITEL(p_hevc->lf_tc_offset_div2, S5P_FIMV_E_HEVC_LF_TC_OFFSET_DIV2); + MFC_WRITEL(p_hevc->lf_beta_offset_div2, MFC_REG_E_HEVC_LF_BETA_OFFSET_DIV2); + MFC_WRITEL(p_hevc->lf_tc_offset_div2, MFC_REG_E_HEVC_LF_TC_OFFSET_DIV2); } /* long term reference */ if (p_hevc->enable_ltr) { @@ -1198,11 +1198,11 @@ void s5p_mfc_set_enc_params_hevc(struct s5p_mfc_ctx *ctx) reg |= (p_hevc->store_ref & 0x3); reg &= ~(0x3 << 2); reg |= (p_hevc->user_ref & 0x3) << 2; - MFC_WRITEL(reg, S5P_FIMV_E_HEVC_NAL_CONTROL); + MFC_WRITEL(reg, MFC_REG_E_HEVC_NAL_CONTROL); } /* Temporal SVC - qp type, layer number */ - reg = MFC_READL(S5P_FIMV_E_NUM_T_LAYER); + reg = MFC_READL(MFC_REG_E_NUM_T_LAYER); reg &= ~(0x1 << 3); reg |= (p_hevc->hier_qp_type & 0x1) << 3; reg &= ~(0x7); @@ -1217,7 +1217,7 @@ void s5p_mfc_set_enc_params_hevc(struct s5p_mfc_ctx *ctx) } reg &= ~(0x1 << 8); reg |= (p->hier_bitrate_ctrl & 0x1) << 8; - MFC_WRITEL(reg, S5P_FIMV_E_NUM_T_LAYER); + MFC_WRITEL(reg, MFC_REG_E_NUM_T_LAYER); mfc_debug(3, "[HIERARCHICAL] hier_qp_enable %d, enable_ltr %d, " "num_hier_layer %d, max_layer %d, hier_ref_type %d, NUM_T_LAYER 0x%x\n", p_hevc->hier_qp_enable, p_hevc->enable_ltr, p_hevc->num_hier_layer, @@ -1226,42 +1226,42 @@ void s5p_mfc_set_enc_params_hevc(struct s5p_mfc_ctx *ctx) /* QP & Bitrate for each layer */ for (i = 0; i < 7; i++) { MFC_WRITEL(p_hevc->hier_qp_layer[i], - S5P_FIMV_E_HIERARCHICAL_QP_LAYER0 + i * 4); + MFC_REG_E_HIERARCHICAL_QP_LAYER0 + i * 4); MFC_WRITEL(p_hevc->hier_bit_layer[i], - S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0 + i * 4); + MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER0 + i * 4); mfc_debug(3, "[HIERARCHICAL] layer[%d] QP: %#x, bitrate: %d(FW ctrl: %d)\n", i, p_hevc->hier_qp_layer[i], p_hevc->hier_bit_layer[i], p->hier_bitrate_ctrl); } /* rate control config. */ - reg = MFC_READL(S5P_FIMV_E_RC_CONFIG); + reg = MFC_READL(MFC_REG_E_RC_CONFIG); /** frame QP */ reg &= ~(0xFF); reg |= (p_hevc->rc_frame_qp & 0xFF); - MFC_WRITEL(reg, S5P_FIMV_E_RC_CONFIG); + MFC_WRITEL(reg, MFC_REG_E_RC_CONFIG); /* frame rate */ p->rc_frame_delta = FRAME_DELTA_DEFAULT; - reg = MFC_READL(S5P_FIMV_E_RC_FRAME_RATE); + reg = MFC_READL(MFC_REG_E_RC_FRAME_RATE); reg &= ~(0xFFFF << 16); reg |= (p->rc_framerate << 16); reg &= ~(0xFFFF); reg |= (p->rc_frame_delta & 0xFFFF); - MFC_WRITEL(reg, S5P_FIMV_E_RC_FRAME_RATE); + MFC_WRITEL(reg, MFC_REG_E_RC_FRAME_RATE); /* max & min value of QP for I frame */ - reg = MFC_READL(S5P_FIMV_E_RC_QP_BOUND); + reg = MFC_READL(MFC_REG_E_RC_QP_BOUND); /** max I frame QP */ reg &= ~(0xFF << 8); reg |= ((p_hevc->rc_max_qp & 0xFF) << 8); /** min I frame QP */ reg &= ~(0xFF); reg |= (p_hevc->rc_min_qp & 0xFF); - MFC_WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND); + MFC_WRITEL(reg, MFC_REG_E_RC_QP_BOUND); /* max & min value of QP for P/B frame */ - reg = MFC_READL(S5P_FIMV_E_RC_QP_BOUND_PB); + reg = MFC_READL(MFC_REG_E_RC_QP_BOUND_PB); /** max B frame QP */ reg &= ~(0xFF << 24); reg |= ((p_hevc->rc_max_qp_b & 0xFF) << 24); @@ -1274,9 +1274,9 @@ void s5p_mfc_set_enc_params_hevc(struct s5p_mfc_ctx *ctx) /** min P frame QP */ reg &= ~(0xFF); reg |= p_hevc->rc_min_qp_p & 0xFF; - MFC_WRITEL(reg, S5P_FIMV_E_RC_QP_BOUND_PB); + MFC_WRITEL(reg, MFC_REG_E_RC_QP_BOUND_PB); - reg = MFC_READL(S5P_FIMV_E_FIXED_PICTURE_QP); + reg = MFC_READL(MFC_REG_E_FIXED_PICTURE_QP); reg &= ~(0xFF << 24); reg |= ((p->config_qp & 0xFF) << 24); reg &= ~(0xFF << 16); @@ -1285,17 +1285,17 @@ void s5p_mfc_set_enc_params_hevc(struct s5p_mfc_ctx *ctx) reg |= ((p_hevc->rc_p_frame_qp & 0xFF) << 8); reg &= ~(0xFF); reg |= (p_hevc->rc_frame_qp & 0xFF); - MFC_WRITEL(reg, S5P_FIMV_E_FIXED_PICTURE_QP); + MFC_WRITEL(reg, MFC_REG_E_FIXED_PICTURE_QP); /* ROI enable: it must set on SEQ_START only for HEVC encoder */ - reg = MFC_READL(S5P_FIMV_E_RC_ROI_CTRL); + reg = MFC_READL(MFC_REG_E_RC_ROI_CTRL); reg &= ~(0x1); reg |= (p->roi_enable); - MFC_WRITEL(reg, S5P_FIMV_E_RC_ROI_CTRL); + MFC_WRITEL(reg, MFC_REG_E_RC_ROI_CTRL); mfc_debug(3, "[ROI] HEVC ROI enable\n"); if (MFC_FEATURE_SUPPORT(dev, dev->pdata->color_aspect_enc) && p->check_color_range) { - reg = MFC_READL(S5P_FIMV_E_VIDEO_SIGNAL_TYPE); + reg = MFC_READL(MFC_REG_E_VIDEO_SIGNAL_TYPE); /* VIDEO_SIGNAL_TYPE_FLAG */ reg |= 0x1 << 31; /* COLOR_RANGE */ @@ -1317,36 +1317,36 @@ void s5p_mfc_set_enc_params_hevc(struct s5p_mfc_ctx *ctx) } else { reg &= ~(0x1 << 24); } - MFC_WRITEL(reg, S5P_FIMV_E_VIDEO_SIGNAL_TYPE); + MFC_WRITEL(reg, MFC_REG_E_VIDEO_SIGNAL_TYPE); mfc_debug(2, "[HDR] HEVC ENC Color aspect: range(%s), pri(%d), trans(%d), mat(%d)\n", p->color_range ? "Full" : "Limited", p->colour_primaries, p->transfer_characteristics, p->matrix_coefficients); } else { - MFC_WRITEL(0, S5P_FIMV_E_VIDEO_SIGNAL_TYPE); + MFC_WRITEL(0, MFC_REG_E_VIDEO_SIGNAL_TYPE); } if (MFC_FEATURE_SUPPORT(dev, dev->pdata->static_info_enc) && p->static_info_enable && ctx->is_10bit) { - reg = MFC_READL(S5P_FIMV_E_HEVC_OPTIONS_2); + reg = MFC_READL(MFC_REG_E_HEVC_OPTIONS_2); /* HDR_STATIC_INFO_ENABLE */ reg |= p->static_info_enable; - MFC_WRITEL(reg, S5P_FIMV_E_HEVC_OPTIONS_2); + MFC_WRITEL(reg, MFC_REG_E_HEVC_OPTIONS_2); /* MAX_PIC_AVERAGE_LIGHT & MAX_CONTENT_LIGHT */ reg = p->max_pic_average_light; reg |= (p->max_content_light << 16); - MFC_WRITEL(reg, S5P_FIMV_E_CONTENT_LIGHT_LEVEL_INFO_SEI); + MFC_WRITEL(reg, MFC_REG_E_CONTENT_LIGHT_LEVEL_INFO_SEI); /* MAX_DISPLAY_LUMINANCE */ - MFC_WRITEL(p->max_display_luminance, S5P_FIMV_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_0); + MFC_WRITEL(p->max_display_luminance, MFC_REG_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_0); /* MIN DISPLAY LUMINANCE */ - MFC_WRITEL(p->min_display_luminance, S5P_FIMV_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_1); + MFC_WRITEL(p->min_display_luminance, MFC_REG_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_1); /* WHITE_POINT */ - MFC_WRITEL(p->white_point, S5P_FIMV_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_2); + MFC_WRITEL(p->white_point, MFC_REG_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_2); /* DISPLAY PRIMARIES_0 */ - MFC_WRITEL(p->display_primaries_0, S5P_FIMV_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_3); + MFC_WRITEL(p->display_primaries_0, MFC_REG_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_3); /* DISPLAY PRIMARIES_1 */ - MFC_WRITEL(p->display_primaries_1, S5P_FIMV_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_4); + MFC_WRITEL(p->display_primaries_1, MFC_REG_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_4); /* DISPLAY PRIMARIES_2 */ - MFC_WRITEL(p->display_primaries_2, S5P_FIMV_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_5); + MFC_WRITEL(p->display_primaries_2, MFC_REG_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_5); mfc_debug(2, "[HDR] HEVC ENC static info: enable(%d), max_pic(0x%x), max_content(0x%x)\n", p->static_info_enable, p->max_pic_average_light, p->max_content_light); @@ -1355,28 +1355,28 @@ void s5p_mfc_set_enc_params_hevc(struct s5p_mfc_ctx *ctx) mfc_debug(2, "[HDR] disp_pri_0(0x%x), disp_pri_1(0x%x), disp_pri_2(0x%x)\n", p->display_primaries_0, p->display_primaries_1, p->display_primaries_2); } else { - reg = MFC_READL(S5P_FIMV_E_HEVC_OPTIONS_2); + reg = MFC_READL(MFC_REG_E_HEVC_OPTIONS_2); /* HDR_STATIC_INFO_ENABLE */ reg &= ~(0x1); - MFC_WRITEL(reg, S5P_FIMV_E_HEVC_OPTIONS_2); + MFC_WRITEL(reg, MFC_REG_E_HEVC_OPTIONS_2); } mfc_debug_leave(); } -void s5p_mfc_set_enc_params_bpg(struct s5p_mfc_ctx *ctx) +void mfc_set_enc_params_bpg(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_enc *enc = ctx->enc_priv; - struct s5p_mfc_enc_params *p = &enc->params; - struct s5p_mfc_bpg_enc_params *p_bpg = &p->codec.bpg; + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + struct mfc_bpg_enc_params *p_bpg = &p->codec.bpg; unsigned int reg = 0; - mfc_set_enc_params(ctx); + __mfc_set_enc_params(ctx); /* extension tag */ reg = p_bpg->thumb_size + p_bpg->exif_size; - MFC_WRITEL(reg, S5P_FIMV_E_BPG_EXTENSION_DATA_SIZE); + MFC_WRITEL(reg, MFC_REG_E_BPG_EXTENSION_DATA_SIZE); mfc_debug(3, "main image extension size %d (thumbnail: %d, exif: %d)\n", reg, p_bpg->thumb_size, p_bpg->exif_size); @@ -1393,5 +1393,5 @@ void s5p_mfc_set_enc_params_bpg(struct s5p_mfc_ctx *ctx) if (ctx->is_422) reg |= 0x1; } - MFC_WRITEL(reg, S5P_FIMV_E_PICTURE_PROFILE); + MFC_WRITEL(reg, MFC_REG_E_PICTURE_PROFILE); } diff --git a/drivers/media/platform/exynos/mfc/mfc_enc_param.h b/drivers/media/platform/exynos/mfc/mfc_enc_param.h index 3e7fcf4d6f06..63fa5c896cfa 100644 --- a/drivers/media/platform/exynos/mfc/mfc_enc_param.h +++ b/drivers/media/platform/exynos/mfc/mfc_enc_param.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_enc_param.h + * drivers/media/platform/exynos/mfc/mfc_enc_param.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -15,13 +15,13 @@ #include "mfc_common.h" -void s5p_mfc_set_slice_mode(struct s5p_mfc_ctx *ctx); -void s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx); -void s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx); -void s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx); -void s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx); -void s5p_mfc_set_enc_params_vp9(struct s5p_mfc_ctx *ctx); -void s5p_mfc_set_enc_params_hevc(struct s5p_mfc_ctx *ctx); -void s5p_mfc_set_enc_params_bpg(struct s5p_mfc_ctx *ctx); +void mfc_set_slice_mode(struct mfc_ctx *ctx); +void mfc_set_enc_params_h264(struct mfc_ctx *ctx); +void mfc_set_enc_params_mpeg4(struct mfc_ctx *ctx); +void mfc_set_enc_params_h263(struct mfc_ctx *ctx); +void mfc_set_enc_params_vp8(struct mfc_ctx *ctx); +void mfc_set_enc_params_vp9(struct mfc_ctx *ctx); +void mfc_set_enc_params_hevc(struct mfc_ctx *ctx); +void mfc_set_enc_params_bpg(struct mfc_ctx *ctx); #endif /* __MFC_ENC_PARAM_H */ diff --git a/drivers/media/platform/exynos/mfc/mfc_enc_vb2_ops.c b/drivers/media/platform/exynos/mfc/mfc_enc_vb2_ops.c index aade99ec62d0..6d9ef8f24ca9 100644 --- a/drivers/media/platform/exynos/mfc/mfc_enc_vb2_ops.c +++ b/drivers/media/platform/exynos/mfc/mfc_enc_vb2_ops.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_enc_vb2_ops.c + * drivers/media/platform/exynos/mfc/mfc_enc_vb2_ops.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -23,14 +23,14 @@ #include "mfc_buf.h" #include "mfc_mem.h" -static int s5p_mfc_enc_queue_setup(struct vb2_queue *vq, +static int mfc_enc_queue_setup(struct vb2_queue *vq, unsigned int *buf_count, unsigned int *plane_count, unsigned int psize[], struct device *alloc_devs[]) { - struct s5p_mfc_dev *dev; - struct s5p_mfc_ctx *ctx = vq->drv_priv; - struct s5p_mfc_enc *enc = ctx->enc_priv; - struct s5p_mfc_raw_info *raw; + struct mfc_dev *dev; + struct mfc_ctx *ctx = vq->drv_priv; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_raw_info *raw; int i; mfc_debug_enter(); @@ -104,32 +104,32 @@ static int s5p_mfc_enc_queue_setup(struct vb2_queue *vq, return 0; } -static void s5p_mfc_enc_unlock(struct vb2_queue *q) +static void mfc_enc_unlock(struct vb2_queue *q) { - struct s5p_mfc_ctx *ctx = q->drv_priv; - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_ctx *ctx = q->drv_priv; + struct mfc_dev *dev = ctx->dev; mutex_unlock(&dev->mfc_mutex); } -static void s5p_mfc_enc_lock(struct vb2_queue *q) +static void mfc_enc_lock(struct vb2_queue *q) { - struct s5p_mfc_ctx *ctx = q->drv_priv; - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_ctx *ctx = q->drv_priv; + struct mfc_dev *dev = ctx->dev; mutex_lock(&dev->mfc_mutex); } -static int s5p_mfc_enc_buf_init(struct vb2_buffer *vb) +static int mfc_enc_buf_init(struct vb2_buffer *vb) { struct vb2_queue *vq = vb->vb2_queue; - struct s5p_mfc_ctx *ctx = vq->drv_priv; + struct mfc_ctx *ctx = vq->drv_priv; int ret; mfc_debug_enter(); if (vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { - ret = s5p_mfc_check_vb_with_fmt(ctx->dst_fmt, vb); + ret = mfc_check_vb_with_fmt(ctx->dst_fmt, vb); if (ret < 0) return ret; @@ -138,7 +138,7 @@ static int s5p_mfc_enc_buf_init(struct vb2_buffer *vb) mfc_err_ctx("failed in init_buf_ctrls\n"); } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { - ret = s5p_mfc_check_vb_with_fmt(ctx->src_fmt, vb); + ret = mfc_check_vb_with_fmt(ctx->src_fmt, vb); if (ret < 0) return ret; @@ -155,14 +155,14 @@ static int s5p_mfc_enc_buf_init(struct vb2_buffer *vb) return 0; } -static int s5p_mfc_enc_buf_prepare(struct vb2_buffer *vb) +static int mfc_enc_buf_prepare(struct vb2_buffer *vb) { struct vb2_queue *vq = vb->vb2_queue; - struct s5p_mfc_ctx *ctx = vq->drv_priv; - struct s5p_mfc_enc *enc = ctx->enc_priv; - struct s5p_mfc_raw_info *raw; + struct mfc_ctx *ctx = vq->drv_priv; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_raw_info *raw; unsigned int index = vb->index; - struct s5p_mfc_buf *buf = vb_to_mfc_buf(vb); + struct mfc_buf *buf = vb_to_mfc_buf(vb); struct dma_buf *bufcon_dmabuf[MFC_MAX_PLANES]; int i, mem_get_count = 0; size_t buf_size; @@ -180,7 +180,7 @@ static int s5p_mfc_enc_buf_prepare(struct vb2_buffer *vb) return -EINVAL; } - buf->addr[0][0] = s5p_mfc_mem_get_daddr_vb(vb, 0); + buf->addr[0][0] = mfc_mem_get_daddr_vb(vb, 0); } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { raw = &ctx->raw_buf; if (ctx->src_fmt->mem_planes == 1) { @@ -213,7 +213,7 @@ static int s5p_mfc_enc_buf_prepare(struct vb2_buffer *vb) } mem_get_count++; - buf->num_bufs_in_batch = s5p_mfc_bufcon_get_buf_count(bufcon_dmabuf[i]); + buf->num_bufs_in_batch = mfc_bufcon_get_buf_count(bufcon_dmabuf[i]); mfc_debug(3, "[BUFCON] num bufs in batch: %d\n", buf->num_bufs_in_batch); if (buf->num_bufs_in_batch == 0) { mfc_err_ctx("[BUFCON] bufs count couldn't be zero\n"); @@ -229,7 +229,7 @@ static int s5p_mfc_enc_buf_prepare(struct vb2_buffer *vb) } if (buf->num_bufs_in_batch > 0) { - if (s5p_mfc_bufcon_get_daddr(ctx, buf, bufcon_dmabuf[i], i)) { + if (mfc_bufcon_get_daddr(ctx, buf, bufcon_dmabuf[i], i)) { mfc_err_ctx("[BUFCON] failed to get daddr[%d] in buffer container\n", i); goto err_mem_put; } @@ -242,7 +242,7 @@ static int s5p_mfc_enc_buf_prepare(struct vb2_buffer *vb) dma_addr_t start_raw; dma_buf_put(bufcon_dmabuf[i]); - start_raw = s5p_mfc_mem_get_daddr_vb(vb, 0); + start_raw = mfc_mem_get_daddr_vb(vb, 0); if (start_raw == 0) { mfc_err_ctx("Plane mem not allocated\n"); return -ENOMEM; @@ -261,7 +261,7 @@ static int s5p_mfc_enc_buf_prepare(struct vb2_buffer *vb) ctx->img_width, ctx->img_height); } else { - buf->addr[0][i] = s5p_mfc_mem_get_daddr_vb(vb, i); + buf->addr[0][i] = mfc_mem_get_daddr_vb(vb, i); } } } @@ -283,10 +283,10 @@ err_mem_put: return -ENOMEM; } -static void s5p_mfc_enc_buf_finish(struct vb2_buffer *vb) +static void mfc_enc_buf_finish(struct vb2_buffer *vb) { struct vb2_queue *vq = vb->vb2_queue; - struct s5p_mfc_ctx *ctx = vq->drv_priv; + struct mfc_ctx *ctx = vq->drv_priv; unsigned int index = vb->index; @@ -299,10 +299,10 @@ static void s5p_mfc_enc_buf_finish(struct vb2_buffer *vb) } } -static void s5p_mfc_enc_buf_cleanup(struct vb2_buffer *vb) +static void mfc_enc_buf_cleanup(struct vb2_buffer *vb) { struct vb2_queue *vq = vb->vb2_queue; - struct s5p_mfc_ctx *ctx = vq->drv_priv; + struct mfc_ctx *ctx = vq->drv_priv; unsigned int index = vb->index; mfc_debug_enter(); @@ -316,31 +316,31 @@ static void s5p_mfc_enc_buf_cleanup(struct vb2_buffer *vb) MFC_CTRL_TYPE_SRC, index) < 0) mfc_err_ctx("failed in cleanup_buf_ctrls\n"); } else { - mfc_err_ctx("s5p_mfc_enc_buf_cleanup: unknown queue type\n"); + mfc_err_ctx("mfc_enc_buf_cleanup: unknown queue type\n"); } mfc_debug_leave(); } -static int s5p_mfc_enc_start_streaming(struct vb2_queue *q, unsigned int count) +static int mfc_enc_start_streaming(struct vb2_queue *q, unsigned int count) { - struct s5p_mfc_ctx *ctx = q->drv_priv; - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_ctx *ctx = q->drv_priv; + struct mfc_dev *dev = ctx->dev; /* If context is ready then dev = work->data;schedule it to run */ - if (s5p_mfc_enc_ctx_ready(ctx)) { - s5p_mfc_set_bit(ctx->num, &dev->work_bits); + if (mfc_enc_ctx_ready(ctx)) { + mfc_set_bit(ctx->num, &dev->work_bits); } - s5p_mfc_try_run(dev); + mfc_try_run(dev); return 0; } -static void s5p_mfc_enc_stop_streaming(struct vb2_queue *q) +static void mfc_enc_stop_streaming(struct vb2_queue *q) { - struct s5p_mfc_ctx *ctx = q->drv_priv; - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_ctx *ctx = q->drv_priv; + struct mfc_dev *dev = ctx->dev; int index = 0; int aborted = 0; int ret = 0; @@ -351,21 +351,21 @@ static void s5p_mfc_enc_stop_streaming(struct vb2_queue *q) /* If a H/W operation is in progress, wait for it complete */ if (need_to_wait_nal_abort(ctx)) { - if (s5p_mfc_wait_for_done_ctx(ctx, S5P_FIMV_R2H_CMD_NAL_ABORT_RET)) { + if (mfc_wait_for_done_ctx(ctx, MFC_REG_R2H_CMD_NAL_ABORT_RET)) { mfc_err_ctx("time out during nal abort\n"); - s5p_mfc_cleanup_work_bit_and_try_run(ctx); + mfc_cleanup_work_bit_and_try_run(ctx); } aborted = 1; } MFC_TRACE_CTX_HWLOCK("**ENC streamoff(type:%d)\n", q->type); - ret = s5p_mfc_get_hwlock_ctx(ctx); + ret = mfc_get_hwlock_ctx(ctx); if (ret < 0) { mfc_err_ctx("Failed to get hwlock\n"); return; } if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { - s5p_mfc_cleanup_enc_dst_queue(ctx); + mfc_cleanup_enc_dst_queue(ctx); while (index < MFC_MAX_BUFFERS) { index = find_next_bit(&ctx->dst_ctrls_avail, @@ -376,16 +376,16 @@ static void s5p_mfc_enc_stop_streaming(struct vb2_queue *q) } } else if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { if (ctx->state == MFCINST_RUNNING) { - s5p_mfc_change_state(ctx, MFCINST_FINISHING); - s5p_mfc_set_bit(ctx->num, &dev->work_bits); + mfc_change_state(ctx, MFCINST_FINISHING); + mfc_set_bit(ctx->num, &dev->work_bits); - while (s5p_mfc_get_buf(&ctx->buf_queue_lock, &ctx->dst_buf_queue, MFC_BUF_NO_TOUCH_USED)) { - ret = s5p_mfc_just_run(dev, ctx->num); + while (mfc_get_buf(&ctx->buf_queue_lock, &ctx->dst_buf_queue, MFC_BUF_NO_TOUCH_USED)) { + ret = mfc_just_run(dev, ctx->num); if (ret) { mfc_err_ctx("Failed to run MFC\n"); break; } - if (s5p_mfc_wait_for_done_ctx(ctx, S5P_FIMV_R2H_CMD_FRAME_DONE_RET)) { + if (mfc_wait_for_done_ctx(ctx, MFC_REG_R2H_CMD_FRAME_DONE_RET)) { mfc_err_ctx("Waiting for LAST_SEQ timed out\n"); break; } @@ -396,9 +396,9 @@ static void s5p_mfc_enc_stop_streaming(struct vb2_queue *q) } } - s5p_mfc_move_all_bufs(&ctx->buf_queue_lock, &ctx->src_buf_queue, + mfc_move_all_bufs(&ctx->buf_queue_lock, &ctx->src_buf_queue, &ctx->ref_buf_queue, MFC_QUEUE_ADD_BOTTOM); - s5p_mfc_cleanup_enc_src_queue(ctx); + mfc_cleanup_enc_src_queue(ctx); while (index < MFC_MAX_BUFFERS) { index = find_next_bit(&ctx->src_ctrls_avail, @@ -410,23 +410,23 @@ static void s5p_mfc_enc_stop_streaming(struct vb2_queue *q) } if (aborted || ctx->state == MFCINST_FINISHING) - s5p_mfc_change_state(ctx, MFCINST_RUNNING); + mfc_change_state(ctx, MFCINST_RUNNING); mfc_debug(2, "buffer cleanup is done in stop_streaming, type : %d\n", q->type); - s5p_mfc_clear_bit(ctx->num, &dev->work_bits); - s5p_mfc_release_hwlock_ctx(ctx); + mfc_clear_bit(ctx->num, &dev->work_bits); + mfc_release_hwlock_ctx(ctx); - if (s5p_mfc_is_work_to_do(dev)) + if (mfc_is_work_to_do(dev)) queue_work(dev->butler_wq, &dev->butler_work); } -static void s5p_mfc_enc_buf_queue(struct vb2_buffer *vb) +static void mfc_enc_buf_queue(struct vb2_buffer *vb) { struct vb2_queue *vq = vb->vb2_queue; - struct s5p_mfc_ctx *ctx = vq->drv_priv; - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_buf *buf = vb_to_mfc_buf(vb); + struct mfc_ctx *ctx = vq->drv_priv; + struct mfc_dev *dev = ctx->dev; + struct mfc_buf *buf = vb_to_mfc_buf(vb); int i; mfc_debug_enter(); @@ -439,40 +439,40 @@ static void s5p_mfc_enc_buf_queue(struct vb2_buffer *vb) ctx->num, vb->index, buf->addr[0][0]); /* Mark destination as available for use by MFC */ - s5p_mfc_add_tail_buf(&ctx->buf_queue_lock, &ctx->dst_buf_queue, buf); + mfc_add_tail_buf(&ctx->buf_queue_lock, &ctx->dst_buf_queue, buf); } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { for (i = 0; i < ctx->src_fmt->mem_planes; i++) mfc_debug(2, "[BUFINFO] ctx[%d] add src index: %d, addr[%d]: 0x%08llx\n", ctx->num, vb->index, i, buf->addr[0][i]); - s5p_mfc_add_tail_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, buf); + mfc_add_tail_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, buf); if (debug_ts == 1) mfc_info_ctx("[TS] framerate: %ld, timestamp: %lld\n", ctx->framerate, buf->vb.vb2_buf.timestamp); - s5p_mfc_qos_update_last_framerate(ctx, buf->vb.vb2_buf.timestamp); - s5p_mfc_qos_update_framerate(ctx); + mfc_qos_update_last_framerate(ctx, buf->vb.vb2_buf.timestamp); + mfc_qos_update_framerate(ctx); } else { mfc_err_ctx("unsupported buffer type (%d)\n", vq->type); } - if (s5p_mfc_enc_ctx_ready(ctx)) { - s5p_mfc_set_bit(ctx->num, &dev->work_bits); + if (mfc_enc_ctx_ready(ctx)) { + mfc_set_bit(ctx->num, &dev->work_bits); } - s5p_mfc_try_run(dev); + mfc_try_run(dev); mfc_debug_leave(); } -struct vb2_ops s5p_mfc_enc_qops = { - .queue_setup = s5p_mfc_enc_queue_setup, - .wait_prepare = s5p_mfc_enc_unlock, - .wait_finish = s5p_mfc_enc_lock, - .buf_init = s5p_mfc_enc_buf_init, - .buf_prepare = s5p_mfc_enc_buf_prepare, - .buf_finish = s5p_mfc_enc_buf_finish, - .buf_cleanup = s5p_mfc_enc_buf_cleanup, - .start_streaming = s5p_mfc_enc_start_streaming, - .stop_streaming = s5p_mfc_enc_stop_streaming, - .buf_queue = s5p_mfc_enc_buf_queue, +struct vb2_ops mfc_enc_qops = { + .queue_setup = mfc_enc_queue_setup, + .wait_prepare = mfc_enc_unlock, + .wait_finish = mfc_enc_lock, + .buf_init = mfc_enc_buf_init, + .buf_prepare = mfc_enc_buf_prepare, + .buf_finish = mfc_enc_buf_finish, + .buf_cleanup = mfc_enc_buf_cleanup, + .start_streaming = mfc_enc_start_streaming, + .stop_streaming = mfc_enc_stop_streaming, + .buf_queue = mfc_enc_buf_queue, }; diff --git a/drivers/media/platform/exynos/mfc/mfc_hwfc_internal.h b/drivers/media/platform/exynos/mfc/mfc_hwfc_internal.h index cb4a6bfe931d..e89c71d9a2d0 100644 --- a/drivers/media/platform/exynos/mfc/mfc_hwfc_internal.h +++ b/drivers/media/platform/exynos/mfc/mfc_hwfc_internal.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_hwfc_internal.h + * drivers/media/platform/exynos/mfc/mfc_hwfc_internal.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -24,7 +24,7 @@ * 2 4 6 8 0 * |B......BG......GR......RA......A| */ -struct s5p_mfc_fmt enc_hwfc_formats[] = { +struct mfc_fmt enc_hwfc_formats[] = { { .name = "4:2:0 2 Planes Y/CbCr single", .fourcc = V4L2_PIX_FMT_NV12N, @@ -36,7 +36,7 @@ struct s5p_mfc_fmt enc_hwfc_formats[] = { { .name = "H264 Encoded Stream", .fourcc = V4L2_PIX_FMT_H264, - .codec_mode = S5P_FIMV_CODEC_H264_ENC, + .codec_mode = MFC_REG_CODEC_H264_ENC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, @@ -44,7 +44,7 @@ struct s5p_mfc_fmt enc_hwfc_formats[] = { { .name = "HEVC Encoded Stream", .fourcc = V4L2_PIX_FMT_HEVC, - .codec_mode = S5P_FIMV_CODEC_HEVC_ENC, + .codec_mode = MFC_REG_CODEC_HEVC_ENC, .type = MFC_FMT_STREAM, .num_planes = 1, .mem_planes = 1, diff --git a/drivers/media/platform/exynos/mfc/mfc_hwlock.c b/drivers/media/platform/exynos/mfc/mfc_hwlock.c index 79cfb44f9e13..0821b1834bab 100644 --- a/drivers/media/platform/exynos/mfc/mfc_hwlock.c +++ b/drivers/media/platform/exynos/mfc/mfc_hwlock.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_hwlock.c + * drivers/media/platform/exynos/mfc/mfc_hwlock.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -26,14 +26,14 @@ #include "mfc_queue.h" #include "mfc_utils.h" -static inline void mfc_print_hwlock(struct s5p_mfc_dev *dev) +static inline void __mfc_print_hwlock(struct mfc_dev *dev) { mfc_debug(2, "dev.hwlock.dev = 0x%lx, bits = 0x%lx, owned_by_irq = %d, wl_count = %d, transfer_owner = %d\n", dev->hwlock.dev, dev->hwlock.bits, dev->hwlock.owned_by_irq, dev->hwlock.wl_count, dev->hwlock.transfer_owner); } -void s5p_mfc_init_hwlock(struct s5p_mfc_dev *dev) +void mfc_init_hwlock(struct mfc_dev *dev) { unsigned long flags; @@ -55,9 +55,9 @@ void s5p_mfc_init_hwlock(struct s5p_mfc_dev *dev) spin_unlock_irqrestore(&dev->hwlock.lock, flags); } -static int mfc_remove_listable_wq_dev(struct s5p_mfc_dev *dev) +static int __mfc_remove_listable_wq_dev(struct mfc_dev *dev) { - struct s5p_mfc_listable_wq *listable_wq; + struct mfc_listable_wq *listable_wq; unsigned long flags; int ret = -1; @@ -67,7 +67,7 @@ static int mfc_remove_listable_wq_dev(struct s5p_mfc_dev *dev) } spin_lock_irqsave(&dev->hwlock.lock, flags); - mfc_print_hwlock(dev); + __mfc_print_hwlock(dev); list_for_each_entry(listable_wq, &dev->hwlock.waiting_list, list) { if (!listable_wq->dev) @@ -82,16 +82,16 @@ static int mfc_remove_listable_wq_dev(struct s5p_mfc_dev *dev) break; } - mfc_print_hwlock(dev); + __mfc_print_hwlock(dev); spin_unlock_irqrestore(&dev->hwlock.lock, flags); return ret; } -static int mfc_remove_listable_wq_ctx(struct s5p_mfc_ctx *curr_ctx) +static int __mfc_remove_listable_wq_ctx(struct mfc_ctx *curr_ctx) { - struct s5p_mfc_dev *dev; - struct s5p_mfc_listable_wq *listable_wq; + struct mfc_dev *dev; + struct mfc_listable_wq *listable_wq; unsigned long flags; int ret = -1; @@ -107,7 +107,7 @@ static int mfc_remove_listable_wq_ctx(struct s5p_mfc_ctx *curr_ctx) } spin_lock_irqsave(&dev->hwlock.lock, flags); - mfc_print_hwlock(dev); + __mfc_print_hwlock(dev); list_for_each_entry(listable_wq, &dev->hwlock.waiting_list, list) { if (!listable_wq->ctx) @@ -123,7 +123,7 @@ static int mfc_remove_listable_wq_ctx(struct s5p_mfc_ctx *curr_ctx) } } - mfc_print_hwlock(dev); + __mfc_print_hwlock(dev); spin_unlock_irqrestore(&dev->hwlock.lock, flags); return ret; @@ -134,7 +134,7 @@ static int mfc_remove_listable_wq_ctx(struct s5p_mfc_ctx *curr_ctx) * 0: succeeded to get hwlock * -EIO: failed to get hwlock (time out) */ -int s5p_mfc_get_hwlock_dev(struct s5p_mfc_dev *dev) +int mfc_get_hwlock_dev(struct mfc_dev *dev) { int ret = 0; unsigned long flags; @@ -147,7 +147,7 @@ int s5p_mfc_get_hwlock_dev(struct s5p_mfc_dev *dev) mutex_lock(&dev->hwlock_wq.wait_mutex); spin_lock_irqsave(&dev->hwlock.lock, flags); - mfc_print_hwlock(dev); + __mfc_print_hwlock(dev); if (dev->shutdown) { mfc_info_dev("Couldn't lock HW. Shutdown was called\n"); @@ -174,15 +174,15 @@ int s5p_mfc_get_hwlock_dev(struct s5p_mfc_dev *dev) dev->hwlock.wl_count, dev->hwlock.transfer_owner); dev->hwlock.transfer_owner = 0; - mfc_remove_listable_wq_dev(dev); + __mfc_remove_listable_wq_dev(dev); if (ret == 0) { mfc_err_dev("Woken up but timed out\n"); - mfc_print_hwlock(dev); + __mfc_print_hwlock(dev); mutex_unlock(&dev->hwlock_wq.wait_mutex); return -EIO; } else { mfc_debug(2, "Woken up and got hwlock\n"); - mfc_print_hwlock(dev); + __mfc_print_hwlock(dev); mutex_unlock(&dev->hwlock_wq.wait_mutex); } } else { @@ -195,14 +195,14 @@ int s5p_mfc_get_hwlock_dev(struct s5p_mfc_dev *dev) dev->hwlock.dev, dev->hwlock.bits, dev->hwlock.owned_by_irq, dev->hwlock.wl_count, dev->hwlock.transfer_owner); - mfc_print_hwlock(dev); + __mfc_print_hwlock(dev); spin_unlock_irqrestore(&dev->hwlock.lock, flags); mutex_unlock(&dev->hwlock_wq.wait_mutex); } /* Stop NAL-Q after getting hwlock */ if (dev->nal_q_handle) - s5p_mfc_nal_q_stop_if_started(dev); + mfc_nal_q_stop_if_started(dev); return 0; } @@ -212,10 +212,10 @@ int s5p_mfc_get_hwlock_dev(struct s5p_mfc_dev *dev) * 0: succeeded to get hwlock * -EIO: failed to get hwlock (time out) */ -int s5p_mfc_get_hwlock_ctx(struct s5p_mfc_ctx *curr_ctx) +int mfc_get_hwlock_ctx(struct mfc_ctx *curr_ctx) { - struct s5p_mfc_dev *dev; - struct s5p_mfc_ctx *ctx = curr_ctx; + struct mfc_dev *dev; + struct mfc_ctx *ctx = curr_ctx; int ret = 0; unsigned long flags; @@ -233,7 +233,7 @@ int s5p_mfc_get_hwlock_ctx(struct s5p_mfc_ctx *curr_ctx) mutex_lock(&curr_ctx->hwlock_wq.wait_mutex); spin_lock_irqsave(&dev->hwlock.lock, flags); - mfc_print_hwlock(dev); + __mfc_print_hwlock(dev); if (dev->shutdown) { mfc_info_dev("Couldn't lock HW. Shutdown was called\n"); @@ -265,15 +265,15 @@ int s5p_mfc_get_hwlock_ctx(struct s5p_mfc_ctx *curr_ctx) dev->hwlock.wl_count, dev->hwlock.transfer_owner); dev->hwlock.transfer_owner = 0; - mfc_remove_listable_wq_ctx(curr_ctx); + __mfc_remove_listable_wq_ctx(curr_ctx); if (ret == 0) { mfc_err_dev("Woken up but timed out\n"); - mfc_print_hwlock(dev); + __mfc_print_hwlock(dev); mutex_unlock(&curr_ctx->hwlock_wq.wait_mutex); return -EIO; } else { mfc_debug(2, "Woken up and got hwlock\n"); - mfc_print_hwlock(dev); + __mfc_print_hwlock(dev); mutex_unlock(&curr_ctx->hwlock_wq.wait_mutex); } } else { @@ -287,14 +287,14 @@ int s5p_mfc_get_hwlock_ctx(struct s5p_mfc_ctx *curr_ctx) dev->hwlock.dev, dev->hwlock.bits, dev->hwlock.owned_by_irq, dev->hwlock.wl_count, dev->hwlock.transfer_owner); - mfc_print_hwlock(dev); + __mfc_print_hwlock(dev); spin_unlock_irqrestore(&dev->hwlock.lock, flags); mutex_unlock(&curr_ctx->hwlock_wq.wait_mutex); } /* Stop NAL-Q after getting hwlock */ if (dev->nal_q_handle) - s5p_mfc_nal_q_stop_if_started(dev); + mfc_nal_q_stop_if_started(dev); return 0; } @@ -305,9 +305,9 @@ int s5p_mfc_get_hwlock_ctx(struct s5p_mfc_ctx *curr_ctx) * 1: succeeded to release hwlock, hwlock is captured by another module * -1: error since device is waiting again. */ -int s5p_mfc_release_hwlock_dev(struct s5p_mfc_dev *dev) +int mfc_release_hwlock_dev(struct mfc_dev *dev) { - struct s5p_mfc_listable_wq *listable_wq; + struct mfc_listable_wq *listable_wq; unsigned long flags; int ret = -1; @@ -317,7 +317,7 @@ int s5p_mfc_release_hwlock_dev(struct s5p_mfc_dev *dev) } spin_lock_irqsave(&dev->hwlock.lock, flags); - mfc_print_hwlock(dev); + __mfc_print_hwlock(dev); dev->hwlock.dev = 0; dev->hwlock.owned_by_irq = 0; @@ -330,7 +330,7 @@ int s5p_mfc_release_hwlock_dev(struct s5p_mfc_dev *dev) ret = 0; } else { mfc_debug(2, "There is a waiting module\n"); - listable_wq = list_entry(dev->hwlock.waiting_list.next, struct s5p_mfc_listable_wq, list); + listable_wq = list_entry(dev->hwlock.waiting_list.next, struct mfc_listable_wq, list); list_del(&listable_wq->list); dev->hwlock.wl_count--; @@ -353,7 +353,7 @@ int s5p_mfc_release_hwlock_dev(struct s5p_mfc_dev *dev) ret = 1; } - mfc_print_hwlock(dev); + __mfc_print_hwlock(dev); spin_unlock_irqrestore(&dev->hwlock.lock, flags); return ret; } @@ -365,11 +365,11 @@ int s5p_mfc_release_hwlock_dev(struct s5p_mfc_dev *dev) * 0: succeeded to release hwlock * 1: succeeded to release hwlock, hwlock is captured by another module */ -static int mfc_release_hwlock_ctx_protected(struct s5p_mfc_ctx *curr_ctx) +static int __mfc_release_hwlock_ctx_protected(struct mfc_ctx *curr_ctx) { - struct s5p_mfc_dev *dev; - struct s5p_mfc_ctx *ctx = curr_ctx; - struct s5p_mfc_listable_wq *listable_wq; + struct mfc_dev *dev; + struct mfc_ctx *ctx = curr_ctx; + struct mfc_listable_wq *listable_wq; int ret = -1; if (!curr_ctx) { @@ -383,7 +383,7 @@ static int mfc_release_hwlock_ctx_protected(struct s5p_mfc_ctx *curr_ctx) return -EINVAL; } - mfc_print_hwlock(dev); + __mfc_print_hwlock(dev); clear_bit(curr_ctx->num, &dev->hwlock.bits); dev->hwlock.owned_by_irq = 0; @@ -395,7 +395,7 @@ static int mfc_release_hwlock_ctx_protected(struct s5p_mfc_ctx *curr_ctx) ret = 0; } else { mfc_debug(2, "There is a waiting module\n"); - listable_wq = list_entry(dev->hwlock.waiting_list.next, struct s5p_mfc_listable_wq, list); + listable_wq = list_entry(dev->hwlock.waiting_list.next, struct mfc_listable_wq, list); list_del(&listable_wq->list); dev->hwlock.wl_count--; @@ -418,7 +418,7 @@ static int mfc_release_hwlock_ctx_protected(struct s5p_mfc_ctx *curr_ctx) ret = 1; } - mfc_print_hwlock(dev); + __mfc_print_hwlock(dev); return ret; } @@ -427,9 +427,9 @@ static int mfc_release_hwlock_ctx_protected(struct s5p_mfc_ctx *curr_ctx) * 0: succeeded to release hwlock * 1: succeeded to release hwlock, hwlock is captured by another module */ -int s5p_mfc_release_hwlock_ctx(struct s5p_mfc_ctx *curr_ctx) +int mfc_release_hwlock_ctx(struct mfc_ctx *curr_ctx) { - struct s5p_mfc_dev *dev; + struct mfc_dev *dev; unsigned long flags; int ret = -1; @@ -445,12 +445,12 @@ int s5p_mfc_release_hwlock_ctx(struct s5p_mfc_ctx *curr_ctx) } spin_lock_irqsave(&dev->hwlock.lock, flags); - ret = mfc_release_hwlock_ctx_protected(curr_ctx); + ret = __mfc_release_hwlock_ctx_protected(curr_ctx); spin_unlock_irqrestore(&dev->hwlock.lock, flags); return ret; } -static inline int mfc_yield_hwlock(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *curr_ctx) +static inline int __mfc_yield_hwlock(struct mfc_dev *dev, struct mfc_ctx *curr_ctx) { unsigned long flags; @@ -466,12 +466,12 @@ static inline int mfc_yield_hwlock(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx * spin_lock_irqsave(&dev->hwlock.lock, flags); - mfc_release_hwlock_ctx_protected(curr_ctx); + __mfc_release_hwlock_ctx_protected(curr_ctx); spin_unlock_irqrestore(&dev->hwlock.lock, flags); /* Trigger again if other instance's work is waiting */ - if (s5p_mfc_is_work_to_do(dev)) + if (mfc_is_work_to_do(dev)) queue_work(dev->butler_wq, &dev->butler_work); return 0; @@ -480,7 +480,7 @@ static inline int mfc_yield_hwlock(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx * /* * Should be called with hwlock.lock */ -static inline void mfc_transfer_hwlock_ctx_protected(struct s5p_mfc_dev *dev, int curr_ctx_index) +static inline void __mfc_transfer_hwlock_ctx_protected(struct mfc_dev *dev, int curr_ctx_index) { dev->hwlock.dev = 0; dev->hwlock.bits = 0; @@ -494,11 +494,11 @@ static inline void mfc_transfer_hwlock_ctx_protected(struct s5p_mfc_dev *dev, in * >=0: succeeded to get hwlock_bit for the context, index of new context * -1, -EINVAL: failed to get hwlock_bit for a context */ -static int mfc_try_to_get_new_ctx_protected(struct s5p_mfc_dev *dev) +static int __mfc_try_to_get_new_ctx_protected(struct mfc_dev *dev) { int ret = 0; int index; - struct s5p_mfc_ctx *new_ctx; + struct mfc_ctx *new_ctx; if (!dev) { mfc_err_dev("no mfc device to run\n"); @@ -523,7 +523,7 @@ static int mfc_try_to_get_new_ctx_protected(struct s5p_mfc_dev *dev) } /* Choose the context to run */ - index = s5p_mfc_get_new_ctx(dev); + index = mfc_get_new_ctx(dev); if (index < 0) { /* This is perfectly ok, the scheduled ctx should wait * No contexts to run @@ -551,7 +551,7 @@ static int mfc_try_to_get_new_ctx_protected(struct s5p_mfc_dev *dev) * * Try to run an operation on hardware */ -void s5p_mfc_try_run(struct s5p_mfc_dev *dev) +void mfc_try_run(struct mfc_dev *dev) { int new_ctx_index; int ret; @@ -563,33 +563,33 @@ void s5p_mfc_try_run(struct s5p_mfc_dev *dev) } spin_lock_irqsave(&dev->hwlock.lock, flags); - mfc_print_hwlock(dev); + __mfc_print_hwlock(dev); - new_ctx_index = mfc_try_to_get_new_ctx_protected(dev); + new_ctx_index = __mfc_try_to_get_new_ctx_protected(dev); if (new_ctx_index < 0) { mfc_debug(2, "Failed to get new context to run\n"); - mfc_print_hwlock(dev); + __mfc_print_hwlock(dev); spin_unlock_irqrestore(&dev->hwlock.lock, flags); return; } dev->hwlock.owned_by_irq = 1; - mfc_print_hwlock(dev); + __mfc_print_hwlock(dev); spin_unlock_irqrestore(&dev->hwlock.lock, flags); - ret = s5p_mfc_just_run(dev, new_ctx_index); + ret = mfc_just_run(dev, new_ctx_index); if (ret) - mfc_yield_hwlock(dev, dev->ctx[new_ctx_index]); + __mfc_yield_hwlock(dev, dev->ctx[new_ctx_index]); } /* * Should be called without hwlock holding * */ -void s5p_mfc_cleanup_work_bit_and_try_run(struct s5p_mfc_ctx *curr_ctx) +void mfc_cleanup_work_bit_and_try_run(struct mfc_ctx *curr_ctx) { - struct s5p_mfc_dev *dev; + struct mfc_dev *dev; if (!curr_ctx) { mfc_err_dev("no mfc context to run\n"); @@ -602,23 +602,23 @@ void s5p_mfc_cleanup_work_bit_and_try_run(struct s5p_mfc_ctx *curr_ctx) return; } - s5p_mfc_clear_bit(curr_ctx->num, &dev->work_bits); + mfc_clear_bit(curr_ctx->num, &dev->work_bits); - s5p_mfc_try_run(dev); + mfc_try_run(dev); } -void s5p_mfc_cache_flush(struct s5p_mfc_dev *dev, int is_drm) +void mfc_cache_flush(struct mfc_dev *dev, int is_drm) { - s5p_mfc_cmd_cache_flush(dev); - if (s5p_mfc_wait_for_done_dev(dev, S5P_FIMV_R2H_CMD_CACHE_FLUSH_RET)) { + mfc_cmd_cache_flush(dev); + if (mfc_wait_for_done_dev(dev, MFC_REG_R2H_CMD_CACHE_FLUSH_RET)) { mfc_err_dev("Failed to CACHE_FLUSH\n"); dev->logging_data->cause |= (1 << MFC_CAUSE_FAIL_CHACHE_FLUSH); call_dop(dev, dump_and_stop_always, dev); } - s5p_mfc_pm_clock_off(dev); + mfc_pm_clock_off(dev); dev->curr_ctx_is_drm = is_drm; - s5p_mfc_pm_clock_on_with_base(dev, (is_drm ? MFCBUF_DRM : MFCBUF_NORMAL)); + mfc_pm_clock_on_with_base(dev, (is_drm ? MFCBUF_DRM : MFCBUF_NORMAL)); } /* @@ -627,9 +627,9 @@ void s5p_mfc_cache_flush(struct s5p_mfc_dev *dev, int is_drm) * 1: NAL_START command should be handled * -1: Error */ -static int mfc_nal_q_just_run(struct s5p_mfc_ctx *ctx, int need_cache_flush) +static int __mfc_nal_q_just_run(struct mfc_ctx *ctx, int need_cache_flush) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; unsigned int ret = -1; nal_queue_handle *nal_q_handle = dev->nal_q_handle; @@ -641,50 +641,50 @@ static int mfc_nal_q_just_run(struct s5p_mfc_ctx *ctx, int need_cache_flush) switch (nal_q_handle->nal_q_state) { case NAL_Q_STATE_CREATED: - if (s5p_mfc_nal_q_check_enable(dev) == 0) { + if (mfc_nal_q_check_enable(dev) == 0) { /* NAL START */ ret = 1; } else { - s5p_mfc_nal_q_clock_on(dev, nal_q_handle); + mfc_nal_q_clock_on(dev, nal_q_handle); - s5p_mfc_nal_q_init(dev, nal_q_handle); + mfc_nal_q_init(dev, nal_q_handle); /* enable NAL QUEUE */ if (need_cache_flush) - s5p_mfc_cache_flush(dev, ctx->is_drm); + mfc_cache_flush(dev, ctx->is_drm); mfc_info_ctx("[NALQ] start NAL QUEUE\n"); - s5p_mfc_nal_q_start(dev, nal_q_handle); + mfc_nal_q_start(dev, nal_q_handle); - if (s5p_mfc_nal_q_enqueue_in_buf(dev, ctx, nal_q_handle->nal_q_in_handle)) { + if (mfc_nal_q_enqueue_in_buf(dev, ctx, nal_q_handle->nal_q_in_handle)) { mfc_debug(2, "[NALQ] Failed to enqueue input data\n"); - s5p_mfc_nal_q_clock_off(dev, nal_q_handle); + mfc_nal_q_clock_off(dev, nal_q_handle); } - s5p_mfc_clear_bit(ctx->num, &dev->work_bits); - if ((s5p_mfc_ctx_ready(ctx) && !ctx->clear_work_bit) || + mfc_clear_bit(ctx->num, &dev->work_bits); + if ((mfc_ctx_ready(ctx) && !ctx->clear_work_bit) || nal_q_handle->nal_q_exception) - s5p_mfc_set_bit(ctx->num, &dev->work_bits); + mfc_set_bit(ctx->num, &dev->work_bits); ctx->clear_work_bit = 0; - s5p_mfc_release_hwlock_ctx(ctx); + mfc_release_hwlock_ctx(ctx); - if (s5p_mfc_is_work_to_do(dev)) + if (mfc_is_work_to_do(dev)) queue_work(dev->butler_wq, &dev->butler_work); ret = 0; } break; case NAL_Q_STATE_STARTED: - s5p_mfc_nal_q_clock_on(dev, nal_q_handle); + mfc_nal_q_clock_on(dev, nal_q_handle); - if (s5p_mfc_nal_q_check_enable(dev) == 0 || + if (mfc_nal_q_check_enable(dev) == 0 || nal_q_handle->nal_q_exception) { /* disable NAL QUEUE */ - s5p_mfc_nal_q_stop(dev, nal_q_handle); + mfc_nal_q_stop(dev, nal_q_handle); mfc_info_ctx("[NALQ] stop NAL QUEUE\n"); - if (s5p_mfc_wait_for_done_dev(dev, - S5P_FIMV_R2H_CMD_COMPLETE_QUEUE_RET)) { + if (mfc_wait_for_done_dev(dev, + MFC_REG_R2H_CMD_COMPLETE_QUEUE_RET)) { mfc_err_dev("[NALQ] Failed to stop queue\n"); dev->logging_data->cause |= (1 << MFC_CAUSE_FAIL_STOP_NAL_Q); call_dop(dev, dump_and_stop_always, dev); @@ -693,21 +693,21 @@ static int mfc_nal_q_just_run(struct s5p_mfc_ctx *ctx, int need_cache_flush) break; } else { /* NAL QUEUE */ - if (s5p_mfc_nal_q_enqueue_in_buf(dev, ctx, nal_q_handle->nal_q_in_handle)) { + if (mfc_nal_q_enqueue_in_buf(dev, ctx, nal_q_handle->nal_q_in_handle)) { mfc_debug(2, "[NALQ] Failed to enqueue input data\n"); - s5p_mfc_nal_q_clock_off(dev, nal_q_handle); + mfc_nal_q_clock_off(dev, nal_q_handle); } - s5p_mfc_clear_bit(ctx->num, &dev->work_bits); + mfc_clear_bit(ctx->num, &dev->work_bits); - if ((s5p_mfc_ctx_ready(ctx) && !ctx->clear_work_bit) || + if ((mfc_ctx_ready(ctx) && !ctx->clear_work_bit) || nal_q_handle->nal_q_exception) - s5p_mfc_set_bit(ctx->num, &dev->work_bits); + mfc_set_bit(ctx->num, &dev->work_bits); ctx->clear_work_bit = 0; - s5p_mfc_release_hwlock_ctx(ctx); + mfc_release_hwlock_ctx(ctx); - if (s5p_mfc_is_work_to_do(dev)) + if (mfc_is_work_to_do(dev)) queue_work(dev->butler_wq, &dev->butler_work); ret = 0; } @@ -722,27 +722,27 @@ static int mfc_nal_q_just_run(struct s5p_mfc_ctx *ctx, int need_cache_flush) return ret; } -static int mfc_just_run_dec(struct s5p_mfc_ctx *ctx) +static int __mfc_just_run_dec(struct mfc_ctx *ctx) { int ret = 0; switch (ctx->state) { case MFCINST_FINISHING: - ret = s5p_mfc_run_dec_last_frames(ctx); + ret = mfc_run_dec_last_frames(ctx); break; case MFCINST_RUNNING: case MFCINST_SPECIAL_PARSING_NAL: - ret = s5p_mfc_run_dec_frame(ctx); + ret = mfc_run_dec_frame(ctx); break; case MFCINST_INIT: - ret = s5p_mfc_open_inst(ctx); + ret = mfc_open_inst(ctx); break; case MFCINST_RETURN_INST: - ret = s5p_mfc_close_inst(ctx); + ret = mfc_close_inst(ctx); break; case MFCINST_GOT_INST: case MFCINST_SPECIAL_PARSING: - ret = s5p_mfc_run_dec_init(ctx); + ret = mfc_run_dec_init(ctx); break; case MFCINST_HEAD_PARSED: if (ctx->codec_buffer_allocated == 0) { @@ -751,22 +751,22 @@ static int mfc_just_run_dec(struct s5p_mfc_ctx *ctx) ret = -EAGAIN; break; } - ret = s5p_mfc_cmd_dec_init_buffers(ctx); + ret = mfc_cmd_dec_init_buffers(ctx); break; case MFCINST_RES_CHANGE_INIT: - ret = s5p_mfc_run_dec_last_frames(ctx); + ret = mfc_run_dec_last_frames(ctx); break; case MFCINST_RES_CHANGE_FLUSH: - ret = s5p_mfc_run_dec_last_frames(ctx); + ret = mfc_run_dec_last_frames(ctx); break; case MFCINST_RES_CHANGE_END: mfc_debug(2, "[DRC] Finished remaining frames after resolution change\n"); ctx->capture_state = QUEUE_FREE; mfc_debug(2, "[DRC] Will re-init the codec\n"); - ret = s5p_mfc_run_dec_init(ctx); + ret = mfc_run_dec_init(ctx); break; case MFCINST_DPB_FLUSHING: - ret = s5p_mfc_cmd_dpb_flush(ctx); + ret = mfc_cmd_dpb_flush(ctx); break; default: mfc_info_ctx("can't try command(decoder just_run), state : %d\n", ctx->state); @@ -776,39 +776,39 @@ static int mfc_just_run_dec(struct s5p_mfc_ctx *ctx) return ret; } -static int mfc_just_run_enc(struct s5p_mfc_ctx *ctx) +static int __mfc_just_run_enc(struct mfc_ctx *ctx) { int ret = 0; switch (ctx->state) { case MFCINST_FINISHING: - ret = s5p_mfc_run_enc_last_frames(ctx); + ret = mfc_run_enc_last_frames(ctx); break; case MFCINST_RUNNING: if (ctx->otf_handle) { - ret = s5p_mfc_otf_run_enc_frame(ctx); + ret = mfc_otf_run_enc_frame(ctx); break; } - ret = s5p_mfc_run_enc_frame(ctx); + ret = mfc_run_enc_frame(ctx); break; case MFCINST_INIT: - ret = s5p_mfc_open_inst(ctx); + ret = mfc_open_inst(ctx); break; case MFCINST_RETURN_INST: - ret = s5p_mfc_close_inst(ctx); + ret = mfc_close_inst(ctx); break; case MFCINST_GOT_INST: if (ctx->otf_handle) { - ret = s5p_mfc_otf_run_enc_init(ctx); + ret = mfc_otf_run_enc_init(ctx); break; } - ret = s5p_mfc_run_enc_init(ctx); + ret = mfc_run_enc_init(ctx); break; case MFCINST_HEAD_PARSED: - ret = s5p_mfc_cmd_enc_init_buffers(ctx); + ret = mfc_cmd_enc_init_buffers(ctx); break; case MFCINST_ABORT_INST: - ret = s5p_mfc_abort_inst(ctx); + ret = mfc_abort_inst(ctx); break; default: mfc_info_ctx("can't try command(encoder just_run), state : %d\n", ctx->state); @@ -819,9 +819,9 @@ static int mfc_just_run_enc(struct s5p_mfc_ctx *ctx) } /* Run an operation on hardware */ -int s5p_mfc_just_run(struct s5p_mfc_dev *dev, int new_ctx_index) +int mfc_just_run(struct mfc_dev *dev, int new_ctx_index) { - struct s5p_mfc_ctx *ctx; + struct mfc_ctx *ctx; unsigned int ret = 0; int need_cache_flush = 0; @@ -837,15 +837,15 @@ int s5p_mfc_just_run(struct s5p_mfc_dev *dev, int new_ctx_index) } if (ctx->state == MFCINST_RUNNING) - s5p_mfc_clean_ctx_int_flags(ctx); + mfc_clean_ctx_int_flags(ctx); mfc_debug(2, "New context: %d\n", new_ctx_index); dev->curr_ctx = ctx->num; /* Got context to run in ctx */ mfc_debug(2, "src: %d, dst: %d, state: %d, dpb_count = %d\n", - s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_queue), - s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_queue), ctx->state, ctx->dpb_count); mfc_debug(2, "ctx->state = %d\n", ctx->state); /* Last frame has already been sent to MFC @@ -860,7 +860,7 @@ int s5p_mfc_just_run(struct s5p_mfc_dev *dev, int new_ctx_index) mfc_debug(2, "need_cache_flush = %d, is_drm = %d\n", need_cache_flush, ctx->is_drm); if (dev->nal_q_handle) { - ret = mfc_nal_q_just_run(ctx, need_cache_flush); + ret = __mfc_nal_q_just_run(ctx, need_cache_flush); if (ret == 0) { mfc_debug(2, "NAL_Q was handled\n"); return ret; @@ -874,18 +874,18 @@ int s5p_mfc_just_run(struct s5p_mfc_dev *dev, int new_ctx_index) mfc_debug(2, "continue_clock_on = %d\n", dev->continue_clock_on); if (!dev->continue_clock_on) { - s5p_mfc_pm_clock_on(dev); + mfc_pm_clock_on(dev); } else { dev->continue_clock_on = false; } if (need_cache_flush) - s5p_mfc_cache_flush(dev, ctx->is_drm); + mfc_cache_flush(dev, ctx->is_drm); if (ctx->type == MFCINST_DECODER) { - ret = mfc_just_run_dec(ctx); + ret = __mfc_just_run_dec(ctx); } else if (ctx->type == MFCINST_ENCODER) { - ret = mfc_just_run_enc(ctx); + ret = __mfc_just_run_enc(ctx); } else { mfc_err_ctx("invalid context type: %d\n", ctx->type); ret = -EAGAIN; @@ -894,18 +894,18 @@ int s5p_mfc_just_run(struct s5p_mfc_dev *dev, int new_ctx_index) if (ret) { /* Check again the ctx condition and clear work bits * if ctx is not available. */ - if (s5p_mfc_ctx_ready(ctx) == 0 || ctx->clear_work_bit) { - s5p_mfc_clear_bit(ctx->num, &dev->work_bits); + if (mfc_ctx_ready(ctx) == 0 || ctx->clear_work_bit) { + mfc_clear_bit(ctx->num, &dev->work_bits); ctx->clear_work_bit = 0; } - s5p_mfc_pm_clock_off(dev); + mfc_pm_clock_off(dev); } return ret; } -void s5p_mfc_hwlock_handler_irq(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *curr_ctx, +void mfc_hwlock_handler_irq(struct mfc_dev *dev, struct mfc_ctx *curr_ctx, unsigned int reason, unsigned int err) { int new_ctx_index; @@ -923,51 +923,51 @@ void s5p_mfc_hwlock_handler_irq(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *cur } spin_lock_irqsave(&dev->hwlock.lock, flags); - mfc_print_hwlock(dev); + __mfc_print_hwlock(dev); if (dev->hwlock.owned_by_irq) { if (dev->preempt_ctx > MFC_NO_INSTANCE_SET) { mfc_debug(2, "There is a preempt_ctx\n"); dev->continue_clock_on = true; - s5p_mfc_wake_up_ctx(curr_ctx, reason, err); + mfc_wake_up_ctx(curr_ctx, reason, err); new_ctx_index = dev->preempt_ctx; mfc_debug(2, "preempt_ctx is : %d\n", new_ctx_index); spin_unlock_irqrestore(&dev->hwlock.lock, flags); - ret = s5p_mfc_just_run(dev, new_ctx_index); + ret = mfc_just_run(dev, new_ctx_index); if (ret) { dev->continue_clock_on = false; - mfc_yield_hwlock(dev, dev->ctx[new_ctx_index]); + __mfc_yield_hwlock(dev, dev->ctx[new_ctx_index]); } } else if (!list_empty(&dev->hwlock.waiting_list)) { mfc_debug(2, "There is a waiting module for hwlock\n"); dev->continue_clock_on = false; - s5p_mfc_pm_clock_off(dev); + mfc_pm_clock_off(dev); spin_unlock_irqrestore(&dev->hwlock.lock, flags); - s5p_mfc_release_hwlock_ctx(curr_ctx); - s5p_mfc_wake_up_ctx(curr_ctx, reason, err); + mfc_release_hwlock_ctx(curr_ctx); + mfc_wake_up_ctx(curr_ctx, reason, err); queue_work(dev->butler_wq, &dev->butler_work); } else { mfc_debug(2, "No preempt_ctx and no waiting module\n"); - new_ctx_index = s5p_mfc_get_new_ctx(dev); + new_ctx_index = mfc_get_new_ctx(dev); if (new_ctx_index < 0) { mfc_debug(2, "No ctx to run\n"); /* No contexts to run */ dev->continue_clock_on = false; - s5p_mfc_pm_clock_off(dev); + mfc_pm_clock_off(dev); spin_unlock_irqrestore(&dev->hwlock.lock, flags); - s5p_mfc_release_hwlock_ctx(curr_ctx); - s5p_mfc_wake_up_ctx(curr_ctx, reason, err); + mfc_release_hwlock_ctx(curr_ctx); + mfc_wake_up_ctx(curr_ctx, reason, err); queue_work(dev->butler_wq, &dev->butler_work); } else { mfc_debug(2, "There is a ctx to run\n"); dev->continue_clock_on = true; - s5p_mfc_wake_up_ctx(curr_ctx, reason, err); + mfc_wake_up_ctx(curr_ctx, reason, err); /* If cache flush command is needed or there is OTF handle, handler should stop */ if ((dev->curr_ctx_is_drm != dev->ctx[new_ctx_index]->is_drm) || @@ -978,18 +978,18 @@ void s5p_mfc_hwlock_handler_irq(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *cur spin_unlock_irqrestore(&dev->hwlock.lock, flags); - s5p_mfc_release_hwlock_ctx(curr_ctx); + mfc_release_hwlock_ctx(curr_ctx); queue_work(dev->butler_wq, &dev->butler_work); } else { mfc_debug(2, "Work to do successively (next ctx: %d)\n", new_ctx_index); - mfc_transfer_hwlock_ctx_protected(dev, new_ctx_index); + __mfc_transfer_hwlock_ctx_protected(dev, new_ctx_index); spin_unlock_irqrestore(&dev->hwlock.lock, flags); - ret = s5p_mfc_just_run(dev, new_ctx_index); + ret = mfc_just_run(dev, new_ctx_index); if (ret) { dev->continue_clock_on = false; - mfc_yield_hwlock(dev, dev->ctx[new_ctx_index]); + __mfc_yield_hwlock(dev, dev->ctx[new_ctx_index]); } } } @@ -997,11 +997,11 @@ void s5p_mfc_hwlock_handler_irq(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *cur } else { mfc_debug(2, "hwlock is NOT owned by irq\n"); dev->continue_clock_on = false; - s5p_mfc_pm_clock_off(dev); - s5p_mfc_wake_up_ctx(curr_ctx, reason, err); + mfc_pm_clock_off(dev); + mfc_wake_up_ctx(curr_ctx, reason, err); queue_work(dev->butler_wq, &dev->butler_work); spin_unlock_irqrestore(&dev->hwlock.lock, flags); } - mfc_print_hwlock(dev); + __mfc_print_hwlock(dev); } diff --git a/drivers/media/platform/exynos/mfc/mfc_hwlock.h b/drivers/media/platform/exynos/mfc/mfc_hwlock.h index 7e6a8a015338..b2c3f1dd3b90 100644 --- a/drivers/media/platform/exynos/mfc/mfc_hwlock.h +++ b/drivers/media/platform/exynos/mfc/mfc_hwlock.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_hwlock.h + * drivers/media/platform/exynos/mfc/mfc_hwlock.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -15,7 +15,7 @@ #include "mfc_common.h" -static inline void s5p_mfc_init_listable_wq_dev(struct s5p_mfc_dev *dev) +static inline void mfc_init_listable_wq_dev(struct mfc_dev *dev) { if (!dev) { mfc_err_dev("no mfc device to run\n"); @@ -29,7 +29,7 @@ static inline void s5p_mfc_init_listable_wq_dev(struct s5p_mfc_dev *dev) dev->hwlock_wq.dev = dev; } -static inline void s5p_mfc_init_listable_wq_ctx(struct s5p_mfc_ctx *curr_ctx) +static inline void mfc_init_listable_wq_ctx(struct mfc_ctx *curr_ctx) { if (!curr_ctx) { mfc_err_dev("no mfc context to run\n"); @@ -43,7 +43,7 @@ static inline void s5p_mfc_init_listable_wq_ctx(struct s5p_mfc_ctx *curr_ctx) curr_ctx->hwlock_wq.dev = NULL; } -static inline void s5p_mfc_destroy_listable_wq_dev(struct s5p_mfc_dev *dev) +static inline void mfc_destroy_listable_wq_dev(struct mfc_dev *dev) { if (!dev) { mfc_err_dev("no mfc device to run\n"); @@ -53,7 +53,7 @@ static inline void s5p_mfc_destroy_listable_wq_dev(struct s5p_mfc_dev *dev) mutex_destroy(&dev->hwlock_wq.wait_mutex); } -static inline void s5p_mfc_destroy_listable_wq_ctx(struct s5p_mfc_ctx *curr_ctx) +static inline void mfc_destroy_listable_wq_ctx(struct mfc_ctx *curr_ctx) { if (!curr_ctx) { mfc_err_dev("no mfc context to run\n"); @@ -63,21 +63,21 @@ static inline void s5p_mfc_destroy_listable_wq_ctx(struct s5p_mfc_ctx *curr_ctx) mutex_destroy(&curr_ctx->hwlock_wq.wait_mutex); } -void s5p_mfc_init_hwlock(struct s5p_mfc_dev *dev); +void mfc_init_hwlock(struct mfc_dev *dev); -int s5p_mfc_get_hwlock_dev(struct s5p_mfc_dev *dev); -int s5p_mfc_get_hwlock_ctx(struct s5p_mfc_ctx *curr_ctx); +int mfc_get_hwlock_dev(struct mfc_dev *dev); +int mfc_get_hwlock_ctx(struct mfc_ctx *curr_ctx); -int s5p_mfc_release_hwlock_dev(struct s5p_mfc_dev *dev); -int s5p_mfc_release_hwlock_ctx(struct s5p_mfc_ctx *curr_ctx); +int mfc_release_hwlock_dev(struct mfc_dev *dev); +int mfc_release_hwlock_ctx(struct mfc_ctx *curr_ctx); -void s5p_mfc_cache_flush(struct s5p_mfc_dev *dev, int is_drm); +void mfc_cache_flush(struct mfc_dev *dev, int is_drm); -void s5p_mfc_try_run(struct s5p_mfc_dev *dev); -void s5p_mfc_cleanup_work_bit_and_try_run(struct s5p_mfc_ctx *ctx); -int s5p_mfc_just_run(struct s5p_mfc_dev *dev, int new_ctx_index); +void mfc_try_run(struct mfc_dev *dev); +void mfc_cleanup_work_bit_and_try_run(struct mfc_ctx *ctx); +int mfc_just_run(struct mfc_dev *dev, int new_ctx_index); -void s5p_mfc_hwlock_handler_irq(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx, +void mfc_hwlock_handler_irq(struct mfc_dev *dev, struct mfc_ctx *ctx, unsigned int reason, unsigned int err); #endif /* __MFC_HWLOCK_H */ diff --git a/drivers/media/platform/exynos/mfc/mfc_inst.c b/drivers/media/platform/exynos/mfc/mfc_inst.c index 5d4e67ea37c5..8e130879aba3 100644 --- a/drivers/media/platform/exynos/mfc/mfc_inst.c +++ b/drivers/media/platform/exynos/mfc/mfc_inst.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_inst.c + * drivers/media/platform/exynos/mfc/mfc_inst.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -20,17 +20,17 @@ #include "mfc_utils.h" -int s5p_mfc_open_inst(struct s5p_mfc_ctx *ctx) +int mfc_open_inst(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; unsigned int reg; int ret; /* Preparing decoding - getting instance number */ mfc_debug(2, "Getting instance number\n"); - s5p_mfc_clean_ctx_int_flags(ctx); + mfc_clean_ctx_int_flags(ctx); - reg = MFC_READL(S5P_FIMV_CODEC_CONTROL); + reg = MFC_READL(MFC_REG_CODEC_CONTROL); /* Clear OTF_CONTROL[2:1] & OTF_DEBUG[3] */ reg &= ~(0x7 << 1); if (ctx->otf_handle) { @@ -43,42 +43,42 @@ int s5p_mfc_open_inst(struct s5p_mfc_ctx *ctx) mfc_info_ctx("Debugging mode enabled\n"); } } - MFC_WRITEL(reg, S5P_FIMV_CODEC_CONTROL); + MFC_WRITEL(reg, MFC_REG_CODEC_CONTROL); - ret = s5p_mfc_cmd_open_inst(ctx); + ret = mfc_cmd_open_inst(ctx); if (ret) { mfc_err_ctx("Failed to create a new instance\n"); - s5p_mfc_change_state(ctx, MFCINST_ERROR); + mfc_change_state(ctx, MFCINST_ERROR); } return ret; } -int s5p_mfc_close_inst(struct s5p_mfc_ctx *ctx) +int mfc_close_inst(struct mfc_ctx *ctx) { int ret = -EINVAL; /* Closing decoding instance */ mfc_debug(2, "Returning instance number\n"); - s5p_mfc_clean_ctx_int_flags(ctx); + mfc_clean_ctx_int_flags(ctx); if (ctx->state == MFCINST_FREE) { mfc_err_ctx("ctx already free status\n"); return ret; } - ret = s5p_mfc_cmd_close_inst(ctx); + ret = mfc_cmd_close_inst(ctx); if (ret) { mfc_err_ctx("Failed to return an instance\n"); - s5p_mfc_change_state(ctx, MFCINST_ERROR); + mfc_change_state(ctx, MFCINST_ERROR); } return ret; } -int s5p_mfc_abort_inst(struct s5p_mfc_ctx *ctx) +int mfc_abort_inst(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev; + struct mfc_dev *dev; if (!ctx) { mfc_err_dev("no mfc context to run\n"); @@ -91,19 +91,19 @@ int s5p_mfc_abort_inst(struct s5p_mfc_ctx *ctx) return -EINVAL; } - s5p_mfc_clean_ctx_int_flags(ctx); + mfc_clean_ctx_int_flags(ctx); - MFC_WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID); - s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_NAL_ABORT); + MFC_WRITEL(ctx->inst_no, MFC_REG_INSTANCE_ID); + mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_NAL_ABORT); return 0; } /* Initialize decoding */ -int s5p_mfc_init_decode(struct s5p_mfc_ctx *ctx) +int mfc_init_decode(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev; - struct s5p_mfc_dec *dec; + struct mfc_dev *dev; + struct mfc_dec *dec; unsigned int reg = 0; int fmo_aso_ctrl = 0; @@ -124,84 +124,84 @@ int s5p_mfc_init_decode(struct s5p_mfc_ctx *ctx) mfc_err_dev("no mfc decoder to run\n"); return -EINVAL; } - mfc_debug(2, "InstNo: %d/%d\n", ctx->inst_no, S5P_FIMV_H2R_CMD_SEQ_HEADER); - mfc_debug(2, "BUFs: %08x\n", MFC_READL(S5P_FIMV_D_CPB_BUFFER_ADDR)); + mfc_debug(2, "InstNo: %d/%d\n", ctx->inst_no, MFC_REG_H2R_CMD_SEQ_HEADER); + mfc_debug(2, "BUFs: %08x\n", MFC_READL(MFC_REG_D_CPB_BUFFER_ADDR)); /* When user sets desplay_delay to 0, * It works as "display_delay enable" and delay set to 0. * If user wants display_delay disable, It should be * set to negative value. */ if (dec->display_delay >= 0) { - reg |= (0x1 << S5P_FIMV_D_DEC_OPT_DISPLAY_DELAY_EN_SHIFT); - MFC_WRITEL(dec->display_delay, S5P_FIMV_D_DISPLAY_DELAY); + reg |= (0x1 << MFC_REG_D_DEC_OPT_DISPLAY_DELAY_EN_SHIFT); + MFC_WRITEL(dec->display_delay, MFC_REG_D_DISPLAY_DELAY); } /* FMO_ASO_CTRL - 0: Enable, 1: Disable */ - reg |= ((fmo_aso_ctrl & S5P_FIMV_D_DEC_OPT_FMO_ASO_CTRL_MASK) - << S5P_FIMV_D_DEC_OPT_FMO_ASO_CTRL_SHIFT); + reg |= ((fmo_aso_ctrl & MFC_REG_D_DEC_OPT_FMO_ASO_CTRL_MASK) + << MFC_REG_D_DEC_OPT_FMO_ASO_CTRL_SHIFT); - reg |= ((dec->idr_decoding & S5P_FIMV_D_DEC_OPT_IDR_DECODING_MASK) - << S5P_FIMV_D_DEC_OPT_IDR_DECODING_SHIFT); + reg |= ((dec->idr_decoding & MFC_REG_D_DEC_OPT_IDR_DECODING_MASK) + << MFC_REG_D_DEC_OPT_IDR_DECODING_SHIFT); /* VC1 RCV: Discard to parse additional header as default */ if (IS_VC1_RCV_DEC(ctx)) - reg |= (0x1 << S5P_FIMV_D_DEC_OPT_DISCARD_RCV_HEADER_SHIFT); + reg |= (0x1 << MFC_REG_D_DEC_OPT_DISCARD_RCV_HEADER_SHIFT); /* conceal control to specific color */ - reg |= (0x4 << S5P_FIMV_D_DEC_OPT_CONCEAL_CONTROL_SHIFT); + reg |= (0x4 << MFC_REG_D_DEC_OPT_CONCEAL_CONTROL_SHIFT); /* Disable parallel processing if nal_q_parallel_disable was set */ if (nal_q_parallel_disable) - reg |= (0x2 << S5P_FIMV_D_DEC_OPT_PARALLEL_DISABLE_SHIFT); + reg |= (0x2 << MFC_REG_D_DEC_OPT_PARALLEL_DISABLE_SHIFT); /* Realloc buffer for resolution decrease case in NAL QUEUE mode */ - reg |= (0x1 << S5P_FIMV_D_DEC_OPT_REALLOC_CONTROL_SHIFT); + reg |= (0x1 << MFC_REG_D_DEC_OPT_REALLOC_CONTROL_SHIFT); /* Parsing all including PPS */ - reg |= (0x1 << S5P_FIMV_D_DEC_OPT_SPECIAL_PARSING_SHIFT); + reg |= (0x1 << MFC_REG_D_DEC_OPT_SPECIAL_PARSING_SHIFT); - MFC_WRITEL(reg, S5P_FIMV_D_DEC_OPTIONS); + MFC_WRITEL(reg, MFC_REG_D_DEC_OPTIONS); - MFC_WRITEL(MFC_CONCEAL_COLOR, S5P_FIMV_D_FORCE_PIXEL_VAL); + MFC_WRITEL(MFC_CONCEAL_COLOR, MFC_REG_D_FORCE_PIXEL_VAL); if (IS_FIMV1_DEC(ctx)) { mfc_debug(2, "Setting FIMV1 resolution to %dx%d\n", ctx->img_width, ctx->img_height); - MFC_WRITEL(ctx->img_width, S5P_FIMV_D_SET_FRAME_WIDTH); - MFC_WRITEL(ctx->img_height, S5P_FIMV_D_SET_FRAME_HEIGHT); + MFC_WRITEL(ctx->img_width, MFC_REG_D_SET_FRAME_WIDTH); + MFC_WRITEL(ctx->img_height, MFC_REG_D_SET_FRAME_HEIGHT); } - s5p_mfc_set_pixel_format(dev, ctx->dst_fmt->fourcc); + mfc_set_pixel_format(dev, ctx->dst_fmt->fourcc); reg = 0; /* Enable realloc interface if SEI is enabled */ if (dec->sei_parse) - reg |= (0x1 << S5P_FIMV_D_SEI_ENABLE_NEED_INIT_BUFFER_SHIFT); + reg |= (0x1 << MFC_REG_D_SEI_ENABLE_NEED_INIT_BUFFER_SHIFT); if (MFC_FEATURE_SUPPORT(dev, dev->pdata->static_info_dec)) { - reg |= (0x1 << S5P_FIMV_D_SEI_ENABLE_CONTENT_LIGHT_SHIFT); - reg |= (0x1 << S5P_FIMV_D_SEI_ENABLE_MASTERING_DISPLAY_SHIFT); + reg |= (0x1 << MFC_REG_D_SEI_ENABLE_CONTENT_LIGHT_SHIFT); + reg |= (0x1 << MFC_REG_D_SEI_ENABLE_MASTERING_DISPLAY_SHIFT); } - reg |= (0x1 << S5P_FIMV_D_SEI_ENABLE_RECOVERY_PARSING_SHIFT); + reg |= (0x1 << MFC_REG_D_SEI_ENABLE_RECOVERY_PARSING_SHIFT); - MFC_WRITEL(reg, S5P_FIMV_D_SEI_ENABLE); - mfc_debug(2, "SEI enable was set, 0x%x\n", MFC_READL(S5P_FIMV_D_SEI_ENABLE)); + MFC_WRITEL(reg, MFC_REG_D_SEI_ENABLE); + mfc_debug(2, "SEI enable was set, 0x%x\n", MFC_READL(MFC_REG_D_SEI_ENABLE)); - MFC_WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID); + MFC_WRITEL(ctx->inst_no, MFC_REG_INSTANCE_ID); if (sfr_dump & MFC_DUMP_DEC_SEQ_START) call_dop(dev, dump_regs, dev); - s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_SEQ_HEADER); + mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_SEQ_HEADER); mfc_debug_leave(); return 0; } /* Decode a single frame */ -int s5p_mfc_decode_one_frame(struct s5p_mfc_ctx *ctx, int last_frame) +int mfc_decode_one_frame(struct mfc_ctx *ctx, int last_frame) { - struct s5p_mfc_dev *dev; - struct s5p_mfc_dec *dec; + struct mfc_dev *dev; + struct mfc_dec *dec; u32 reg = 0; if (!ctx) { @@ -224,20 +224,20 @@ int s5p_mfc_decode_one_frame(struct s5p_mfc_ctx *ctx, int last_frame) mfc_debug(2, "Dynamic:0x%08x, Available:0x%lx\n", dec->dynamic_set, dec->available_dpb); - reg = MFC_READL(S5P_FIMV_D_NAL_START_OPTIONS); - reg &= ~(0x1 << S5P_FIMV_D_NAL_START_OPT_BLACK_BAR_SHIFT); - reg |= ((dec->detect_black_bar & 0x1) << S5P_FIMV_D_NAL_START_OPT_BLACK_BAR_SHIFT); - MFC_WRITEL(reg, S5P_FIMV_D_NAL_START_OPTIONS); + reg = MFC_READL(MFC_REG_D_NAL_START_OPTIONS); + reg &= ~(0x1 << MFC_REG_D_NAL_START_OPT_BLACK_BAR_SHIFT); + reg |= ((dec->detect_black_bar & 0x1) << MFC_REG_D_NAL_START_OPT_BLACK_BAR_SHIFT); + MFC_WRITEL(reg, MFC_REG_D_NAL_START_OPTIONS); mfc_debug(3, "[BLACKBAR] black bar detect set: %#x\n", reg); - MFC_WRITEL(dec->dynamic_set, S5P_FIMV_D_DYNAMIC_DPB_FLAG_LOWER); - MFC_WRITEL(0x0, S5P_FIMV_D_DYNAMIC_DPB_FLAG_UPPER); - MFC_WRITEL(dec->available_dpb, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER); - MFC_WRITEL(0x0, S5P_FIMV_D_AVAILABLE_DPB_FLAG_UPPER); - MFC_WRITEL(dec->slice_enable, S5P_FIMV_D_SLICE_IF_ENABLE); - MFC_WRITEL(MFC_TIMEOUT_VALUE, S5P_FIMV_DEC_TIMEOUT_VALUE); + MFC_WRITEL(dec->dynamic_set, MFC_REG_D_DYNAMIC_DPB_FLAG_LOWER); + MFC_WRITEL(0x0, MFC_REG_D_DYNAMIC_DPB_FLAG_UPPER); + MFC_WRITEL(dec->available_dpb, MFC_REG_D_AVAILABLE_DPB_FLAG_LOWER); + MFC_WRITEL(0x0, MFC_REG_D_AVAILABLE_DPB_FLAG_UPPER); + MFC_WRITEL(dec->slice_enable, MFC_REG_D_SLICE_IF_ENABLE); + MFC_WRITEL(MFC_TIMEOUT_VALUE, MFC_REG_DEC_TIMEOUT_VALUE); - MFC_WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID); + MFC_WRITEL(ctx->inst_no, MFC_REG_INSTANCE_ID); if ((sfr_dump & MFC_DUMP_DEC_NAL_START) && !ctx->check_dump) { call_dop(dev, dump_regs, dev); @@ -248,12 +248,12 @@ int s5p_mfc_decode_one_frame(struct s5p_mfc_ctx *ctx, int last_frame) * is the last frame or not. */ switch (last_frame) { case 0: - s5p_mfc_perf_measure_on(dev); + mfc_perf_measure_on(dev); - s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_NAL_START); + mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_NAL_START); break; case 1: - s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_LAST_FRAME); + mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_LAST_FRAME); break; } @@ -261,26 +261,26 @@ int s5p_mfc_decode_one_frame(struct s5p_mfc_ctx *ctx, int last_frame) return 0; } -int s5p_mfc_init_encode(struct s5p_mfc_ctx *ctx) +int mfc_init_encode(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; mfc_debug(2, "++\n"); if (IS_H264_ENC(ctx)) - s5p_mfc_set_enc_params_h264(ctx); + mfc_set_enc_params_h264(ctx); else if (IS_MPEG4_ENC(ctx)) - s5p_mfc_set_enc_params_mpeg4(ctx); + mfc_set_enc_params_mpeg4(ctx); else if (IS_H263_ENC(ctx)) - s5p_mfc_set_enc_params_h263(ctx); + mfc_set_enc_params_h263(ctx); else if (IS_VP8_ENC(ctx)) - s5p_mfc_set_enc_params_vp8(ctx); + mfc_set_enc_params_vp8(ctx); else if (IS_VP9_ENC(ctx)) - s5p_mfc_set_enc_params_vp9(ctx); + mfc_set_enc_params_vp9(ctx); else if (IS_HEVC_ENC(ctx)) - s5p_mfc_set_enc_params_hevc(ctx); + mfc_set_enc_params_hevc(ctx); else if (IS_BPG_ENC(ctx)) - s5p_mfc_set_enc_params_bpg(ctx); + mfc_set_enc_params_bpg(ctx); else { mfc_err_ctx("Unknown codec for encoding (%x)\n", ctx->codec_mode); @@ -288,52 +288,52 @@ int s5p_mfc_init_encode(struct s5p_mfc_ctx *ctx) } mfc_debug(5, "RC) Bitrate: %d / framerate: %#x / config %#x / mode %#x\n", - MFC_READL(S5P_FIMV_E_RC_BIT_RATE), - MFC_READL(S5P_FIMV_E_RC_FRAME_RATE), - MFC_READL(S5P_FIMV_E_RC_CONFIG), - MFC_READL(S5P_FIMV_E_RC_MODE)); + MFC_READL(MFC_REG_E_RC_BIT_RATE), + MFC_READL(MFC_REG_E_RC_FRAME_RATE), + MFC_READL(MFC_REG_E_RC_CONFIG), + MFC_READL(MFC_REG_E_RC_MODE)); - MFC_WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID); + MFC_WRITEL(ctx->inst_no, MFC_REG_INSTANCE_ID); if (sfr_dump & MFC_DUMP_ENC_SEQ_START) call_dop(dev, dump_regs, dev); - s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_SEQ_HEADER); + mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_SEQ_HEADER); mfc_debug(2, "--\n"); return 0; } -static int mfc_h264_set_aso_slice_order(struct s5p_mfc_ctx *ctx) +static int mfc_h264_set_aso_slice_order(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_enc *enc = ctx->enc_priv; - struct s5p_mfc_enc_params *p = &enc->params; - struct s5p_mfc_h264_enc_params *p_264 = &p->codec.h264; + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + struct mfc_h264_enc_params *p_264 = &p->codec.h264; int i; if (p_264->aso_enable) { for (i = 0; i < 8; i++) MFC_WRITEL(p_264->aso_slice_order[i], - S5P_FIMV_E_H264_ASO_SLICE_ORDER_0 + i * 4); + MFC_REG_E_H264_ASO_SLICE_ORDER_0 + i * 4); } return 0; } /* Encode a single frame */ -int s5p_mfc_encode_one_frame(struct s5p_mfc_ctx *ctx, int last_frame) +int mfc_encode_one_frame(struct mfc_ctx *ctx, int last_frame) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; mfc_debug(2, "++\n"); if (IS_H264_ENC(ctx)) mfc_h264_set_aso_slice_order(ctx); - s5p_mfc_set_slice_mode(ctx); + mfc_set_slice_mode(ctx); - MFC_WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID); + MFC_WRITEL(ctx->inst_no, MFC_REG_INSTANCE_ID); if ((sfr_dump & MFC_DUMP_ENC_NAL_START) && !ctx->check_dump) { call_dop(dev, dump_regs, dev); @@ -344,12 +344,12 @@ int s5p_mfc_encode_one_frame(struct s5p_mfc_ctx *ctx, int last_frame) * is the last frame or not. */ switch (last_frame) { case 0: - s5p_mfc_perf_measure_on(dev); + mfc_perf_measure_on(dev); - s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_NAL_START); + mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_NAL_START); break; case 1: - s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_LAST_FRAME); + mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_LAST_FRAME); break; } diff --git a/drivers/media/platform/exynos/mfc/mfc_inst.h b/drivers/media/platform/exynos/mfc/mfc_inst.h index 10b07ac60340..909b0d99af33 100644 --- a/drivers/media/platform/exynos/mfc/mfc_inst.h +++ b/drivers/media/platform/exynos/mfc/mfc_inst.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_inst.h + * drivers/media/platform/exynos/mfc/mfc_inst.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -15,14 +15,14 @@ #include "mfc_common.h" -int s5p_mfc_open_inst(struct s5p_mfc_ctx *ctx); -int s5p_mfc_close_inst(struct s5p_mfc_ctx *ctx); -int s5p_mfc_abort_inst(struct s5p_mfc_ctx *ctx); +int mfc_open_inst(struct mfc_ctx *ctx); +int mfc_close_inst(struct mfc_ctx *ctx); +int mfc_abort_inst(struct mfc_ctx *ctx); -int s5p_mfc_init_decode(struct s5p_mfc_ctx *ctx); -int s5p_mfc_decode_one_frame(struct s5p_mfc_ctx *ctx, int last_frame); +int mfc_init_decode(struct mfc_ctx *ctx); +int mfc_decode_one_frame(struct mfc_ctx *ctx, int last_frame); -int s5p_mfc_init_encode(struct s5p_mfc_ctx *ctx); -int s5p_mfc_encode_one_frame(struct s5p_mfc_ctx *ctx, int last_frame); +int mfc_init_encode(struct mfc_ctx *ctx); +int mfc_encode_one_frame(struct mfc_ctx *ctx, int last_frame); #endif /* __MFC_INST_H */ diff --git a/drivers/media/platform/exynos/mfc/mfc_irq.c b/drivers/media/platform/exynos/mfc/mfc_irq.c index 95136aff9c0c..680ce74ef09a 100644 --- a/drivers/media/platform/exynos/mfc/mfc_irq.c +++ b/drivers/media/platform/exynos/mfc/mfc_irq.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_irq.c + * drivers/media/platform/exynos/mfc/mfc_irq.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -29,26 +29,26 @@ #include "mfc_buf.h" #include "mfc_mem.h" -static void mfc_handle_black_bar_info(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx) +static void __mfc_handle_black_bar_info(struct mfc_dev *dev, struct mfc_ctx *ctx) { struct v4l2_rect new_black_bar; int black_bar_info; - struct s5p_mfc_dec *dec = ctx->dec_priv; + struct mfc_dec *dec = ctx->dec_priv; - black_bar_info = s5p_mfc_get_black_bar_detection(); + black_bar_info = mfc_get_black_bar_detection(); mfc_debug(3, "[BLACKBAR] type: %#x\n", black_bar_info); - if (black_bar_info == S5P_FIMV_DISP_STATUS_BLACK_BAR) { - new_black_bar.left = s5p_mfc_get_black_bar_pos_x(); - new_black_bar.top = s5p_mfc_get_black_bar_pos_y(); - new_black_bar.width = s5p_mfc_get_black_bar_image_w(); - new_black_bar.height = s5p_mfc_get_black_bar_image_h(); - } else if (black_bar_info == S5P_FIMV_DISP_STATUS_BLACK_SCREEN) { + if (black_bar_info == MFC_REG_DISP_STATUS_BLACK_BAR) { + new_black_bar.left = mfc_get_black_bar_pos_x(); + new_black_bar.top = mfc_get_black_bar_pos_y(); + new_black_bar.width = mfc_get_black_bar_image_w(); + new_black_bar.height = mfc_get_black_bar_image_h(); + } else if (black_bar_info == MFC_REG_DISP_STATUS_BLACK_SCREEN) { new_black_bar.left = -1; new_black_bar.top = -1; new_black_bar.width = ctx->img_width; new_black_bar.height = ctx->img_height; - } else if (black_bar_info == S5P_FIMV_DISP_STATUS_NOT_DETECTED) { + } else if (black_bar_info == MFC_REG_DISP_STATUS_NOT_DETECTED) { new_black_bar.left = 0; new_black_bar.top = 0; new_black_bar.width = ctx->img_width; @@ -72,20 +72,20 @@ static void mfc_handle_black_bar_info(struct s5p_mfc_dev *dev, struct s5p_mfc_ct dec->black_bar_updated = 1; } -static unsigned int mfc_handle_frame_field(struct s5p_mfc_ctx *ctx) +static unsigned int __mfc_handle_frame_field(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; unsigned int interlace_type = 0, is_interlace = 0, is_mbaff = 0; unsigned int field; if (CODEC_INTERLACED(ctx)) - is_interlace = s5p_mfc_is_interlace_picture(); + is_interlace = mfc_is_interlace_picture(); if (CODEC_MBAFF(ctx)) - is_mbaff = s5p_mfc_is_mbaff_picture(); + is_mbaff = mfc_is_mbaff_picture(); if (is_interlace) { - interlace_type = s5p_mfc_get_interlace_type(); + interlace_type = mfc_get_interlace_type(); if (interlace_type) field = V4L2_FIELD_INTERLACED_TB; else @@ -102,17 +102,17 @@ static unsigned int mfc_handle_frame_field(struct s5p_mfc_ctx *ctx) return field; } -static void mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx) +static void __mfc_handle_frame_all_extracted(struct mfc_ctx *ctx) { - struct s5p_mfc_dec *dec = ctx->dec_priv; - struct s5p_mfc_buf *dst_mb; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_buf *dst_mb; int index, i, is_first = 1; mfc_debug(2, "Decided to finish\n"); ctx->sequence++; while (1) { - dst_mb = s5p_mfc_get_del_buf(&ctx->buf_queue_lock, &ctx->dst_buf_queue, MFC_BUF_NO_TOUCH_USED); + dst_mb = mfc_get_del_buf(&ctx->buf_queue_lock, &ctx->dst_buf_queue, MFC_BUF_NO_TOUCH_USED); if (!dst_mb) break; @@ -125,7 +125,7 @@ static void mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx) vb2_set_plane_payload(&dst_mb->vb.vb2_buf, i, 0); dst_mb->vb.sequence = (ctx->sequence++); - dst_mb->vb.field = mfc_handle_frame_field(ctx); + dst_mb->vb.field = __mfc_handle_frame_field(ctx); dst_mb->vb.reserved2 = 0; clear_bit(dst_mb->vb.vb2_buf.index, &dec->available_dpb); @@ -154,44 +154,44 @@ static void mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx) /* decoder dst buffer CFW UNPROT */ if (ctx->is_drm) - s5p_mfc_raw_unprotect(ctx, dst_mb, index); + mfc_raw_unprotect(ctx, dst_mb, index); mfc_debug(2, "Cleaned up buffer: %d\n", index); } - s5p_mfc_handle_force_change_status(ctx); + mfc_handle_force_change_status(ctx); mfc_debug(2, "After cleanup\n"); } -static void mfc_handle_frame_copy_timestamp(struct s5p_mfc_ctx *ctx) +static void __mfc_handle_frame_copy_timestamp(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_buf *ref_mb, *src_mb; + struct mfc_dev *dev = ctx->dev; + struct mfc_buf *ref_mb, *src_mb; dma_addr_t dec_y_addr; - dec_y_addr = (dma_addr_t)s5p_mfc_get_dec_y_addr(); + dec_y_addr = (dma_addr_t)mfc_get_dec_y_addr(); /* Get the source buffer */ - src_mb = s5p_mfc_get_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, MFC_BUF_NO_TOUCH_USED); + src_mb = mfc_get_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, MFC_BUF_NO_TOUCH_USED); if (!src_mb) { mfc_err_dev("[TS] no src buffers\n"); return; } - ref_mb = s5p_mfc_find_buf(&ctx->buf_queue_lock, &ctx->ref_buf_queue, dec_y_addr); + ref_mb = mfc_find_buf(&ctx->buf_queue_lock, &ctx->ref_buf_queue, dec_y_addr); if (ref_mb) ref_mb->vb.vb2_buf.timestamp = src_mb->vb.vb2_buf.timestamp; } -static void mfc_handle_frame_output_move(struct s5p_mfc_ctx *ctx, +static void __mfc_handle_frame_output_move(struct mfc_ctx *ctx, dma_addr_t dspl_y_addr, unsigned int released_flag) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_dec *dec = ctx->dec_priv; - struct s5p_mfc_buf *ref_mb; + struct mfc_dev *dev = ctx->dev; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_buf *ref_mb; int index; - ref_mb = s5p_mfc_find_move_buf(&ctx->buf_queue_lock, + ref_mb = mfc_find_move_buf(&ctx->buf_queue_lock, &ctx->dst_buf_queue, &ctx->ref_buf_queue, dspl_y_addr, released_flag); if (ref_mb) { index = ref_mb->vb.vb2_buf.index; @@ -204,23 +204,23 @@ static void mfc_handle_frame_output_move(struct s5p_mfc_ctx *ctx, dec->available_dpb &= ~(1 << index); released_flag &= ~(1 << index); mfc_debug(2, "[DPB] Corrupted frame(%d), it will be re-used(release)\n", - s5p_mfc_get_warn(s5p_mfc_get_int_err())); + mfc_get_warn(mfc_get_int_err())); } else { dec->err_reuse_flag |= 1 << index; mfc_debug(2, "[DPB] Corrupted frame(%d), it will be re-used(not released)\n", - s5p_mfc_get_warn(s5p_mfc_get_int_err())); + mfc_get_warn(mfc_get_int_err())); } dec->dynamic_used |= released_flag; } } -static void mfc_handle_frame_output_del(struct s5p_mfc_ctx *ctx, +static void __mfc_handle_frame_output_del(struct mfc_ctx *ctx, unsigned int err, unsigned int released_flag) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_dec *dec = ctx->dec_priv; - struct s5p_mfc_raw_info *raw = &ctx->raw_buf; - struct s5p_mfc_buf *ref_mb; + struct mfc_dev *dev = ctx->dev; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_raw_info *raw = &ctx->raw_buf; + struct mfc_buf *ref_mb; dma_addr_t dspl_y_addr; unsigned int frame_type; unsigned int dst_frame_status; @@ -229,29 +229,29 @@ static void mfc_handle_frame_output_del(struct s5p_mfc_ctx *ctx, unsigned int i, index; if (MFC_FEATURE_SUPPORT(dev, dev->pdata->color_aspect_dec)) { - is_video_signal_type = s5p_mfc_get_video_signal_type(); - is_colour_description = s5p_mfc_get_colour_description(); + is_video_signal_type = mfc_get_video_signal_type(); + is_colour_description = mfc_get_colour_description(); } if (MFC_FEATURE_SUPPORT(dev, dev->pdata->static_info_dec)) { - is_content_light = s5p_mfc_get_sei_avail_content_light(); - is_display_colour = s5p_mfc_get_sei_avail_mastering_display(); + is_content_light = mfc_get_sei_avail_content_light(); + is_display_colour = mfc_get_sei_avail_mastering_display(); } if (MFC_FEATURE_SUPPORT(dev, dev->pdata->black_bar) && dec->detect_black_bar) - mfc_handle_black_bar_info(dev, ctx); + __mfc_handle_black_bar_info(dev, ctx); else dec->black_bar_updated = 0; if (dec->immediate_display == 1) { - dspl_y_addr = (dma_addr_t)s5p_mfc_get_dec_y_addr(); - frame_type = s5p_mfc_get_dec_frame_type(); + dspl_y_addr = (dma_addr_t)mfc_get_dec_y_addr(); + frame_type = mfc_get_dec_frame_type(); } else { - dspl_y_addr = (dma_addr_t)s5p_mfc_get_disp_y_addr(); - frame_type = s5p_mfc_get_disp_frame_type(); + dspl_y_addr = (dma_addr_t)mfc_get_disp_y_addr(); + frame_type = mfc_get_disp_frame_type(); } - ref_mb = s5p_mfc_find_del_buf(&ctx->buf_queue_lock, + ref_mb = mfc_find_del_buf(&ctx->buf_queue_lock, &ctx->ref_buf_queue, dspl_y_addr); if (ref_mb) { index = ref_mb->vb.vb2_buf.index; @@ -260,7 +260,7 @@ static void mfc_handle_frame_output_del(struct s5p_mfc_ctx *ctx, ctx->num, index, ref_mb->addr[0][0]); ref_mb->vb.sequence = ctx->sequence; - ref_mb->vb.field = mfc_handle_frame_field(ctx); + ref_mb->vb.field = __mfc_handle_frame_field(ctx); /* Set reserved2 bits in order to inform SEI information */ ref_mb->vb.reserved2 = 0; @@ -287,7 +287,7 @@ static void mfc_handle_frame_output_del(struct s5p_mfc_ctx *ctx, } if (IS_VP9_DEC(ctx) && MFC_FEATURE_SUPPORT(dev, dev->pdata->color_aspect_dec)) { - if (dec->color_space != S5P_FIMV_D_COLOR_UNKNOWN) { + if (dec->color_space != MFC_REG_D_COLOR_UNKNOWN) { ref_mb->vb.reserved2 |= (1 << 3); mfc_debug(2, "[HDR] color space parsed\n"); } @@ -320,32 +320,32 @@ static void mfc_handle_frame_output_del(struct s5p_mfc_ctx *ctx, V4L2_BUF_FLAG_ERROR); switch (frame_type) { - case S5P_FIMV_DISPLAY_FRAME_I: + case MFC_REG_DISPLAY_FRAME_I: ref_mb->vb.flags |= V4L2_BUF_FLAG_KEYFRAME; break; - case S5P_FIMV_DISPLAY_FRAME_P: + case MFC_REG_DISPLAY_FRAME_P: ref_mb->vb.flags |= V4L2_BUF_FLAG_PFRAME; break; - case S5P_FIMV_DISPLAY_FRAME_B: + case MFC_REG_DISPLAY_FRAME_B: ref_mb->vb.flags |= V4L2_BUF_FLAG_BFRAME; break; default: break; } - if (s5p_mfc_get_warn(err)) { + if (mfc_get_warn(err)) { mfc_err_ctx("Warning for displayed frame: %d\n", - s5p_mfc_get_warn(err)); + mfc_get_warn(err)); ref_mb->vb.flags |= V4L2_BUF_FLAG_ERROR; } if (call_cop(ctx, get_buf_ctrls_val, ctx, &ctx->dst_ctrls[index]) < 0) mfc_err_ctx("failed in get_buf_ctrls_val\n"); - s5p_mfc_handle_released_info(ctx, released_flag, index); + mfc_handle_released_info(ctx, released_flag, index); if (dec->immediate_display == 1) { - dst_frame_status = s5p_mfc_get_dec_status(); + dst_frame_status = mfc_get_dec_status(); call_cop(ctx, get_buf_update_val, ctx, &ctx->dst_ctrls[index], @@ -369,23 +369,23 @@ static void mfc_handle_frame_output_del(struct s5p_mfc_ctx *ctx, dec->y_addr_for_pb = 0; } - s5p_mfc_qos_update_last_framerate(ctx, ref_mb->vb.vb2_buf.timestamp); - vb2_buffer_done(&ref_mb->vb.vb2_buf, s5p_mfc_get_warn(err) ? + mfc_qos_update_last_framerate(ctx, ref_mb->vb.vb2_buf.timestamp); + vb2_buffer_done(&ref_mb->vb.vb2_buf, mfc_get_warn(err) ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); } } -static void mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err) +static void __mfc_handle_frame_new(struct mfc_ctx *ctx, unsigned int err) { - struct s5p_mfc_dec *dec = ctx->dec_priv; - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_dev *dev = ctx->dev; dma_addr_t dspl_y_addr; unsigned int frame_type; int mvc_view_id; unsigned int prev_flag, released_flag = 0; - frame_type = s5p_mfc_get_disp_frame_type(); - mvc_view_id = s5p_mfc_get_mvc_disp_view_id(); + frame_type = mfc_get_disp_frame_type(); + mvc_view_id = mfc_get_mvc_disp_view_id(); if (IS_H264_MVC_DEC(ctx)) { if (mvc_view_id == 0) @@ -394,43 +394,43 @@ static void mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err) ctx->sequence++; } - dspl_y_addr = s5p_mfc_get_disp_y_addr(); + dspl_y_addr = mfc_get_disp_y_addr(); if (dec->immediate_display == 1) { - dspl_y_addr = (dma_addr_t)s5p_mfc_get_dec_y_addr(); - frame_type = s5p_mfc_get_dec_frame_type(); + dspl_y_addr = (dma_addr_t)mfc_get_dec_y_addr(); + frame_type = mfc_get_dec_frame_type(); } mfc_debug(2, "[FRAME] frame type: %d\n", frame_type); /* If frame is same as previous then skip and do not dequeue */ - if (frame_type == S5P_FIMV_DISPLAY_FRAME_NOT_CODED) + if (frame_type == MFC_REG_DISPLAY_FRAME_NOT_CODED) if (!CODEC_NOT_CODED(ctx)) return; prev_flag = dec->dynamic_used; - dec->dynamic_used = s5p_mfc_get_dec_used_flag(); + dec->dynamic_used = mfc_get_dec_used_flag(); released_flag = prev_flag & (~dec->dynamic_used); mfc_debug(2, "[DPB] Used flag: old = %08x, new = %08x, Released buffer = %08x\n", prev_flag, dec->dynamic_used, released_flag); /* decoder dst buffer CFW UNPROT */ - s5p_mfc_unprotect_released_dpb(ctx, released_flag); + mfc_unprotect_released_dpb(ctx, released_flag); if ((IS_VC1_RCV_DEC(ctx) && - s5p_mfc_get_warn(err) == S5P_FIMV_ERR_SYNC_POINT_NOT_RECEIVED) || - (s5p_mfc_get_warn(err) == S5P_FIMV_ERR_BROKEN_LINK)) - mfc_handle_frame_output_move(ctx, dspl_y_addr, released_flag); + mfc_get_warn(err) == MFC_REG_ERR_SYNC_POINT_NOT_RECEIVED) || + (mfc_get_warn(err) == MFC_REG_ERR_BROKEN_LINK)) + __mfc_handle_frame_output_move(ctx, dspl_y_addr, released_flag); else - mfc_handle_frame_output_del(ctx, err, released_flag); + __mfc_handle_frame_output_del(ctx, err, released_flag); } -static void mfc_handle_frame_error(struct s5p_mfc_ctx *ctx, +static void __mfc_handle_frame_error(struct mfc_ctx *ctx, unsigned int reason, unsigned int err) { - struct s5p_mfc_dec *dec; - struct s5p_mfc_buf *src_mb; + struct mfc_dec *dec; + struct mfc_buf *src_mb; unsigned int index; if (ctx->type == MFCINST_ENCODER) { @@ -447,7 +447,7 @@ static void mfc_handle_frame_error(struct s5p_mfc_ctx *ctx, mfc_err_ctx("Interrupt Error: %d\n", err); /* Get the source buffer */ - src_mb = s5p_mfc_get_del_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, MFC_BUF_NO_TOUCH_USED); + src_mb = mfc_get_del_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, MFC_BUF_NO_TOUCH_USED); if (!src_mb) { mfc_err_dev("no src buffers\n"); @@ -464,7 +464,7 @@ static void mfc_handle_frame_error(struct s5p_mfc_ctx *ctx, /* decoder src buffer CFW UNPROT */ if (ctx->is_drm) - s5p_mfc_stream_unprotect(ctx, src_mb, index); + mfc_stream_unprotect(ctx, src_mb, index); vb2_buffer_done(&src_mb->vb.vb2_buf, VB2_BUF_STATE_ERROR); } @@ -472,38 +472,38 @@ static void mfc_handle_frame_error(struct s5p_mfc_ctx *ctx, mfc_debug(2, "Assesing whether this context should be run again\n"); } -static void mfc_handle_ref_frame(struct s5p_mfc_ctx *ctx) +static void __mfc_handle_ref_frame(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_dec *dec = ctx->dec_priv; - struct s5p_mfc_buf *dst_mb; + struct mfc_dev *dev = ctx->dev; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_buf *dst_mb; dma_addr_t dec_addr; - dec_addr = (dma_addr_t)s5p_mfc_get_dec_y_addr(); + dec_addr = (dma_addr_t)mfc_get_dec_y_addr(); /* Try to search decoded address in whole dst queue */ - dst_mb = s5p_mfc_find_move_buf_used(&ctx->buf_queue_lock, + dst_mb = mfc_find_move_buf_used(&ctx->buf_queue_lock, &ctx->ref_buf_queue, &ctx->dst_buf_queue, dec_addr); if (dst_mb) { mfc_debug(2, "[DPB] Found in dst queue = 0x%08llx, buf = 0x%08llx\n", dec_addr, dst_mb->addr[0][0]); - if (!(dec->dynamic_set & s5p_mfc_get_dec_used_flag())) + if (!(dec->dynamic_set & mfc_get_dec_used_flag())) dec->dynamic_used |= dec->dynamic_set; } else { mfc_debug(2, "[DPB] Can't find buffer for addr = 0x%08llx\n", dec_addr); } } -static void mfc_handle_reuse_buffer(struct s5p_mfc_ctx *ctx) +static void __mfc_handle_reuse_buffer(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_dec *dec = ctx->dec_priv; + struct mfc_dev *dev = ctx->dev; + struct mfc_dec *dec = ctx->dec_priv; unsigned int prev_flag, released_flag = 0; int i; prev_flag = dec->dynamic_used; - dec->dynamic_used = s5p_mfc_get_dec_used_flag(); + dec->dynamic_used = mfc_get_dec_used_flag(); released_flag = prev_flag & (~dec->dynamic_used); if (!released_flag) @@ -512,7 +512,7 @@ static void mfc_handle_reuse_buffer(struct s5p_mfc_ctx *ctx) /* Reuse not referenced buf anymore */ for (i = 0; i < MFC_MAX_DPBS; i++) if (released_flag & (1 << i)) - if (s5p_mfc_move_reuse_buffer(ctx, i)) + if (mfc_move_reuse_buffer(ctx, i)) released_flag &= ~(1 << i); /* Not reused buffer should be released when there is a display frame */ @@ -522,18 +522,18 @@ static void mfc_handle_reuse_buffer(struct s5p_mfc_ctx *ctx) clear_bit(i, &dec->available_dpb); } -static void mfc_handle_frame_input(struct s5p_mfc_ctx *ctx, unsigned int err) +static void __mfc_handle_frame_input(struct mfc_ctx *ctx, unsigned int err) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_dec *dec = ctx->dec_priv; - struct s5p_mfc_buf *src_mb; + struct mfc_dev *dev = ctx->dev; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_buf *src_mb; unsigned int index; int deleted = 0; unsigned long consumed; - consumed = dec->consumed + s5p_mfc_get_consumed_stream(); + consumed = dec->consumed + mfc_get_consumed_stream(); - if (s5p_mfc_get_err(err) == S5P_FIMV_ERR_NON_PAIRED_FIELD) { + if (mfc_get_err(err) == MFC_REG_ERR_NON_PAIRED_FIELD) { /* * For non-paired field, the same buffer need to be * resubmitted and the consumed stream will be 0 @@ -543,8 +543,8 @@ static void mfc_handle_frame_input(struct s5p_mfc_ctx *ctx, unsigned int err) } /* Get the source buffer */ - src_mb = s5p_mfc_get_del_if_consumed(ctx, &ctx->src_buf_queue, - s5p_mfc_get_consumed_stream(), STUFF_BYTE, err, &deleted); + src_mb = mfc_get_del_if_consumed(ctx, &ctx->src_buf_queue, + mfc_get_consumed_stream(), STUFF_BYTE, err, &deleted); if (!src_mb) { mfc_err_dev("no src buffers\n"); return; @@ -559,7 +559,7 @@ static void mfc_handle_frame_input(struct s5p_mfc_ctx *ctx, unsigned int err) mfc_debug(2, "[MULTIFRAME] Running again the same buffer\n"); if (CODEC_MULTIFRAME(ctx)) - dec->y_addr_for_pb = (dma_addr_t)s5p_mfc_get_dec_y_addr(); + dec->y_addr_for_pb = (dma_addr_t)mfc_get_dec_y_addr(); dec->consumed = consumed; dec->remained_size = src_mb->vb.vb2_buf.planes[0].bytesused @@ -583,54 +583,54 @@ static void mfc_handle_frame_input(struct s5p_mfc_ctx *ctx, unsigned int err) /* decoder src buffer CFW UNPROT */ if (ctx->is_drm) - s5p_mfc_stream_unprotect(ctx, src_mb, index); + mfc_stream_unprotect(ctx, src_mb, index); vb2_buffer_done(&src_mb->vb.vb2_buf, VB2_BUF_STATE_DONE); } /* Handle frame decoding interrupt */ -static void mfc_handle_frame(struct s5p_mfc_ctx *ctx, +static void __mfc_handle_frame(struct mfc_ctx *ctx, unsigned int reason, unsigned int err) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_dec *dec = ctx->dec_priv; + struct mfc_dev *dev = ctx->dev; + struct mfc_dec *dec = ctx->dec_priv; unsigned int dst_frame_status, sei_avail_frame_pack; unsigned int res_change, need_dpb_change, need_scratch_change; - dst_frame_status = s5p_mfc_get_disp_status(); - res_change = s5p_mfc_get_res_change(); - need_dpb_change = s5p_mfc_get_dpb_change(); - need_scratch_change = s5p_mfc_get_scratch_change(); - sei_avail_frame_pack = s5p_mfc_get_sei_avail_frame_pack(); + dst_frame_status = mfc_get_disp_status(); + res_change = mfc_get_res_change(); + need_dpb_change = mfc_get_dpb_change(); + need_scratch_change = mfc_get_scratch_change(); + sei_avail_frame_pack = mfc_get_sei_avail_frame_pack(); if (dec->immediate_display == 1) - dst_frame_status = s5p_mfc_get_dec_status(); + dst_frame_status = mfc_get_dec_status(); mfc_debug(2, "[FRAME] frame status: %d\n", dst_frame_status); mfc_debug(2, "[FRAME] display status: %d, type: %d, yaddr: %#x\n", - s5p_mfc_get_disp_status(), s5p_mfc_get_disp_frame_type(), - s5p_mfc_get_disp_y_addr()); + mfc_get_disp_status(), mfc_get_disp_frame_type(), + mfc_get_disp_y_addr()); mfc_debug(2, "[FRAME] decoded status: %d, type: %d, yaddr: %#x\n", - s5p_mfc_get_dec_status(), s5p_mfc_get_dec_frame_type(), - s5p_mfc_get_dec_y_addr()); + mfc_get_dec_status(), mfc_get_dec_frame_type(), + mfc_get_dec_y_addr()); - mfc_debug(4, "[HDR] SEI available status: 0x%08x\n", s5p_mfc_get_sei_avail()); - mfc_debug(4, "[HDR] SEI content light: 0x%08x\n", s5p_mfc_get_sei_content_light()); + mfc_debug(4, "[HDR] SEI available status: 0x%08x\n", mfc_get_sei_avail()); + mfc_debug(4, "[HDR] SEI content light: 0x%08x\n", mfc_get_sei_content_light()); mfc_debug(4, "[HDR] SEI luminance: 0x%08x, 0x%08x white point: 0x%08x\n", - s5p_mfc_get_sei_mastering0(), s5p_mfc_get_sei_mastering1(), - s5p_mfc_get_sei_mastering2()); + mfc_get_sei_mastering0(), mfc_get_sei_mastering1(), + mfc_get_sei_mastering2()); mfc_debug(4, "[HDR] SEI display primaries: 0x%08x, 0x%08x, 0x%08x\n", - s5p_mfc_get_sei_mastering3(), s5p_mfc_get_sei_mastering4(), - s5p_mfc_get_sei_mastering5()); + mfc_get_sei_mastering3(), mfc_get_sei_mastering4(), + mfc_get_sei_mastering5()); mfc_debug(2, "[DPB] Used flag: old = %08x, new = %08x\n", - dec->dynamic_used, s5p_mfc_get_dec_used_flag()); + dec->dynamic_used, mfc_get_dec_used_flag()); if (ctx->state == MFCINST_RES_CHANGE_INIT) - s5p_mfc_change_state(ctx, MFCINST_RES_CHANGE_FLUSH); + mfc_change_state(ctx, MFCINST_RES_CHANGE_FLUSH); if (res_change) { mfc_debug(2, "[DRC] Resolution change set to %d\n", res_change); - s5p_mfc_change_state(ctx, MFCINST_RES_CHANGE_INIT); + mfc_change_state(ctx, MFCINST_RES_CHANGE_INIT); ctx->wait_state = WAIT_DECODING; mfc_debug(7, "[DRC] Decoding waiting! : %d\n", ctx->wait_state); return; @@ -639,37 +639,37 @@ static void mfc_handle_frame(struct s5p_mfc_ctx *ctx, if (need_dpb_change || need_scratch_change) mfc_debug(2, "[DRC] Interframe resolution change is not supported\n"); - if (s5p_mfc_is_queue_count_same(&ctx->buf_queue_lock, &ctx->src_buf_queue, 0) && - s5p_mfc_is_queue_count_same(&ctx->buf_queue_lock, &ctx->dst_buf_queue, 0)) { + if (mfc_is_queue_count_same(&ctx->buf_queue_lock, &ctx->src_buf_queue, 0) && + mfc_is_queue_count_same(&ctx->buf_queue_lock, &ctx->dst_buf_queue, 0)) { mfc_err_dev("Queue count is zero for src and dst\n"); goto leave_handle_frame; } if (IS_H264_DEC(ctx) && sei_avail_frame_pack && - dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_ONLY) { + dst_frame_status == MFC_REG_DEC_STATUS_DECODING_ONLY) { mfc_debug(2, "Frame packing SEI exists for a frame\n"); mfc_debug(2, "Reallocate DPBs and issue init_buffer\n"); ctx->is_dpb_realloc = 1; - s5p_mfc_change_state(ctx, MFCINST_HEAD_PARSED); + mfc_change_state(ctx, MFCINST_HEAD_PARSED); ctx->capture_state = QUEUE_FREE; ctx->wait_state = WAIT_DECODING; - mfc_handle_frame_all_extracted(ctx); + __mfc_handle_frame_all_extracted(ctx); goto leave_handle_frame; } /* All frames remaining in the buffer have been extracted */ - if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) { + if (dst_frame_status == MFC_REG_DEC_STATUS_DECODING_EMPTY) { if (ctx->state == MFCINST_RES_CHANGE_FLUSH) { struct mfc_timestamp *temp_ts = NULL; mfc_debug(2, "[DRC] Last frame received after resolution change\n"); - mfc_handle_frame_all_extracted(ctx); - s5p_mfc_change_state(ctx, MFCINST_RES_CHANGE_END); + __mfc_handle_frame_all_extracted(ctx); + mfc_change_state(ctx, MFCINST_RES_CHANGE_END); /* If there is no display frame after resolution change, * Some released frames can't be unprotected. * So, check and request unprotection in the end of DRC. */ - s5p_mfc_cleanup_assigned_dpb(ctx); + mfc_cleanup_assigned_dpb(ctx); /* empty the timestamp queue */ while (!list_empty(&ctx->ts_list)) { @@ -679,58 +679,58 @@ static void mfc_handle_frame(struct s5p_mfc_ctx *ctx, } ctx->ts_count = 0; ctx->ts_is_full = 0; - s5p_mfc_qos_reset_last_framerate(ctx); - s5p_mfc_qos_set_framerate(ctx, DEC_DEFAULT_FPS); + mfc_qos_reset_last_framerate(ctx); + mfc_qos_set_framerate(ctx, DEC_DEFAULT_FPS); goto leave_handle_frame; } else { - mfc_handle_frame_all_extracted(ctx); + __mfc_handle_frame_all_extracted(ctx); } } - if (s5p_mfc_get_num_of_tile() >= 4) + if (mfc_get_num_of_tile() >= 4) dec->num_of_tile_over_4 = 1; switch (dst_frame_status) { - case S5P_FIMV_DEC_STATUS_DECODING_DISPLAY: - mfc_handle_ref_frame(ctx); + case MFC_REG_DEC_STATUS_DECODING_DISPLAY: + __mfc_handle_ref_frame(ctx); break; - case S5P_FIMV_DEC_STATUS_DECODING_ONLY: - mfc_handle_ref_frame(ctx); + case MFC_REG_DEC_STATUS_DECODING_ONLY: + __mfc_handle_ref_frame(ctx); /* * Some cases can have many decoding only frames like VP9 * alt-ref frame. So need handling release buffer * because of DPB full. */ - mfc_handle_reuse_buffer(ctx); + __mfc_handle_reuse_buffer(ctx); break; default: break; } - if (s5p_mfc_dec_status_decoding(dst_frame_status)) - mfc_handle_frame_copy_timestamp(ctx); + if (mfc_dec_status_decoding(dst_frame_status)) + __mfc_handle_frame_copy_timestamp(ctx); /* A frame has been decoded and is in the buffer */ - if (s5p_mfc_dec_status_display(dst_frame_status)) - mfc_handle_frame_new(ctx, err); + if (mfc_dec_status_display(dst_frame_status)) + __mfc_handle_frame_new(ctx, err); else mfc_debug(2, "No frame decode\n"); /* Mark source buffer as complete */ - if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY) - mfc_handle_frame_input(ctx, err); + if (dst_frame_status != MFC_REG_DEC_STATUS_DISPLAY_ONLY) + __mfc_handle_frame_input(ctx, err); leave_handle_frame: mfc_debug(2, "Assesing whether this context should be run again\n"); } -static void mfc_handle_stream_copy_timestamp(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *src_mb) +static void __mfc_handle_stream_copy_timestamp(struct mfc_ctx *ctx, struct mfc_buf *src_mb) { - struct s5p_mfc_dev *dev; - struct s5p_mfc_enc *enc = ctx->enc_priv; - struct s5p_mfc_enc_params *p = &enc->params; - struct s5p_mfc_buf *dst_mb; + struct mfc_dev *dev; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + struct mfc_buf *dst_mb; u32 interval; u64 start_timestamp; u64 new_timestamp; @@ -758,22 +758,22 @@ static void mfc_handle_stream_copy_timestamp(struct s5p_mfc_ctx *ctx, struct s5p new_timestamp, interval * src_mb->done_index); /* Get the destination buffer */ - dst_mb = s5p_mfc_get_buf(&ctx->buf_queue_lock, &ctx->dst_buf_queue, MFC_BUF_NO_TOUCH_USED); + dst_mb = mfc_get_buf(&ctx->buf_queue_lock, &ctx->dst_buf_queue, MFC_BUF_NO_TOUCH_USED); if (dst_mb) dst_mb->vb.vb2_buf.timestamp = new_timestamp; } -static void mfc_handle_stream_input(struct s5p_mfc_ctx *ctx) +static void __mfc_handle_stream_input(struct mfc_ctx *ctx) { - struct s5p_mfc_raw_info *raw; - struct s5p_mfc_buf *ref_mb, *src_mb; + struct mfc_raw_info *raw; + struct mfc_buf *ref_mb, *src_mb; dma_addr_t enc_addr[3] = { 0, 0, 0 }; int i, found_in_src_queue = 0; unsigned int index; raw = &ctx->raw_buf; - s5p_mfc_get_enc_frame_buffer(ctx, &enc_addr[0], raw->num_planes); + mfc_get_enc_frame_buffer(ctx, &enc_addr[0], raw->num_planes); if (enc_addr[0] == 0) { mfc_debug(3, "no encoded src\n"); goto move_buf; @@ -783,12 +783,12 @@ static void mfc_handle_stream_input(struct s5p_mfc_ctx *ctx) ctx->num, i, enc_addr[i]); if (IS_BUFFER_BATCH_MODE(ctx)) { - src_mb = s5p_mfc_find_first_buf(&ctx->buf_queue_lock, + src_mb = mfc_find_first_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, enc_addr[0]); if (src_mb) { found_in_src_queue = 1; - mfc_handle_stream_copy_timestamp(ctx, src_mb); + __mfc_handle_stream_copy_timestamp(ctx, src_mb); src_mb->done_index++; mfc_debug(4, "[BUFCON] batch buf done_index: %d\n", src_mb->done_index); @@ -800,20 +800,20 @@ static void mfc_handle_stream_input(struct s5p_mfc_ctx *ctx) /* single buffer || last image in a buffer container */ if (!src_mb->num_valid_bufs || src_mb->done_index == src_mb->num_valid_bufs) { - src_mb = s5p_mfc_find_del_buf(&ctx->buf_queue_lock, + src_mb = mfc_find_del_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, enc_addr[0]); for (i = 0; i < raw->num_planes; i++) - s5p_mfc_bufcon_put_daddr(ctx, src_mb, i); + mfc_bufcon_put_daddr(ctx, src_mb, i); vb2_buffer_done(&src_mb->vb.vb2_buf, VB2_BUF_STATE_DONE); } /* encoder src buffer CFW UNPROT */ if (ctx->is_drm) - s5p_mfc_raw_unprotect(ctx, src_mb, index); + mfc_raw_unprotect(ctx, src_mb, index); } } else { /* normal single buffer */ - src_mb = s5p_mfc_find_del_buf(&ctx->buf_queue_lock, + src_mb = mfc_find_del_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, enc_addr[0]); if (src_mb) { found_in_src_queue = 1; @@ -827,10 +827,10 @@ static void mfc_handle_stream_input(struct s5p_mfc_ctx *ctx) /* encoder src buffer CFW UNPROT */ if (ctx->is_drm) - s5p_mfc_raw_unprotect(ctx, src_mb, index); + mfc_raw_unprotect(ctx, src_mb, index); } else { mfc_debug(3, "no src buf in src_queue\n"); - ref_mb = s5p_mfc_find_del_buf(&ctx->buf_queue_lock, + ref_mb = mfc_find_del_buf(&ctx->buf_queue_lock, &ctx->ref_buf_queue, enc_addr[0]); if (ref_mb) { mfc_debug(3, "find src buf in ref_queue\n"); @@ -839,7 +839,7 @@ static void mfc_handle_stream_input(struct s5p_mfc_ctx *ctx) /* encoder src buffer CFW UNPROT */ if (ctx->is_drm) { index = ref_mb->vb.vb2_buf.index; - s5p_mfc_raw_unprotect(ctx, ref_mb, index); + mfc_raw_unprotect(ctx, ref_mb, index); } } else { mfc_err_ctx("couldn't find src buffer\n"); @@ -850,20 +850,20 @@ static void mfc_handle_stream_input(struct s5p_mfc_ctx *ctx) move_buf: /* move enqueued src buffer: src queue -> ref queue */ if (!found_in_src_queue && ctx->state != MFCINST_FINISHING) { - s5p_mfc_move_first_buf_used(&ctx->buf_queue_lock, + mfc_move_first_buf_used(&ctx->buf_queue_lock, &ctx->ref_buf_queue, &ctx->src_buf_queue, MFC_QUEUE_ADD_BOTTOM); mfc_debug(2, "enc src_buf_queue(%d) -> ref_buf_queue(%d)\n", - s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_queue), - s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->ref_buf_queue)); + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->ref_buf_queue)); } } -static void mfc_handle_stream_output(struct s5p_mfc_ctx *ctx, int slice_type, +static void __mfc_handle_stream_output(struct mfc_ctx *ctx, int slice_type, unsigned int strm_size) { - struct s5p_mfc_enc *enc = ctx->enc_priv; - struct s5p_mfc_buf *dst_mb; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_buf *dst_mb; unsigned int index; if (strm_size == 0) { @@ -875,7 +875,7 @@ static void mfc_handle_stream_output(struct s5p_mfc_ctx *ctx, int slice_type, } /* at least one more dest. buffers exist always */ - dst_mb = s5p_mfc_get_del_buf(&ctx->buf_queue_lock, + dst_mb = mfc_get_del_buf(&ctx->buf_queue_lock, &ctx->dst_buf_queue, MFC_BUF_NO_TOUCH_USED); if (!dst_mb) { mfc_err_ctx("no dst buffers\n"); @@ -889,13 +889,13 @@ static void mfc_handle_stream_output(struct s5p_mfc_ctx *ctx, int slice_type, V4L2_BUF_FLAG_PFRAME | V4L2_BUF_FLAG_BFRAME); switch (slice_type) { - case S5P_FIMV_E_SLICE_TYPE_I: + case MFC_REG_E_SLICE_TYPE_I: dst_mb->vb.flags |= V4L2_BUF_FLAG_KEYFRAME; break; - case S5P_FIMV_E_SLICE_TYPE_P: + case MFC_REG_E_SLICE_TYPE_P: dst_mb->vb.flags |= V4L2_BUF_FLAG_PFRAME; break; - case S5P_FIMV_E_SLICE_TYPE_B: + case MFC_REG_E_SLICE_TYPE_B: dst_mb->vb.flags |= V4L2_BUF_FLAG_BFRAME; break; default: @@ -918,64 +918,64 @@ static void mfc_handle_stream_output(struct s5p_mfc_ctx *ctx, int slice_type, /* encoder dst buffer CFW UNPROT */ if (ctx->is_drm) - s5p_mfc_stream_unprotect(ctx, dst_mb, index); + mfc_stream_unprotect(ctx, dst_mb, index); } /* Handle frame encoding interrupt */ -static int mfc_handle_stream(struct s5p_mfc_ctx *ctx) +static int __mfc_handle_stream(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_enc *enc = ctx->enc_priv; + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; int slice_type; unsigned int strm_size; unsigned int pic_count; - slice_type = s5p_mfc_get_enc_slice_type(); - strm_size = s5p_mfc_get_enc_strm_size(); - pic_count = s5p_mfc_get_enc_pic_count(); + slice_type = mfc_get_enc_slice_type(); + strm_size = mfc_get_enc_strm_size(); + pic_count = mfc_get_enc_pic_count(); mfc_debug(2, "[STREAM] encoded slice type: %d, size: %d, display order: %d\n", slice_type, strm_size, pic_count); /* buffer full handling */ if (enc->buf_full) { - s5p_mfc_change_state(ctx, MFCINST_ABORT_INST); + mfc_change_state(ctx, MFCINST_ABORT_INST); return 0; } if (ctx->state == MFCINST_RUNNING_BUF_FULL) - s5p_mfc_change_state(ctx, MFCINST_RUNNING); + mfc_change_state(ctx, MFCINST_RUNNING); /* set encoded frame type */ enc->frame_type = slice_type; ctx->sequence++; if (enc->in_slice) { - if (s5p_mfc_is_queue_count_same(&ctx->buf_queue_lock, &ctx->dst_buf_queue, 0)) { - s5p_mfc_clear_bit(ctx->num, &dev->work_bits); + if (mfc_is_queue_count_same(&ctx->buf_queue_lock, &ctx->dst_buf_queue, 0)) { + mfc_clear_bit(ctx->num, &dev->work_bits); } return 0; } /* handle source buffer */ - mfc_handle_stream_input(ctx); + __mfc_handle_stream_input(ctx); /* handle destination buffer */ - mfc_handle_stream_output(ctx, slice_type, strm_size); + __mfc_handle_stream_output(ctx, slice_type, strm_size); return 0; } /* Error handling for interrupt */ -static inline void mfc_handle_error(struct s5p_mfc_ctx *ctx, +static inline void __mfc_handle_error(struct mfc_ctx *ctx, unsigned int reason, unsigned int err) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_buf *src_mb; + struct mfc_dev *dev = ctx->dev; + struct mfc_buf *src_mb; int index; mfc_err_ctx("Interrupt Error: display: %d, decoded: %d\n", - s5p_mfc_get_warn(err), s5p_mfc_get_err(err)); - err = s5p_mfc_get_err(err); + mfc_get_warn(err), mfc_get_err(err)); + err = mfc_get_err(err); /* Error recovery is dependent on the state of context */ switch (ctx->state) { @@ -986,7 +986,7 @@ static inline void mfc_handle_error(struct s5p_mfc_ctx *ctx, unsigned char *stream_vir = NULL; unsigned int strm_size = 0; - src_mb = s5p_mfc_get_del_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, MFC_BUF_NO_TOUCH_USED); + src_mb = mfc_get_del_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, MFC_BUF_NO_TOUCH_USED); if (src_mb) { stream_vir = src_mb->vir_addr; strm_size = src_mb->vb.vb2_buf.planes[0].bytesused; @@ -1001,11 +1001,11 @@ static inline void mfc_handle_error(struct s5p_mfc_ctx *ctx, vb2_buffer_done(&src_mb->vb.vb2_buf, VB2_BUF_STATE_DONE); } } else { - src_mb = s5p_mfc_get_del_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, MFC_BUF_NO_TOUCH_USED); + src_mb = mfc_get_del_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, MFC_BUF_NO_TOUCH_USED); if (src_mb) { index = src_mb->vb.vb2_buf.index; /* decoder src buffer CFW UNPROT */ - s5p_mfc_stream_unprotect(ctx, src_mb, index); + mfc_stream_unprotect(ctx, src_mb, index); vb2_buffer_done(&src_mb->vb.vb2_buf, VB2_BUF_STATE_DONE); } } @@ -1030,11 +1030,11 @@ static inline void mfc_handle_error(struct s5p_mfc_ctx *ctx, case MFCINST_FINISHING: /* It is higly probable that an error occured * while decoding a frame */ - s5p_mfc_change_state(ctx, MFCINST_ERROR); + mfc_change_state(ctx, MFCINST_ERROR); /* Mark all dst buffers as having an error */ - s5p_mfc_cleanup_queue(&ctx->buf_queue_lock, &ctx->dst_buf_queue); + mfc_cleanup_queue(&ctx->buf_queue_lock, &ctx->dst_buf_queue); /* Mark all src buffers as having an error */ - s5p_mfc_cleanup_queue(&ctx->buf_queue_lock, &ctx->src_buf_queue); + mfc_cleanup_queue(&ctx->buf_queue_lock, &ctx->src_buf_queue); break; default: mfc_err_ctx("Encountered an error interrupt which had not been handled\n"); @@ -1043,68 +1043,68 @@ static inline void mfc_handle_error(struct s5p_mfc_ctx *ctx, break; } - s5p_mfc_wake_up_dev(dev, reason, err); + mfc_wake_up_dev(dev, reason, err); return; } /* Handle header decoder interrupt */ -static int mfc_handle_seq_dec(struct s5p_mfc_ctx *ctx) +static int __mfc_handle_seq_dec(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_dec *dec = ctx->dec_priv; + struct mfc_dev *dev = ctx->dev; + struct mfc_dec *dec = ctx->dec_priv; int i, is_interlace, is_mbaff; if (ctx->src_fmt->fourcc != V4L2_PIX_FMT_FIMV1) { - ctx->img_width = s5p_mfc_get_img_width(); - ctx->img_height = s5p_mfc_get_img_height(); + ctx->img_width = mfc_get_img_width(); + ctx->img_height = mfc_get_img_height(); ctx->crop_width = ctx->img_width; ctx->crop_height = ctx->img_height; mfc_info_ctx("[STREAM] resolution w: %d, h: %d\n", ctx->img_width, ctx->img_height); } - ctx->dpb_count = s5p_mfc_get_dpb_count(); - ctx->scratch_buf_size = s5p_mfc_get_scratch_size(); + ctx->dpb_count = mfc_get_dpb_count(); + ctx->scratch_buf_size = mfc_get_scratch_size(); for (i = 0; i < ctx->dst_fmt->num_planes; i++) - ctx->min_dpb_size[i] = s5p_mfc_get_min_dpb_size(i); + ctx->min_dpb_size[i] = mfc_get_min_dpb_size(i); - s5p_mfc_dec_store_crop_info(ctx); - dec->mv_count = s5p_mfc_get_mv_count(); + mfc_dec_store_crop_info(ctx); + dec->mv_count = mfc_get_mv_count(); if (CODEC_10BIT(ctx) && dev->pdata->support_10bit) { - if (s5p_mfc_get_luma_bit_depth_minus8() || - s5p_mfc_get_chroma_bit_depth_minus8() || - s5p_mfc_get_profile() == S5P_FIMV_D_PROFILE_HEVC_MAIN_10) { + if (mfc_get_luma_bit_depth_minus8() || + mfc_get_chroma_bit_depth_minus8() || + mfc_get_profile() == MFC_REG_D_PROFILE_HEVC_MAIN_10) { ctx->is_10bit = 1; mfc_info_ctx("[STREAM][10BIT] 10bit contents, profile: %d, depth: %d/%d\n", - s5p_mfc_get_profile(), - s5p_mfc_get_luma_bit_depth_minus8() + 8, - s5p_mfc_get_chroma_bit_depth_minus8() + 8); + mfc_get_profile(), + mfc_get_luma_bit_depth_minus8() + 8, + mfc_get_chroma_bit_depth_minus8() + 8); } } if (CODEC_422FORMAT(ctx) && dev->pdata->support_422) { - if (s5p_mfc_get_chroma_format() == S5P_FIMV_D_CHROMA_422) { + if (mfc_get_chroma_format() == MFC_REG_D_CHROMA_422) { ctx->is_422 = 1; mfc_info_ctx("[STREAM] 422 chroma format\n"); } } if (ctx->img_width == 0 || ctx->img_height == 0) - s5p_mfc_change_state(ctx, MFCINST_ERROR); + mfc_change_state(ctx, MFCINST_ERROR); else - s5p_mfc_change_state(ctx, MFCINST_HEAD_PARSED); + mfc_change_state(ctx, MFCINST_HEAD_PARSED); if (ctx->state == MFCINST_HEAD_PARSED) { - is_interlace = s5p_mfc_is_interlace_picture(); - is_mbaff = s5p_mfc_is_mbaff_picture(); + is_interlace = mfc_is_interlace_picture(); + is_mbaff = mfc_is_mbaff_picture(); if (is_interlace || is_mbaff) dec->is_interlaced = 1; mfc_debug(2, "[INTERLACE] interlace: %d, mbaff: %d\n", is_interlace, is_mbaff); } if (IS_H264_DEC(ctx) || IS_H264_MVC_DEC(ctx) || IS_HEVC_DEC(ctx)) { - struct s5p_mfc_buf *src_mb = s5p_mfc_get_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, MFC_BUF_NO_TOUCH_USED); + struct mfc_buf *src_mb = mfc_get_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, MFC_BUF_NO_TOUCH_USED); if (src_mb) { - dec->consumed += s5p_mfc_get_consumed_stream(); + dec->consumed += mfc_get_consumed_stream(); mfc_debug(2, "[STREAM] header total size : %d, consumed : %lu\n", src_mb->vb.vb2_buf.planes[0].bytesused, dec->consumed); if ((dec->consumed > 0) && @@ -1121,8 +1121,8 @@ static int mfc_handle_seq_dec(struct s5p_mfc_ctx *ctx) } if (IS_VP9_DEC(ctx)) { - dec->color_range = s5p_mfc_get_color_range(); - dec->color_space = s5p_mfc_get_color_space(); + dec->color_range = mfc_get_color_range(); + dec->color_space = mfc_get_color_space(); mfc_debug(2, "color range: %d, color space: %d, It's valid for VP9\n", dec->color_range, dec->color_space); } @@ -1131,21 +1131,21 @@ static int mfc_handle_seq_dec(struct s5p_mfc_ctx *ctx) } /* Handle header encoder interrupt */ -static int mfc_handle_seq_enc(struct s5p_mfc_ctx *ctx) +static int __mfc_handle_seq_enc(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_enc *enc = ctx->enc_priv; - struct s5p_mfc_enc_params *p = &enc->params; - struct s5p_mfc_buf *dst_mb; + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + struct mfc_buf *dst_mb; int ret; - enc->header_size = s5p_mfc_get_enc_strm_size(); + enc->header_size = mfc_get_enc_strm_size(); mfc_debug(2, "[STREAM] encoded slice type: %d, header size: %d, display order: %d\n", - s5p_mfc_get_enc_slice_type(), enc->header_size, - s5p_mfc_get_enc_pic_count()); + mfc_get_enc_slice_type(), enc->header_size, + mfc_get_enc_pic_count()); if (IS_BPG_ENC(ctx)) { - dst_mb = s5p_mfc_get_buf(&ctx->buf_queue_lock, &ctx->dst_buf_queue, MFC_BUF_NO_TOUCH_USED); + dst_mb = mfc_get_buf(&ctx->buf_queue_lock, &ctx->dst_buf_queue, MFC_BUF_NO_TOUCH_USED); if (!dst_mb) { mfc_err_dev("no dst buffers\n"); return -EAGAIN; @@ -1161,66 +1161,66 @@ static int mfc_handle_seq_enc(struct s5p_mfc_ctx *ctx) } else { if ((p->seq_hdr_mode == V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) || (p->seq_hdr_mode == V4L2_MPEG_VIDEO_HEADER_MODE_AT_THE_READY)) { - dst_mb = s5p_mfc_get_del_buf(&ctx->buf_queue_lock, + dst_mb = mfc_get_del_buf(&ctx->buf_queue_lock, &ctx->dst_buf_queue, MFC_BUF_NO_TOUCH_USED); if (!dst_mb) { mfc_err_dev("no dst buffers\n"); return -EAGAIN; } - vb2_set_plane_payload(&dst_mb->vb.vb2_buf, 0, s5p_mfc_get_enc_strm_size()); + vb2_set_plane_payload(&dst_mb->vb.vb2_buf, 0, mfc_get_enc_strm_size()); vb2_buffer_done(&dst_mb->vb.vb2_buf, VB2_BUF_STATE_DONE); /* encoder dst buffer CFW UNPROT */ if (ctx->is_drm) { int index = dst_mb->vb.vb2_buf.index; - s5p_mfc_stream_unprotect(ctx, dst_mb, index); + mfc_stream_unprotect(ctx, dst_mb, index); } } } - ctx->dpb_count = s5p_mfc_get_enc_dpb_count(); - ctx->scratch_buf_size = s5p_mfc_get_enc_scratch_size(); + ctx->dpb_count = mfc_get_enc_dpb_count(); + ctx->scratch_buf_size = mfc_get_enc_scratch_size(); /* If the ROI is enabled at SEQ_START, clear ROI_ENABLE bit */ - s5p_mfc_clear_roi_enable(dev); + mfc_clear_roi_enable(dev); if (!ctx->codec_buffer_allocated) { mfc_debug(2, "[DRC] previous codec buffer is exist\n"); if (dev->has_mmcache && dev->mmcache.is_on_status) - s5p_mfc_invalidate_mmcache(dev); + mfc_invalidate_mmcache(dev); - s5p_mfc_release_codec_buffers(ctx); + mfc_release_codec_buffers(ctx); } - ret = s5p_mfc_alloc_codec_buffers(ctx); + ret = mfc_alloc_codec_buffers(ctx); if (ret) { mfc_err_ctx("Failed to allocate encoding buffers\n"); return ret; } - s5p_mfc_change_state(ctx, MFCINST_HEAD_PARSED); + mfc_change_state(ctx, MFCINST_HEAD_PARSED); return 0; } static inline int is_err_condition(unsigned int err) { - if (err == S5P_FIMV_ERR_NO_AVAILABLE_DPB || - err == S5P_FIMV_ERR_INSUFFICIENT_DPB_SIZE || - err == S5P_FIMV_ERR_INSUFFICIENT_NUM_DPB || - err == S5P_FIMV_ERR_INSUFFICIENT_MV_BUF_SIZE || - err == S5P_FIMV_ERR_INSUFFICIENT_SCRATCH_BUF_SIZE) + if (err == MFC_REG_ERR_NO_AVAILABLE_DPB || + err == MFC_REG_ERR_INSUFFICIENT_DPB_SIZE || + err == MFC_REG_ERR_INSUFFICIENT_NUM_DPB || + err == MFC_REG_ERR_INSUFFICIENT_MV_BUF_SIZE || + err == MFC_REG_ERR_INSUFFICIENT_SCRATCH_BUF_SIZE) return 1; return 0; } -irqreturn_t s5p_mfc_top_half_irq(int irq, void *priv) +irqreturn_t mfc_top_half_irq(int irq, void *priv) { - struct s5p_mfc_dev *dev = priv; - struct s5p_mfc_ctx *ctx; + struct mfc_dev *dev = priv; + struct mfc_ctx *ctx; unsigned int err; unsigned int reason; @@ -1230,13 +1230,13 @@ irqreturn_t s5p_mfc_top_half_irq(int irq, void *priv) return IRQ_WAKE_THREAD; } - reason = s5p_mfc_get_int_reason(); - err = s5p_mfc_get_int_err(); + reason = mfc_get_int_reason(); + err = mfc_get_int_err(); mfc_debug(2, "[c:%d] Int reason: %d (err: %d)\n", dev->curr_ctx, reason, err); MFC_TRACE_CTX("<< INT(top): %d\n", reason); - s5p_mfc_perf_measure_off(dev); + mfc_perf_measure_off(dev); return IRQ_WAKE_THREAD; } @@ -1247,7 +1247,7 @@ irqreturn_t s5p_mfc_top_half_irq(int irq, void *priv) * 1: NAL_START command * -1: Error */ -static inline int mfc_nal_q_irq(struct s5p_mfc_dev *dev, +static inline int __mfc_nal_q_irq(struct mfc_dev *dev, unsigned int reason, unsigned int err) { int ret = -1; @@ -1257,36 +1257,36 @@ static inline int mfc_nal_q_irq(struct s5p_mfc_dev *dev, EncoderOutputStr *pOutStr; switch (reason) { - case S5P_FIMV_R2H_CMD_QUEUE_DONE_RET: - pOutStr = s5p_mfc_nal_q_dequeue_out_buf(dev, + case MFC_REG_R2H_CMD_QUEUE_DONE_RET: + pOutStr = mfc_nal_q_dequeue_out_buf(dev, nal_q_handle->nal_q_out_handle, &errcode); if (pOutStr) { - if (s5p_mfc_nal_q_handle_out_buf(dev, pOutStr)) + if (mfc_nal_q_handle_out_buf(dev, pOutStr)) mfc_err_dev("[NALQ] Failed to handle out buf\n"); } else { mfc_err_dev("[NALQ] pOutStr is NULL\n"); } if (nal_q_handle->nal_q_exception) - s5p_mfc_set_bit(nal_q_handle->nal_q_out_handle->nal_q_ctx, + mfc_set_bit(nal_q_handle->nal_q_out_handle->nal_q_ctx, &dev->work_bits); - s5p_mfc_clear_int_sfr(); + mfc_clear_int_sfr(); if (!nal_q_handle->nal_q_exception) - s5p_mfc_nal_q_clock_off(dev, nal_q_handle); + mfc_nal_q_clock_off(dev, nal_q_handle); ret = 0; break; - case S5P_FIMV_R2H_CMD_COMPLETE_QUEUE_RET: - s5p_mfc_watchdog_stop_tick(dev); + case MFC_REG_R2H_CMD_COMPLETE_QUEUE_RET: + mfc_watchdog_stop_tick(dev); nal_q_handle->nal_q_state = NAL_Q_STATE_CREATED; MFC_TRACE_DEV("** NAL Q state : %d\n", nal_q_handle->nal_q_state); mfc_debug(2, "[NALQ] return to created state\n"); - s5p_mfc_nal_q_cleanup_queue(dev); - s5p_mfc_nal_q_cleanup_clock(dev); - s5p_mfc_clear_int_sfr(); - s5p_mfc_pm_clock_off(dev); - s5p_mfc_wake_up_dev(dev, reason, err); + mfc_nal_q_cleanup_queue(dev); + mfc_nal_q_cleanup_clock(dev); + mfc_clear_int_sfr(); + mfc_pm_clock_off(dev); + mfc_wake_up_dev(dev, reason, err); ret = 0; break; @@ -1295,7 +1295,7 @@ static inline int mfc_nal_q_irq(struct s5p_mfc_dev *dev, nal_q_handle->nal_q_state == NAL_Q_STATE_STOPPED) { mfc_err_dev("[NALQ] Should not be here! state: %d, int reason : %d\n", nal_q_handle->nal_q_state, reason); - s5p_mfc_clear_int_sfr(); + mfc_clear_int_sfr(); ret = -1; } else { @@ -1312,35 +1312,35 @@ static inline int mfc_nal_q_irq(struct s5p_mfc_dev *dev, return ret; } -static inline int mfc_handle_done_frame(struct s5p_mfc_ctx *ctx, +static inline int __mfc_handle_done_frame(struct mfc_ctx *ctx, unsigned int reason, unsigned int err) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_enc *enc = NULL; + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = NULL; if (ctx->type == MFCINST_DECODER) { if (ctx->state == MFCINST_SPECIAL_PARSING_NAL) { - s5p_mfc_clear_int_sfr(); - s5p_mfc_pm_clock_off(dev); - s5p_mfc_clear_bit(ctx->num, &dev->work_bits); - s5p_mfc_change_state(ctx, MFCINST_RUNNING); - s5p_mfc_wake_up_ctx(ctx, reason, err); + mfc_clear_int_sfr(); + mfc_pm_clock_off(dev); + mfc_clear_bit(ctx->num, &dev->work_bits); + mfc_change_state(ctx, MFCINST_RUNNING); + mfc_wake_up_ctx(ctx, reason, err); return 0; } - mfc_handle_frame(ctx, reason, err); + __mfc_handle_frame(ctx, reason, err); } else if (ctx->type == MFCINST_ENCODER) { if (ctx->otf_handle) { - s5p_mfc_otf_handle_stream(ctx); + mfc_otf_handle_stream(ctx); return 1; } enc = ctx->enc_priv; - if (reason == S5P_FIMV_R2H_CMD_SLICE_DONE_RET) { + if (reason == MFC_REG_R2H_CMD_SLICE_DONE_RET) { dev->preempt_ctx = ctx->num; enc->buf_full = 0; enc->in_slice = 1; - } else if (reason == S5P_FIMV_R2H_CMD_ENC_BUFFER_FULL_RET) { + } else if (reason == MFC_REG_R2H_CMD_ENC_BUFFER_FULL_RET) { mfc_err_ctx("stream buffer size(%d) isn't enough\n", - s5p_mfc_get_enc_strm_size()); + mfc_get_enc_strm_size()); dev->preempt_ctx = ctx->num; enc->buf_full = 1; enc->in_slice = 0; @@ -1348,112 +1348,112 @@ static inline int mfc_handle_done_frame(struct s5p_mfc_ctx *ctx, enc->buf_full = 0; enc->in_slice = 0; } - mfc_handle_stream(ctx); + __mfc_handle_stream(ctx); } return 1; } -static inline void mfc_handle_nal_abort(struct s5p_mfc_ctx *ctx) +static inline void __mfc_handle_nal_abort(struct mfc_ctx *ctx) { - struct s5p_mfc_enc *enc = ctx->enc_priv; + struct mfc_enc *enc = ctx->enc_priv; if (ctx->type == MFCINST_ENCODER) { - s5p_mfc_change_state(ctx, MFCINST_RUNNING_BUF_FULL); + mfc_change_state(ctx, MFCINST_RUNNING_BUF_FULL); enc->buf_full = 0; if (IS_VP8_ENC(ctx)) mfc_err_ctx("stream buffer size isn't enough\n"); - mfc_handle_stream(ctx); + __mfc_handle_stream(ctx); } else { - s5p_mfc_change_state(ctx, MFCINST_ABORT); + mfc_change_state(ctx, MFCINST_ABORT); } } -static int mfc_irq_dev(struct s5p_mfc_dev *dev, unsigned int reason, unsigned int err) +static int __mfc_irq_dev(struct mfc_dev *dev, unsigned int reason, unsigned int err) { /* Stop the timeout watchdog */ - if (reason != S5P_FIMV_R2H_CMD_FW_STATUS_RET) - s5p_mfc_watchdog_stop_tick(dev); + if (reason != MFC_REG_R2H_CMD_FW_STATUS_RET) + mfc_watchdog_stop_tick(dev); switch (reason) { - case S5P_FIMV_R2H_CMD_CACHE_FLUSH_RET: - case S5P_FIMV_R2H_CMD_SYS_INIT_RET: - case S5P_FIMV_R2H_CMD_FW_STATUS_RET: - case S5P_FIMV_R2H_CMD_SLEEP_RET: - case S5P_FIMV_R2H_CMD_WAKEUP_RET: - s5p_mfc_clear_int_sfr(); - s5p_mfc_wake_up_dev(dev, reason, err); + case MFC_REG_R2H_CMD_CACHE_FLUSH_RET: + case MFC_REG_R2H_CMD_SYS_INIT_RET: + case MFC_REG_R2H_CMD_FW_STATUS_RET: + case MFC_REG_R2H_CMD_SLEEP_RET: + case MFC_REG_R2H_CMD_WAKEUP_RET: + mfc_clear_int_sfr(); + mfc_wake_up_dev(dev, reason, err); return 0; } return 1; } -static int mfc_irq_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err) +static int __mfc_irq_ctx(struct mfc_ctx *ctx, unsigned int reason, unsigned int err) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; switch (reason) { - case S5P_FIMV_R2H_CMD_ERR_RET: + case MFC_REG_R2H_CMD_ERR_RET: if (ctx->otf_handle) { - s5p_mfc_otf_handle_error(ctx, reason, err); + mfc_otf_handle_error(ctx, reason, err); break; } /* An error has occured */ if (ctx->state == MFCINST_RUNNING || ctx->state == MFCINST_ABORT) { - if ((s5p_mfc_get_err(err) >= S5P_FIMV_ERR_WARNINGS_START) && - (s5p_mfc_get_err(err) <= S5P_FIMV_ERR_WARNINGS_END)) - mfc_handle_frame(ctx, reason, err); + if ((mfc_get_err(err) >= MFC_REG_ERR_WARNINGS_START) && + (mfc_get_err(err) <= MFC_REG_ERR_WARNINGS_END)) + __mfc_handle_frame(ctx, reason, err); else - mfc_handle_frame_error(ctx, reason, err); + __mfc_handle_frame_error(ctx, reason, err); } else { - mfc_handle_error(ctx, reason, err); + __mfc_handle_error(ctx, reason, err); } break; - case S5P_FIMV_R2H_CMD_SLICE_DONE_RET: - case S5P_FIMV_R2H_CMD_FIELD_DONE_RET: - case S5P_FIMV_R2H_CMD_FRAME_DONE_RET: - case S5P_FIMV_R2H_CMD_ENC_BUFFER_FULL_RET: - return mfc_handle_done_frame(ctx, reason, err); - case S5P_FIMV_R2H_CMD_COMPLETE_SEQ_RET: + case MFC_REG_R2H_CMD_SLICE_DONE_RET: + case MFC_REG_R2H_CMD_FIELD_DONE_RET: + case MFC_REG_R2H_CMD_FRAME_DONE_RET: + case MFC_REG_R2H_CMD_ENC_BUFFER_FULL_RET: + return __mfc_handle_done_frame(ctx, reason, err); + case MFC_REG_R2H_CMD_COMPLETE_SEQ_RET: if (ctx->type == MFCINST_ENCODER) { - mfc_handle_stream(ctx); - s5p_mfc_change_state(ctx, MFCINST_RUNNING); + __mfc_handle_stream(ctx); + mfc_change_state(ctx, MFCINST_RUNNING); } else if (ctx->type == MFCINST_DECODER) { - return mfc_handle_done_frame(ctx, reason, err); + return __mfc_handle_done_frame(ctx, reason, err); } break; - case S5P_FIMV_R2H_CMD_SEQ_DONE_RET: + case MFC_REG_R2H_CMD_SEQ_DONE_RET: if (ctx->type == MFCINST_ENCODER) { if (ctx->otf_handle) { - s5p_mfc_otf_handle_seq(ctx); + mfc_otf_handle_seq(ctx); break; } - mfc_handle_seq_enc(ctx); + __mfc_handle_seq_enc(ctx); } else if (ctx->type == MFCINST_DECODER) { - mfc_handle_seq_dec(ctx); + __mfc_handle_seq_dec(ctx); } break; - case S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET: - ctx->inst_no = s5p_mfc_get_inst_no(); - s5p_mfc_change_state(ctx, MFCINST_GOT_INST); + case MFC_REG_R2H_CMD_OPEN_INSTANCE_RET: + ctx->inst_no = mfc_get_inst_no(); + mfc_change_state(ctx, MFCINST_GOT_INST); break; - case S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET: - s5p_mfc_change_state(ctx, MFCINST_FREE); + case MFC_REG_R2H_CMD_CLOSE_INSTANCE_RET: + mfc_change_state(ctx, MFCINST_FREE); break; - case S5P_FIMV_R2H_CMD_NAL_ABORT_RET: - mfc_handle_nal_abort(ctx); + case MFC_REG_R2H_CMD_NAL_ABORT_RET: + __mfc_handle_nal_abort(ctx); break; - case S5P_FIMV_R2H_CMD_DPB_FLUSH_RET: - s5p_mfc_change_state(ctx, MFCINST_ABORT); + case MFC_REG_R2H_CMD_DPB_FLUSH_RET: + mfc_change_state(ctx, MFCINST_ABORT); break; - case S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET: + case MFC_REG_R2H_CMD_INIT_BUFFERS_RET: if (err != 0) { mfc_err_ctx("INIT_BUFFERS_RET error: %d\n", err); break; } - s5p_mfc_change_state(ctx, MFCINST_RUNNING); + mfc_change_state(ctx, MFCINST_RUNNING); if (ctx->type == MFCINST_DECODER) { if (ctx->wait_state == WAIT_DECODING) { ctx->wait_state = WAIT_INITBUF_DONE; @@ -1471,10 +1471,10 @@ static int mfc_irq_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned in } /* Interrupt processing */ -irqreturn_t s5p_mfc_irq(int irq, void *priv) +irqreturn_t mfc_irq(int irq, void *priv) { - struct s5p_mfc_dev *dev = priv; - struct s5p_mfc_ctx *ctx; + struct mfc_dev *dev = priv; + struct mfc_ctx *ctx; unsigned int reason; unsigned int err; int ret = -1; @@ -1486,35 +1486,35 @@ irqreturn_t s5p_mfc_irq(int irq, void *priv) goto irq_end; } - if (s5p_mfc_pm_get_pwr_ref_cnt(dev) == 0) { + if (mfc_pm_get_pwr_ref_cnt(dev) == 0) { mfc_err_dev("no mfc power on\n"); call_dop(dev, dump_and_stop_debug_mode, dev); goto irq_end; } /* Get the reason of interrupt and the error code */ - reason = s5p_mfc_get_int_reason(); - err = s5p_mfc_get_int_err(); + reason = mfc_get_int_reason(); + err = mfc_get_int_err(); mfc_debug(1, "Int reason: %d (err: %d)\n", reason, err); MFC_TRACE_DEV("<< INT: %d\n", reason); dev->preempt_ctx = MFC_NO_INSTANCE_SET; - if (dbg_enable && (reason != S5P_FIMV_R2H_CMD_QUEUE_DONE_RET)) - s5p_mfc_dbg_disable(dev); + if (dbg_enable && (reason != MFC_REG_R2H_CMD_QUEUE_DONE_RET)) + mfc_dbg_disable(dev); - if ((sfr_dump & MFC_DUMP_ERR_INT) && (reason == S5P_FIMV_R2H_CMD_ERR_RET)) + if ((sfr_dump & MFC_DUMP_ERR_INT) && (reason == MFC_REG_R2H_CMD_ERR_RET)) call_dop(dev, dump_regs, dev); if ((sfr_dump & MFC_DUMP_WARN_INT) && - (err && (reason != S5P_FIMV_R2H_CMD_ERR_RET))) + (err && (reason != MFC_REG_R2H_CMD_ERR_RET))) call_dop(dev, dump_regs, dev); if (is_err_condition(err)) call_dop(dev, dump_and_stop_debug_mode, dev); if (dev->nal_q_handle) { - ret = mfc_nal_q_irq(dev, reason, err); + ret = __mfc_nal_q_irq(dev, reason, err); if (ret == 0) { mfc_debug(2, "[NALQ] command was handled\n"); goto irq_end; @@ -1527,36 +1527,36 @@ irqreturn_t s5p_mfc_irq(int irq, void *priv) } } - ret = mfc_irq_dev(dev, reason, err); + ret = __mfc_irq_dev(dev, reason, err); if (!ret) goto irq_end; ctx = dev->ctx[dev->curr_ctx]; if (!ctx) { mfc_err_dev("no mfc context to run\n"); - s5p_mfc_clear_int_sfr(); - s5p_mfc_pm_clock_off(dev); + mfc_clear_int_sfr(); + mfc_pm_clock_off(dev); goto irq_end; } - ret = mfc_irq_ctx(ctx, reason, err); + ret = __mfc_irq_ctx(ctx, reason, err); if (!ret) goto irq_end; /* clean-up interrupt */ - s5p_mfc_clear_int_sfr(); + mfc_clear_int_sfr(); - if ((ctx->state != MFCINST_RES_CHANGE_INIT) && (s5p_mfc_ctx_ready(ctx) == 0)) - s5p_mfc_clear_bit(ctx->num, &dev->work_bits); + if ((ctx->state != MFCINST_RES_CHANGE_INIT) && (mfc_ctx_ready(ctx) == 0)) + mfc_clear_bit(ctx->num, &dev->work_bits); if (ctx->otf_handle) { - if (s5p_mfc_otf_ctx_ready(ctx)) - s5p_mfc_set_bit(ctx->num, &dev->work_bits); + if (mfc_otf_ctx_ready(ctx)) + mfc_set_bit(ctx->num, &dev->work_bits); else - s5p_mfc_clear_bit(ctx->num, &dev->work_bits); + mfc_clear_bit(ctx->num, &dev->work_bits); } - s5p_mfc_hwlock_handler_irq(dev, ctx, reason, err); + mfc_hwlock_handler_irq(dev, ctx, reason, err); irq_end: mfc_debug_leave(); diff --git a/drivers/media/platform/exynos/mfc/mfc_irq.h b/drivers/media/platform/exynos/mfc/mfc_irq.h index 51ff3afecff1..872596a2653c 100644 --- a/drivers/media/platform/exynos/mfc/mfc_irq.h +++ b/drivers/media/platform/exynos/mfc/mfc_irq.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_irq.h + * drivers/media/platform/exynos/mfc/mfc_irq.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -19,14 +19,14 @@ #include "mfc_utils.h" -irqreturn_t s5p_mfc_top_half_irq(int irq, void *priv); -irqreturn_t s5p_mfc_irq(int irq, void *priv); +irqreturn_t mfc_top_half_irq(int irq, void *priv); +irqreturn_t mfc_irq(int irq, void *priv); -static inline void s5p_mfc_handle_force_change_status(struct s5p_mfc_ctx *ctx) +static inline void mfc_handle_force_change_status(struct mfc_ctx *ctx) { if (ctx->state != MFCINST_ABORT && ctx->state != MFCINST_HEAD_PARSED && ctx->state != MFCINST_RES_CHANGE_FLUSH) - s5p_mfc_change_state(ctx, MFCINST_RUNNING); + mfc_change_state(ctx, MFCINST_RUNNING); } #endif /* __MFC_IRQ_H */ diff --git a/drivers/media/platform/exynos/mfc/mfc_macros.h b/drivers/media/platform/exynos/mfc/mfc_macros.h index b82cde483312..8151af723f7e 100644 --- a/drivers/media/platform/exynos/mfc/mfc_macros.h +++ b/drivers/media/platform/exynos/mfc/mfc_macros.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_macros.h + * drivers/media/platform/exynos/mfc/mfc_macros.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ diff --git a/drivers/media/platform/exynos/mfc/mfc_mem.c b/drivers/media/platform/exynos/mfc/mfc_mem.c index f09819eb3de4..c88efba09c5e 100644 --- a/drivers/media/platform/exynos/mfc/mfc_mem.c +++ b/drivers/media/platform/exynos/mfc/mfc_mem.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_mem.c + * drivers/media/platform/exynos/mfc/mfc_mem.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -12,28 +12,28 @@ #include "mfc_mem.h" -struct vb2_mem_ops *s5p_mfc_mem_ops(void) +struct vb2_mem_ops *mfc_mem_ops(void) { return (struct vb2_mem_ops *)&vb2_dma_sg_memops; } -void s5p_mfc_mem_clean(struct s5p_mfc_dev *dev, - struct s5p_mfc_special_buf *special_buf, +void mfc_mem_clean(struct mfc_dev *dev, + struct mfc_special_buf *special_buf, off_t offset, size_t size) { __dma_map_area(special_buf->vaddr + offset, size, DMA_TO_DEVICE); return; } -void s5p_mfc_mem_invalidate(struct s5p_mfc_dev *dev, - struct s5p_mfc_special_buf *special_buf, +void mfc_mem_invalidate(struct mfc_dev *dev, + struct mfc_special_buf *special_buf, off_t offset, size_t size) { __dma_map_area(special_buf->vaddr + offset, size, DMA_FROM_DEVICE); return; } -int s5p_mfc_mem_get_user_shared_handle(struct s5p_mfc_ctx *ctx, +int mfc_mem_get_user_shared_handle(struct mfc_ctx *ctx, struct mfc_user_shared_handle *handle) { int ret = 0; @@ -64,7 +64,7 @@ import_dma_fail: return ret; } -void s5p_mfc_mem_cleanup_user_shared_handle(struct s5p_mfc_ctx *ctx, +void mfc_mem_cleanup_user_shared_handle(struct mfc_ctx *ctx, struct mfc_user_shared_handle *handle) { if (handle->vaddr) @@ -77,10 +77,10 @@ void s5p_mfc_mem_cleanup_user_shared_handle(struct s5p_mfc_ctx *ctx, handle->fd = -1; } -int s5p_mfc_mem_ion_alloc(struct s5p_mfc_dev *dev, - struct s5p_mfc_special_buf *special_buf) +int mfc_mem_ion_alloc(struct mfc_dev *dev, + struct mfc_special_buf *special_buf) { - struct s5p_mfc_ctx *ctx = dev->ctx[dev->curr_ctx]; + struct mfc_ctx *ctx = dev->ctx[dev->curr_ctx]; int flag; const char *heapname; @@ -169,8 +169,8 @@ err_ion_alloc: return -ENOMEM; } -void s5p_mfc_mem_ion_free(struct s5p_mfc_dev *dev, - struct s5p_mfc_special_buf *special_buf) +void mfc_mem_ion_free(struct mfc_dev *dev, + struct mfc_special_buf *special_buf) { if (special_buf->vaddr) dma_buf_vunmap(special_buf->dma_buf, special_buf->vaddr); @@ -191,7 +191,7 @@ void s5p_mfc_mem_ion_free(struct s5p_mfc_dev *dev, special_buf->vaddr = NULL; } -void s5p_mfc_bufcon_put_daddr(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *mfc_buf, int plane) +void mfc_bufcon_put_daddr(struct mfc_ctx *ctx, struct mfc_buf *mfc_buf, int plane) { int i; @@ -212,11 +212,11 @@ void s5p_mfc_bufcon_put_daddr(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *mfc_b } } -int s5p_mfc_bufcon_get_daddr(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *mfc_buf, +int mfc_bufcon_get_daddr(struct mfc_ctx *ctx, struct mfc_buf *mfc_buf, struct dma_buf *bufcon_dmabuf, int plane) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_raw_info *raw = &ctx->raw_buf; + struct mfc_dev *dev = ctx->dev; + struct mfc_raw_info *raw = &ctx->raw_buf; int i, j = 0; u32 mask; @@ -269,6 +269,6 @@ int s5p_mfc_bufcon_get_daddr(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *mfc_bu return 0; err_get_daddr: - s5p_mfc_bufcon_put_daddr(ctx, mfc_buf, plane); + mfc_bufcon_put_daddr(ctx, mfc_buf, plane); return -1; } diff --git a/drivers/media/platform/exynos/mfc/mfc_mem.h b/drivers/media/platform/exynos/mfc/mfc_mem.h index 5a3a65b51fef..5ac0fdd081a6 100644 --- a/drivers/media/platform/exynos/mfc/mfc_mem.h +++ b/drivers/media/platform/exynos/mfc/mfc_mem.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_mem.h + * drivers/media/platform/exynos/mfc/mfc_mem.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -19,7 +19,7 @@ * while mmaping */ #define DST_QUEUE_OFF_BASE (TASK_SIZE / 2) -static inline dma_addr_t s5p_mfc_mem_get_daddr_vb( +static inline dma_addr_t mfc_mem_get_daddr_vb( struct vb2_buffer *vb, unsigned int n) { dma_addr_t addr = 0; @@ -30,32 +30,32 @@ static inline dma_addr_t s5p_mfc_mem_get_daddr_vb( return addr; } -static inline int s5p_mfc_bufcon_get_buf_count(struct dma_buf *dmabuf) +static inline int mfc_bufcon_get_buf_count(struct dma_buf *dmabuf) { return dmabuf_container_get_count(dmabuf); } -struct vb2_mem_ops *s5p_mfc_mem_ops(void); +struct vb2_mem_ops *mfc_mem_ops(void); -void s5p_mfc_mem_set_cacheable(bool cacheable); -void s5p_mfc_mem_clean(struct s5p_mfc_dev *dev, - struct s5p_mfc_special_buf *specail_buf, +void mfc_mem_set_cacheable(bool cacheable); +void mfc_mem_clean(struct mfc_dev *dev, + struct mfc_special_buf *specail_buf, off_t offset, size_t size); -void s5p_mfc_mem_invalidate(struct s5p_mfc_dev *dev, - struct s5p_mfc_special_buf *specail_buf, +void mfc_mem_invalidate(struct mfc_dev *dev, + struct mfc_special_buf *specail_buf, off_t offset, size_t size); -int s5p_mfc_mem_get_user_shared_handle(struct s5p_mfc_ctx *ctx, +int mfc_mem_get_user_shared_handle(struct mfc_ctx *ctx, struct mfc_user_shared_handle *handle); -void s5p_mfc_mem_cleanup_user_shared_handle(struct s5p_mfc_ctx *ctx, +void mfc_mem_cleanup_user_shared_handle(struct mfc_ctx *ctx, struct mfc_user_shared_handle *handle); -int s5p_mfc_mem_ion_alloc(struct s5p_mfc_dev *dev, - struct s5p_mfc_special_buf *special_buf); -void s5p_mfc_mem_ion_free(struct s5p_mfc_dev *dev, - struct s5p_mfc_special_buf *special_buf); +int mfc_mem_ion_alloc(struct mfc_dev *dev, + struct mfc_special_buf *special_buf); +void mfc_mem_ion_free(struct mfc_dev *dev, + struct mfc_special_buf *special_buf); -void s5p_mfc_bufcon_put_daddr(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *mfc_buf, int plane); -int s5p_mfc_bufcon_get_daddr(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *mfc_buf, +void mfc_bufcon_put_daddr(struct mfc_ctx *ctx, struct mfc_buf *mfc_buf, int plane); +int mfc_bufcon_get_daddr(struct mfc_ctx *ctx, struct mfc_buf *mfc_buf, struct dma_buf *bufcon_dmabuf, int plane); #endif /* __MFC_MEM_H */ diff --git a/drivers/media/platform/exynos/mfc/mfc_mmcache.c b/drivers/media/platform/exynos/mfc/mfc_mmcache.c index 7385139abebb..3587d8bc27c7 100644 --- a/drivers/media/platform/exynos/mfc/mfc_mmcache.c +++ b/drivers/media/platform/exynos/mfc/mfc_mmcache.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_mmcache.c + * drivers/media/platform/exynos/mfc/mfc_mmcache.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -35,7 +35,7 @@ static const unsigned char mmcache_SFR_0x0040[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; -static void mmcache_print_config(struct s5p_mfc_dev *dev) +static void mmcache_print_config(struct mfc_dev *dev) { void __iomem *addr; unsigned int size; @@ -58,7 +58,7 @@ static void mmcache_print_config(struct s5p_mfc_dev *dev) mfc_debug_leave(); } -static void mmcache_set_config(struct s5p_mfc_dev *dev) +static void mmcache_set_config(struct mfc_dev *dev) { unsigned int data, i, size; const unsigned int *sfr_dump; @@ -86,7 +86,7 @@ static void mmcache_set_config(struct s5p_mfc_dev *dev) mfc_debug_leave(); } -static void mmcache_reset_config(struct s5p_mfc_dev *dev) +static void mmcache_reset_config(struct mfc_dev *dev) { void __iomem *addr; unsigned int data; @@ -109,7 +109,7 @@ static void mmcache_reset_config(struct s5p_mfc_dev *dev) mfc_debug_leave(); } -static void mmcache_update_master_grp(struct s5p_mfc_dev *dev) +static void mmcache_update_master_grp(struct mfc_dev *dev) { void __iomem *addr; unsigned int data; @@ -132,7 +132,7 @@ static void mmcache_update_master_grp(struct s5p_mfc_dev *dev) mfc_debug_leave(); } -static void mmcache_enable_clock_gating(struct s5p_mfc_dev *dev) +static void mmcache_enable_clock_gating(struct mfc_dev *dev) { void __iomem *addr; unsigned int data; @@ -155,7 +155,7 @@ static void mmcache_enable_clock_gating(struct s5p_mfc_dev *dev) mfc_debug_leave(); } -void s5p_mfc_mmcache_enable(struct s5p_mfc_dev *dev) +void mfc_mmcache_enable(struct mfc_dev *dev) { mfc_debug_enter(); @@ -174,7 +174,7 @@ void s5p_mfc_mmcache_enable(struct s5p_mfc_dev *dev) mfc_debug_leave(); } -void s5p_mfc_mmcache_disable(struct s5p_mfc_dev *dev) +void mfc_mmcache_disable(struct mfc_dev *dev) { mfc_debug_enter(); @@ -188,7 +188,7 @@ void s5p_mfc_mmcache_disable(struct s5p_mfc_dev *dev) mfc_debug_leave(); } -void s5p_mfc_invalidate_mmcache(struct s5p_mfc_dev *dev) +void mfc_invalidate_mmcache(struct mfc_dev *dev) { void __iomem *addr; unsigned int data; diff --git a/drivers/media/platform/exynos/mfc/mfc_mmcache.h b/drivers/media/platform/exynos/mfc/mfc_mmcache.h index c9f67af24d8d..bcfa770e835e 100644 --- a/drivers/media/platform/exynos/mfc/mfc_mmcache.h +++ b/drivers/media/platform/exynos/mfc/mfc_mmcache.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_mmcache.h + * drivers/media/platform/exynos/mfc/mfc_mmcache.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -29,11 +29,11 @@ /* Need HW lock to call this function */ -void s5p_mfc_mmcache_enable(struct s5p_mfc_dev *dev); -void s5p_mfc_mmcache_disable(struct s5p_mfc_dev *dev); +void mfc_mmcache_enable(struct mfc_dev *dev); +void mfc_mmcache_disable(struct mfc_dev *dev); /* Need HW lock to call this function */ -void s5p_mfc_invalidate_mmcache(struct s5p_mfc_dev *dev); +void mfc_invalidate_mmcache(struct mfc_dev *dev); #endif /* __MFC_MMCACHE_H */ diff --git a/drivers/media/platform/exynos/mfc/mfc_nal_q.c b/drivers/media/platform/exynos/mfc/mfc_nal_q.c index 74d330bf32c1..870620e10792 100644 --- a/drivers/media/platform/exynos/mfc/mfc_nal_q.c +++ b/drivers/media/platform/exynos/mfc/mfc_nal_q.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_nal_q.c + * drivers/media/platform/exynos/mfc/mfc_nal_q.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -25,12 +25,12 @@ #include "mfc_mem.h" #define CBR_I_LIMIT_MAX 5 -int s5p_mfc_nal_q_check_enable(struct s5p_mfc_dev *dev) +int mfc_nal_q_check_enable(struct mfc_dev *dev) { - struct s5p_mfc_ctx *temp_ctx; - struct s5p_mfc_dec *dec = NULL; - struct s5p_mfc_enc *enc = NULL; - struct s5p_mfc_enc_params *p = NULL; + struct mfc_ctx *temp_ctx; + struct mfc_dec *dec = NULL; + struct mfc_enc *enc = NULL; + struct mfc_enc_params *p = NULL; int i; mfc_debug_enter(); @@ -58,7 +58,7 @@ int s5p_mfc_nal_q_check_enable(struct s5p_mfc_dev *dev) return 0; } /* NAL-Q can't use the command about last frame */ - if (s5p_mfc_is_last_frame(temp_ctx) == 1) { + if (mfc_is_last_frame(temp_ctx) == 1) { mfc_debug(2, "There is a last frame. index: %d\n", i); return 0; } @@ -123,7 +123,7 @@ int s5p_mfc_nal_q_check_enable(struct s5p_mfc_dev *dev) return 1; } -void s5p_mfc_nal_q_clock_on(struct s5p_mfc_dev *dev, nal_queue_handle *nal_q_handle) +void mfc_nal_q_clock_on(struct mfc_dev *dev, nal_queue_handle *nal_q_handle) { unsigned long flags; @@ -135,7 +135,7 @@ void s5p_mfc_nal_q_clock_on(struct s5p_mfc_dev *dev, nal_queue_handle *nal_q_han dev->continue_clock_on, nal_q_handle->nal_q_clk_cnt); if (!dev->continue_clock_on && !nal_q_handle->nal_q_clk_cnt) - s5p_mfc_pm_clock_on(dev); + mfc_pm_clock_on(dev); nal_q_handle->nal_q_clk_cnt++; dev->continue_clock_on = false; @@ -147,7 +147,7 @@ void s5p_mfc_nal_q_clock_on(struct s5p_mfc_dev *dev, nal_queue_handle *nal_q_han mfc_debug_leave(); } -void s5p_mfc_nal_q_clock_off(struct s5p_mfc_dev *dev, nal_queue_handle *nal_q_handle) +void mfc_nal_q_clock_off(struct mfc_dev *dev, nal_queue_handle *nal_q_handle) { unsigned long flags; @@ -165,7 +165,7 @@ void s5p_mfc_nal_q_clock_off(struct s5p_mfc_dev *dev, nal_queue_handle *nal_q_ha nal_q_handle->nal_q_clk_cnt--; if (!nal_q_handle->nal_q_clk_cnt) - s5p_mfc_pm_clock_off(dev); + mfc_pm_clock_off(dev); mfc_debug(2, "[NALQ] nal_q_clk_cnt = %d\n", nal_q_handle->nal_q_clk_cnt); @@ -174,7 +174,7 @@ void s5p_mfc_nal_q_clock_off(struct s5p_mfc_dev *dev, nal_queue_handle *nal_q_ha mfc_debug_leave(); } -void s5p_mfc_nal_q_cleanup_clock(struct s5p_mfc_dev *dev) +void mfc_nal_q_cleanup_clock(struct mfc_dev *dev) { unsigned long flags; @@ -189,7 +189,7 @@ void s5p_mfc_nal_q_cleanup_clock(struct s5p_mfc_dev *dev) mfc_debug_leave(); } -static int mfc_nal_q_find_ctx(struct s5p_mfc_dev *dev, EncoderOutputStr *pOutputStr) +static int __mfc_nal_q_find_ctx(struct mfc_dev *dev, EncoderOutputStr *pOutputStr) { int i; @@ -205,7 +205,7 @@ static int mfc_nal_q_find_ctx(struct s5p_mfc_dev *dev, EncoderOutputStr *pOutput return -1; } -static nal_queue_in_handle* mfc_nal_q_create_in_q(struct s5p_mfc_dev *dev, +static nal_queue_in_handle* __mfc_nal_q_create_in_q(struct mfc_dev *dev, nal_queue_handle *nal_q_handle) { nal_queue_in_handle *nal_q_in_handle; @@ -226,7 +226,7 @@ static nal_queue_in_handle* mfc_nal_q_create_in_q(struct s5p_mfc_dev *dev, nal_q_in_handle->nal_q_handle = nal_q_handle; nal_q_in_handle->in_buf.buftype = MFCBUF_NORMAL; nal_q_in_handle->in_buf.size = NAL_Q_IN_ENTRY_SIZE * (NAL_Q_IN_QUEUE_SIZE + 2); - if (s5p_mfc_mem_ion_alloc(dev, &nal_q_in_handle->in_buf)) { + if (mfc_mem_ion_alloc(dev, &nal_q_in_handle->in_buf)) { mfc_err_dev("[NALQ] failed to get memory\n"); kfree(nal_q_in_handle); return NULL; @@ -238,7 +238,7 @@ static nal_queue_in_handle* mfc_nal_q_create_in_q(struct s5p_mfc_dev *dev, return nal_q_in_handle; } -static nal_queue_out_handle* mfc_nal_q_create_out_q(struct s5p_mfc_dev *dev, +static nal_queue_out_handle* __mfc_nal_q_create_out_q(struct mfc_dev *dev, nal_queue_handle *nal_q_handle) { nal_queue_out_handle *nal_q_out_handle; @@ -259,7 +259,7 @@ static nal_queue_out_handle* mfc_nal_q_create_out_q(struct s5p_mfc_dev *dev, nal_q_out_handle->nal_q_handle = nal_q_handle; nal_q_out_handle->out_buf.buftype = MFCBUF_NORMAL; nal_q_out_handle->out_buf.size = NAL_Q_OUT_ENTRY_SIZE * (NAL_Q_OUT_QUEUE_SIZE + 2); - if (s5p_mfc_mem_ion_alloc(dev, &nal_q_out_handle->out_buf)) { + if (mfc_mem_ion_alloc(dev, &nal_q_out_handle->out_buf)) { mfc_err_dev("[NALQ] failed to get memory\n"); kfree(nal_q_out_handle); return NULL; @@ -271,7 +271,7 @@ static nal_queue_out_handle* mfc_nal_q_create_out_q(struct s5p_mfc_dev *dev, return nal_q_out_handle; } -static int mfc_nal_q_destroy_in_q(struct s5p_mfc_dev *dev, +static int __mfc_nal_q_destroy_in_q(struct mfc_dev *dev, nal_queue_in_handle *nal_q_in_handle) { mfc_debug_enter(); @@ -279,7 +279,7 @@ static int mfc_nal_q_destroy_in_q(struct s5p_mfc_dev *dev, if (!nal_q_in_handle) return -EINVAL; - s5p_mfc_mem_ion_free(dev, &nal_q_in_handle->in_buf); + mfc_mem_ion_free(dev, &nal_q_in_handle->in_buf); if (nal_q_in_handle) kfree(nal_q_in_handle); @@ -288,7 +288,7 @@ static int mfc_nal_q_destroy_in_q(struct s5p_mfc_dev *dev, return 0; } -static int mfc_nal_q_destroy_out_q(struct s5p_mfc_dev *dev, +static int __mfc_nal_q_destroy_out_q(struct mfc_dev *dev, nal_queue_out_handle *nal_q_out_handle) { mfc_debug_enter(); @@ -296,7 +296,7 @@ static int mfc_nal_q_destroy_out_q(struct s5p_mfc_dev *dev, if (!nal_q_out_handle) return -EINVAL; - s5p_mfc_mem_ion_free(dev, &nal_q_out_handle->out_buf); + mfc_mem_ion_free(dev, &nal_q_out_handle->out_buf); if (nal_q_out_handle) kfree(nal_q_out_handle); @@ -306,9 +306,9 @@ static int mfc_nal_q_destroy_out_q(struct s5p_mfc_dev *dev, } /* - * This function should be called after s5p_mfc_alloc_firmware() being called. + * This function should be called after mfc_alloc_firmware() being called. */ -nal_queue_handle *s5p_mfc_nal_q_create(struct s5p_mfc_dev *dev) +nal_queue_handle *mfc_nal_q_create(struct mfc_dev *dev) { nal_queue_handle *nal_q_handle; @@ -325,7 +325,7 @@ nal_queue_handle *s5p_mfc_nal_q_create(struct s5p_mfc_dev *dev) return NULL; } - nal_q_handle->nal_q_in_handle = mfc_nal_q_create_in_q(dev, nal_q_handle); + nal_q_handle->nal_q_in_handle = __mfc_nal_q_create_in_q(dev, nal_q_handle); if (!nal_q_handle->nal_q_in_handle) { kfree(nal_q_handle); mfc_err_dev("[NALQ] no nal_q_in_handle\n"); @@ -334,9 +334,9 @@ nal_queue_handle *s5p_mfc_nal_q_create(struct s5p_mfc_dev *dev) spin_lock_init(&nal_q_handle->lock); - nal_q_handle->nal_q_out_handle = mfc_nal_q_create_out_q(dev, nal_q_handle); + nal_q_handle->nal_q_out_handle = __mfc_nal_q_create_out_q(dev, nal_q_handle); if (!nal_q_handle->nal_q_out_handle) { - mfc_nal_q_destroy_in_q(dev, nal_q_handle->nal_q_in_handle); + __mfc_nal_q_destroy_in_q(dev, nal_q_handle->nal_q_in_handle); kfree(nal_q_handle); mfc_err_dev("[NALQ] no nal_q_out_handle\n"); return NULL; @@ -351,7 +351,7 @@ nal_queue_handle *s5p_mfc_nal_q_create(struct s5p_mfc_dev *dev) return nal_q_handle; } -int s5p_mfc_nal_q_destroy(struct s5p_mfc_dev *dev, nal_queue_handle *nal_q_handle) +int mfc_nal_q_destroy(struct mfc_dev *dev, nal_queue_handle *nal_q_handle) { int ret = 0; @@ -367,13 +367,13 @@ int s5p_mfc_nal_q_destroy(struct s5p_mfc_dev *dev, nal_queue_handle *nal_q_handl return -EINVAL; } - ret = mfc_nal_q_destroy_out_q(dev, nal_q_handle->nal_q_out_handle); + ret = __mfc_nal_q_destroy_out_q(dev, nal_q_handle->nal_q_out_handle); if (ret) { mfc_err_dev("[NALQ] failed nal_q_out_handle destroy\n"); return ret; } - ret = mfc_nal_q_destroy_in_q(dev, nal_q_handle->nal_q_in_handle); + ret = __mfc_nal_q_destroy_in_q(dev, nal_q_handle->nal_q_in_handle); if (ret) { mfc_err_dev("[NALQ] failed nal_q_in_handle destroy\n"); return ret; @@ -387,7 +387,7 @@ int s5p_mfc_nal_q_destroy(struct s5p_mfc_dev *dev, nal_queue_handle *nal_q_handl return ret; } -void s5p_mfc_nal_q_init(struct s5p_mfc_dev *dev, nal_queue_handle *nal_q_handle) +void mfc_nal_q_init(struct mfc_dev *dev, nal_queue_handle *nal_q_handle) { mfc_debug_enter(); @@ -407,19 +407,19 @@ void s5p_mfc_nal_q_init(struct s5p_mfc_dev *dev, nal_queue_handle *nal_q_handle) return; } - s5p_mfc_reset_nal_queue_registers(dev); + mfc_reset_nal_queue_registers(dev); nal_q_handle->nal_q_in_handle->in_exe_count = 0; nal_q_handle->nal_q_out_handle->out_exe_count = 0; - mfc_debug(2, "[NALQ] S5P_FIMV_NAL_QUEUE_INPUT_COUNT=%d\n", - s5p_mfc_get_nal_q_input_count()); - mfc_debug(2, "[NALQ] S5P_FIMV_NAL_QUEUE_OUTPUT_COUNT=%d\n", - s5p_mfc_get_nal_q_output_count()); - mfc_debug(2, "[NALQ] S5P_FIMV_NAL_QUEUE_INPUT_EXE_COUNT=%d\n", - s5p_mfc_get_nal_q_input_exe_count()); - mfc_debug(2, "[NALQ] S5P_FIMV_NAL_QUEUE_INFO=%d\n", - s5p_mfc_get_nal_q_info()); + mfc_debug(2, "[NALQ] MFC_REG_NAL_QUEUE_INPUT_COUNT=%d\n", + mfc_get_nal_q_input_count()); + mfc_debug(2, "[NALQ] MFC_REG_NAL_QUEUE_OUTPUT_COUNT=%d\n", + mfc_get_nal_q_output_count()); + mfc_debug(2, "[NALQ] MFC_REG_NAL_QUEUE_INPUT_EXE_COUNT=%d\n", + mfc_get_nal_q_input_exe_count()); + mfc_debug(2, "[NALQ] MFC_REG_NAL_QUEUE_INFO=%d\n", + mfc_get_nal_q_info()); nal_q_handle->nal_q_exception = 0; @@ -428,7 +428,7 @@ void s5p_mfc_nal_q_init(struct s5p_mfc_dev *dev, nal_queue_handle *nal_q_handle) return; } -void s5p_mfc_nal_q_start(struct s5p_mfc_dev *dev, nal_queue_handle *nal_q_handle) +void mfc_nal_q_start(struct mfc_dev *dev, nal_queue_handle *nal_q_handle) { dma_addr_t addr; @@ -451,35 +451,35 @@ void s5p_mfc_nal_q_start(struct s5p_mfc_dev *dev, nal_queue_handle *nal_q_handle addr = nal_q_handle->nal_q_in_handle->in_buf.daddr; - s5p_mfc_update_nal_queue_input(dev, addr, NAL_Q_IN_ENTRY_SIZE * NAL_Q_IN_QUEUE_SIZE); + mfc_update_nal_queue_input(dev, addr, NAL_Q_IN_ENTRY_SIZE * NAL_Q_IN_QUEUE_SIZE); - mfc_debug(2, "[NALQ] S5P_FIMV_NAL_QUEUE_INPUT_ADDR=0x%x\n", - s5p_mfc_get_nal_q_input_addr()); - mfc_debug(2, "[NALQ] S5P_FIMV_NAL_QUEUE_INPUT_SIZE=%d\n", - s5p_mfc_get_nal_q_input_size()); + mfc_debug(2, "[NALQ] MFC_REG_NAL_QUEUE_INPUT_ADDR=0x%x\n", + mfc_get_nal_q_input_addr()); + mfc_debug(2, "[NALQ] MFC_REG_NAL_QUEUE_INPUT_SIZE=%d\n", + mfc_get_nal_q_input_size()); addr = nal_q_handle->nal_q_out_handle->out_buf.daddr; - s5p_mfc_update_nal_queue_output(dev, addr, NAL_Q_OUT_ENTRY_SIZE * NAL_Q_OUT_QUEUE_SIZE); + mfc_update_nal_queue_output(dev, addr, NAL_Q_OUT_ENTRY_SIZE * NAL_Q_OUT_QUEUE_SIZE); - mfc_debug(2, "[NALQ] S5P_FIMV_NAL_QUEUE_OUTPUT_ADDR=0x%x\n", - s5p_mfc_get_nal_q_output_addr()); - mfc_debug(2, "[NALQ] S5P_FIMV_NAL_QUEUE_OUTPUT_SIZE=%d\n", - s5p_mfc_get_nal_q_output_ize()); + mfc_debug(2, "[NALQ] MFC_REG_NAL_QUEUE_OUTPUT_ADDR=0x%x\n", + mfc_get_nal_q_output_addr()); + mfc_debug(2, "[NALQ] MFC_REG_NAL_QUEUE_OUTPUT_SIZE=%d\n", + mfc_get_nal_q_output_ize()); nal_q_handle->nal_q_state = NAL_Q_STATE_STARTED; MFC_TRACE_DEV("** NAL Q state : %d\n", nal_q_handle->nal_q_state); mfc_debug(2, "[NALQ] started, state = %d\n", nal_q_handle->nal_q_state); - MFC_WRITEL(MFC_TIMEOUT_VALUE, S5P_FIMV_DEC_TIMEOUT_VALUE); - s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_NAL_QUEUE); + MFC_WRITEL(MFC_TIMEOUT_VALUE, MFC_REG_DEC_TIMEOUT_VALUE); + mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_NAL_QUEUE); mfc_debug_leave(); return; } -void s5p_mfc_nal_q_stop(struct s5p_mfc_dev *dev, nal_queue_handle *nal_q_handle) +void mfc_nal_q_stop(struct mfc_dev *dev, nal_queue_handle *nal_q_handle) { mfc_debug_enter(); @@ -502,16 +502,16 @@ void s5p_mfc_nal_q_stop(struct s5p_mfc_dev *dev, nal_queue_handle *nal_q_handle) MFC_TRACE_DEV("** NAL Q state : %d\n", nal_q_handle->nal_q_state); mfc_debug(2, "[NALQ] stopped, state = %d\n", nal_q_handle->nal_q_state); - s5p_mfc_clean_dev_int_flags(dev); + mfc_clean_dev_int_flags(dev); - s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_STOP_QUEUE); + mfc_cmd_host2risc(dev, MFC_REG_H2R_CMD_STOP_QUEUE); mfc_debug_leave(); return; } -void s5p_mfc_nal_q_stop_if_started(struct s5p_mfc_dev *dev) +void mfc_nal_q_stop_if_started(struct mfc_dev *dev) { nal_queue_handle *nal_q_handle; @@ -534,12 +534,12 @@ void s5p_mfc_nal_q_stop_if_started(struct s5p_mfc_dev *dev) return; } - s5p_mfc_nal_q_clock_on(dev, nal_q_handle); + mfc_nal_q_clock_on(dev, nal_q_handle); - s5p_mfc_nal_q_stop(dev, nal_q_handle); + mfc_nal_q_stop(dev, nal_q_handle); mfc_info_dev("[NALQ] stop NAL QUEUE during get hwlock\n"); - if (s5p_mfc_wait_for_done_dev(dev, - S5P_FIMV_R2H_CMD_COMPLETE_QUEUE_RET)) { + if (mfc_wait_for_done_dev(dev, + MFC_REG_R2H_CMD_COMPLETE_QUEUE_RET)) { mfc_err_dev("[NALQ] Failed to stop qeueue during get hwlock\n"); dev->logging_data->cause |= (1 << MFC_CAUSE_FAIL_STOP_NAL_Q_FOR_OTHER); call_dop(dev, dump_and_stop_always, dev); @@ -549,9 +549,9 @@ void s5p_mfc_nal_q_stop_if_started(struct s5p_mfc_dev *dev) return; } -void s5p_mfc_nal_q_cleanup_queue(struct s5p_mfc_dev *dev) +void mfc_nal_q_cleanup_queue(struct mfc_dev *dev) { - struct s5p_mfc_ctx *ctx; + struct mfc_ctx *ctx; int i; mfc_debug_enter(); @@ -564,9 +564,9 @@ void s5p_mfc_nal_q_cleanup_queue(struct s5p_mfc_dev *dev) for(i = 0; i < MFC_NUM_CONTEXTS; i++) { ctx = dev->ctx[i]; if (ctx) { - s5p_mfc_cleanup_nal_queue(ctx); - if (s5p_mfc_ctx_ready(ctx)) { - s5p_mfc_set_bit(ctx->num, &dev->work_bits); + mfc_cleanup_nal_queue(ctx); + if (mfc_ctx_ready(ctx)) { + mfc_set_bit(ctx->num, &dev->work_bits); mfc_debug(2, "[NALQ] set work_bits after cleanup," " ctx: %d\n", ctx->num); } @@ -578,9 +578,9 @@ void s5p_mfc_nal_q_cleanup_queue(struct s5p_mfc_dev *dev) return; } -static void mfc_nal_q_set_slice_mode(struct s5p_mfc_ctx *ctx, EncoderInputStr *pInStr) +static void __mfc_nal_q_set_slice_mode(struct mfc_ctx *ctx, EncoderInputStr *pInStr) { - struct s5p_mfc_enc *enc = ctx->enc_priv; + struct mfc_enc *enc = ctx->enc_priv; /* multi-slice control */ if (enc->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) @@ -605,11 +605,11 @@ static void mfc_nal_q_set_slice_mode(struct s5p_mfc_ctx *ctx, EncoderInputStr *p } } -static int mfc_nal_q_run_in_buf_enc(struct s5p_mfc_ctx *ctx, EncoderInputStr *pInStr) +static int __mfc_nal_q_run_in_buf_enc(struct mfc_ctx *ctx, EncoderInputStr *pInStr) { - struct s5p_mfc_dev *dev; - struct s5p_mfc_buf *src_mb, *dst_mb; - struct s5p_mfc_raw_info *raw = NULL; + struct mfc_dev *dev; + struct mfc_buf *src_mb, *dst_mb; + struct mfc_raw_info *raw = NULL; dma_addr_t src_addr[3] = {0, 0, 0}; dma_addr_t addr_2bit[2] = {0, 0}; unsigned int index, i; @@ -627,13 +627,13 @@ static int mfc_nal_q_run_in_buf_enc(struct s5p_mfc_ctx *ctx, EncoderInputStr *pI } pInStr->StartCode = 0xBBBBBBBB; - pInStr->CommandId = s5p_mfc_get_nal_q_input_count(); + pInStr->CommandId = mfc_get_nal_q_input_count(); pInStr->InstanceId = ctx->inst_no; raw = &ctx->raw_buf; if (IS_BUFFER_BATCH_MODE(ctx)) { - src_mb = s5p_mfc_get_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, MFC_BUF_SET_USED); + src_mb = mfc_get_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, MFC_BUF_SET_USED); if (!src_mb) { mfc_err_dev("[NALQ][BUFCON] no src buffers\n"); return -EAGAIN; @@ -642,7 +642,7 @@ static int mfc_nal_q_run_in_buf_enc(struct s5p_mfc_ctx *ctx, EncoderInputStr *pI /* last image in a buffer container */ /* move src_queue -> src_queue_nal_q */ if (src_mb->next_index == (src_mb->num_valid_bufs - 1)) { - src_mb = s5p_mfc_get_move_buf(&ctx->buf_queue_lock, + src_mb = mfc_get_move_buf(&ctx->buf_queue_lock, &ctx->src_buf_nal_queue, &ctx->src_buf_queue, MFC_BUF_SET_USED, MFC_QUEUE_ADD_BOTTOM); if (!src_mb) { @@ -660,7 +660,7 @@ static int mfc_nal_q_run_in_buf_enc(struct s5p_mfc_ctx *ctx, EncoderInputStr *pI src_mb->next_index++; } else { /* move src_queue -> src_queue_nal_q */ - src_mb = s5p_mfc_get_move_buf(&ctx->buf_queue_lock, + src_mb = mfc_get_move_buf(&ctx->buf_queue_lock, &ctx->src_buf_nal_queue, &ctx->src_buf_queue, MFC_BUF_SET_USED, MFC_QUEUE_ADD_BOTTOM); if (!src_mb) { @@ -702,7 +702,7 @@ static int mfc_nal_q_run_in_buf_enc(struct s5p_mfc_ctx *ctx, EncoderInputStr *pI } /* move dst_queue -> dst_queue_nal_q */ - dst_mb = s5p_mfc_get_move_buf(&ctx->buf_queue_lock, + dst_mb = mfc_get_move_buf(&ctx->buf_queue_lock, &ctx->dst_buf_nal_queue, &ctx->dst_buf_queue, MFC_BUF_SET_USED, MFC_QUEUE_ADD_BOTTOM); if (!dst_mb) { mfc_err_dev("[NALQ] no dst buffers\n"); @@ -723,19 +723,19 @@ static int mfc_nal_q_run_in_buf_enc(struct s5p_mfc_ctx *ctx, EncoderInputStr *pI mfc_debug(2, "[NALQ] input queue, dst_buf_queue -> dst_buf_nal_queue, index:%d\n", dst_mb->vb.vb2_buf.index); - mfc_nal_q_set_slice_mode(ctx, pInStr); + __mfc_nal_q_set_slice_mode(ctx, pInStr); mfc_debug_leave(); return 0; } -static int mfc_nal_q_run_in_buf_dec(struct s5p_mfc_ctx *ctx, DecoderInputStr *pInStr) +static int __mfc_nal_q_run_in_buf_dec(struct mfc_ctx *ctx, DecoderInputStr *pInStr) { - struct s5p_mfc_dev *dev; - struct s5p_mfc_buf *src_mb, *dst_mb; - struct s5p_mfc_dec *dec; - struct s5p_mfc_raw_info *raw = &ctx->raw_buf; + struct mfc_dev *dev; + struct mfc_buf *src_mb, *dst_mb; + struct mfc_dec *dec; + struct mfc_raw_info *raw = &ctx->raw_buf; dma_addr_t buf_addr; unsigned int strm_size; unsigned int cpb_buf_size; @@ -759,32 +759,32 @@ static int mfc_nal_q_run_in_buf_dec(struct s5p_mfc_ctx *ctx, DecoderInputStr *pI return -EINVAL; } - if (s5p_mfc_is_queue_count_same(&ctx->buf_queue_lock, &ctx->dst_buf_queue, 0) && - s5p_mfc_is_queue_count_smaller(&ctx->buf_queue_lock, + if (mfc_is_queue_count_same(&ctx->buf_queue_lock, &ctx->dst_buf_queue, 0) && + mfc_is_queue_count_smaller(&ctx->buf_queue_lock, &ctx->ref_buf_queue, (ctx->dpb_count + 5))) { mfc_err_dev("[NALQ] no dst buffers\n"); return -EAGAIN; } - if (s5p_mfc_is_queue_count_same(&ctx->buf_queue_lock, &ctx->src_buf_queue, 0)) { + if (mfc_is_queue_count_same(&ctx->buf_queue_lock, &ctx->src_buf_queue, 0)) { mfc_err_dev("[NALQ] no src buffers\n"); return -EAGAIN; } pInStr->StartCode = 0xAAAAAAAA; - pInStr->CommandId = s5p_mfc_get_nal_q_input_count(); + pInStr->CommandId = mfc_get_nal_q_input_count(); pInStr->InstanceId = ctx->inst_no; pInStr->NalStartOptions = 0; /* Try to use the non-referenced DPB on dst-queue */ - dst_mb = s5p_mfc_search_move_dpb_nal_q(ctx, dec->dynamic_used); + dst_mb = mfc_search_move_dpb_nal_q(ctx, dec->dynamic_used); if (!dst_mb) { mfc_debug(2, "[NALQ][DPB] couldn't find dst buffers\n"); return -EAGAIN; } /* move src_queue -> src_queue_nal_q */ - src_mb = s5p_mfc_get_move_buf(&ctx->buf_queue_lock, + src_mb = mfc_get_move_buf(&ctx->buf_queue_lock, &ctx->src_buf_nal_queue, &ctx->src_buf_queue, MFC_BUF_SET_USED, MFC_QUEUE_ADD_BOTTOM); if (!src_mb) { @@ -857,7 +857,7 @@ static int mfc_nal_q_run_in_buf_dec(struct s5p_mfc_ctx *ctx, DecoderInputStr *pI return 0; } -static void mfc_nal_q_get_enc_frame_buffer(struct s5p_mfc_ctx *ctx, +static void __mfc_nal_q_get_enc_frame_buffer(struct mfc_ctx *ctx, dma_addr_t addr[], int num_planes, EncoderOutputStr *pOutStr) { unsigned long enc_recon_y_addr, enc_recon_c_addr; @@ -873,12 +873,12 @@ static void mfc_nal_q_get_enc_frame_buffer(struct s5p_mfc_ctx *ctx, enc_recon_y_addr, enc_recon_c_addr); } -static void mfc_nal_q_handle_stream_copy_timestamp(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *src_mb) +static void __mfc_nal_q_handle_stream_copy_timestamp(struct mfc_ctx *ctx, struct mfc_buf *src_mb) { - struct s5p_mfc_dev *dev; - struct s5p_mfc_enc *enc = ctx->enc_priv; - struct s5p_mfc_enc_params *p = &enc->params; - struct s5p_mfc_buf *dst_mb; + struct mfc_dev *dev; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + struct mfc_buf *dst_mb; u32 interval; u64 start_timestamp; u64 new_timestamp; @@ -906,22 +906,22 @@ static void mfc_nal_q_handle_stream_copy_timestamp(struct s5p_mfc_ctx *ctx, stru new_timestamp, interval * src_mb->done_index); /* Get the destination buffer */ - dst_mb = s5p_mfc_get_buf(&ctx->buf_queue_lock, &ctx->dst_buf_nal_queue, MFC_BUF_NO_TOUCH_USED); + dst_mb = mfc_get_buf(&ctx->buf_queue_lock, &ctx->dst_buf_nal_queue, MFC_BUF_NO_TOUCH_USED); if (dst_mb) dst_mb->vb.vb2_buf.timestamp = new_timestamp; } -static void mfc_nal_q_handle_stream_input(struct s5p_mfc_ctx *ctx, EncoderOutputStr *pOutStr) +static void __mfc_nal_q_handle_stream_input(struct mfc_ctx *ctx, EncoderOutputStr *pOutStr) { - struct s5p_mfc_buf *src_mb, *ref_mb; + struct mfc_buf *src_mb, *ref_mb; dma_addr_t enc_addr[3] = { 0, 0, 0 }; - struct s5p_mfc_raw_info *raw; + struct mfc_raw_info *raw; int found_in_src_queue = 0; unsigned int i; raw = &ctx->raw_buf; - mfc_nal_q_get_enc_frame_buffer(ctx, &enc_addr[0], raw->num_planes, pOutStr); + __mfc_nal_q_get_enc_frame_buffer(ctx, &enc_addr[0], raw->num_planes, pOutStr); if (enc_addr[0] == 0) { mfc_debug(3, "[NALQ] no encoded src\n"); goto move_buf; @@ -932,36 +932,36 @@ static void mfc_nal_q_handle_stream_input(struct s5p_mfc_ctx *ctx, EncoderOutput ctx->num, i, enc_addr[i]); if (IS_BUFFER_BATCH_MODE(ctx)) { - src_mb = s5p_mfc_find_first_buf(&ctx->buf_queue_lock, + src_mb = mfc_find_first_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, enc_addr[0]); if (src_mb) { found_in_src_queue = 1; - mfc_nal_q_handle_stream_copy_timestamp(ctx, src_mb); + __mfc_nal_q_handle_stream_copy_timestamp(ctx, src_mb); src_mb->done_index++; mfc_debug(4, "[NALQ][BUFCON] batch buf done_index: %d\n", src_mb->done_index); } else { - src_mb = s5p_mfc_find_first_buf(&ctx->buf_queue_lock, + src_mb = mfc_find_first_buf(&ctx->buf_queue_lock, &ctx->src_buf_nal_queue, enc_addr[0]); if (src_mb) { found_in_src_queue = 1; - mfc_nal_q_handle_stream_copy_timestamp(ctx, src_mb); + __mfc_nal_q_handle_stream_copy_timestamp(ctx, src_mb); src_mb->done_index++; mfc_debug(4, "[NALQ][BUFCON] batch buf done_index: %d\n", src_mb->done_index); /* last image in a buffer container */ if (src_mb->done_index == src_mb->num_valid_bufs) { - src_mb = s5p_mfc_find_del_buf(&ctx->buf_queue_lock, + src_mb = mfc_find_del_buf(&ctx->buf_queue_lock, &ctx->src_buf_nal_queue, enc_addr[0]); for (i = 0; i < raw->num_planes; i++) - s5p_mfc_bufcon_put_daddr(ctx, src_mb, i); + mfc_bufcon_put_daddr(ctx, src_mb, i); vb2_buffer_done(&src_mb->vb.vb2_buf, VB2_BUF_STATE_DONE); } } } } else { - src_mb = s5p_mfc_find_del_buf(&ctx->buf_queue_lock, + src_mb = mfc_find_del_buf(&ctx->buf_queue_lock, &ctx->src_buf_nal_queue, enc_addr[0]); if (src_mb) { mfc_debug(3, "[NALQ] find src buf in src_queue\n"); @@ -969,7 +969,7 @@ static void mfc_nal_q_handle_stream_input(struct s5p_mfc_ctx *ctx, EncoderOutput vb2_buffer_done(&src_mb->vb.vb2_buf, VB2_BUF_STATE_DONE); } else { mfc_debug(3, "[NALQ] no src buf in src_queue\n"); - ref_mb = s5p_mfc_find_del_buf(&ctx->buf_queue_lock, + ref_mb = mfc_find_del_buf(&ctx->buf_queue_lock, &ctx->ref_buf_queue, enc_addr[0]); if (ref_mb) { mfc_debug(3, "[NALQ] find src buf in ref_queue\n"); @@ -983,26 +983,26 @@ static void mfc_nal_q_handle_stream_input(struct s5p_mfc_ctx *ctx, EncoderOutput move_buf: /* move enqueued src buffer: src nal queue -> ref queue */ if (!found_in_src_queue) { - src_mb = s5p_mfc_get_move_buf_used(&ctx->buf_queue_lock, + src_mb = mfc_get_move_buf_used(&ctx->buf_queue_lock, &ctx->ref_buf_queue, &ctx->src_buf_nal_queue); if (!src_mb) mfc_err_dev("[NALQ] no src buffers\n"); mfc_debug(2, "[NALQ] enc src_buf_nal_queue(%d) -> ref_buf_queue(%d)\n", - s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_nal_queue), - s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->ref_buf_queue)); + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_nal_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->ref_buf_queue)); } } -static void mfc_nal_q_handle_stream_output(struct s5p_mfc_ctx *ctx, int slice_type, +static void __mfc_nal_q_handle_stream_output(struct mfc_ctx *ctx, int slice_type, unsigned int strm_size, EncoderOutputStr *pOutStr) { - struct s5p_mfc_buf *dst_mb; + struct mfc_buf *dst_mb; unsigned int index; if (strm_size == 0) { mfc_debug(3, "[NALQ] no encoded dst (reuse)\n"); - dst_mb = s5p_mfc_get_move_buf(&ctx->buf_queue_lock, + dst_mb = mfc_get_move_buf(&ctx->buf_queue_lock, &ctx->dst_buf_queue, &ctx->dst_buf_nal_queue, MFC_BUF_RESET_USED, MFC_QUEUE_ADD_TOP); if (!dst_mb) { @@ -1011,8 +1011,8 @@ static void mfc_nal_q_handle_stream_output(struct s5p_mfc_ctx *ctx, int slice_ty } mfc_debug(2, "[NALQ] no output, dst_buf_nal_queue(%d) -> dst_buf_queue(%d) index:%d\n", - s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_nal_queue), - s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_nal_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_queue), dst_mb->vb.vb2_buf.index); return; } else if (strm_size < 0) { @@ -1021,7 +1021,7 @@ static void mfc_nal_q_handle_stream_output(struct s5p_mfc_ctx *ctx, int slice_ty } /* at least one more dest. buffers exist always */ - dst_mb = s5p_mfc_get_del_buf(&ctx->buf_queue_lock, &ctx->dst_buf_nal_queue, MFC_BUF_NO_TOUCH_USED); + dst_mb = mfc_get_del_buf(&ctx->buf_queue_lock, &ctx->dst_buf_nal_queue, MFC_BUF_NO_TOUCH_USED); if (!dst_mb) { mfc_err_dev("[NALQ] no dst buffers\n"); return; @@ -1035,13 +1035,13 @@ static void mfc_nal_q_handle_stream_output(struct s5p_mfc_ctx *ctx, int slice_ty V4L2_BUF_FLAG_BFRAME); switch (slice_type) { - case S5P_FIMV_E_SLICE_TYPE_I: + case MFC_REG_E_SLICE_TYPE_I: dst_mb->vb.flags |= V4L2_BUF_FLAG_KEYFRAME; break; - case S5P_FIMV_E_SLICE_TYPE_P: + case MFC_REG_E_SLICE_TYPE_P: dst_mb->vb.flags |= V4L2_BUF_FLAG_PFRAME; break; - case S5P_FIMV_E_SLICE_TYPE_B: + case MFC_REG_E_SLICE_TYPE_B: dst_mb->vb.flags |= V4L2_BUF_FLAG_BFRAME; break; default: @@ -1060,9 +1060,9 @@ static void mfc_nal_q_handle_stream_output(struct s5p_mfc_ctx *ctx, int slice_ty vb2_buffer_done(&dst_mb->vb.vb2_buf, VB2_BUF_STATE_DONE); } -static void mfc_nal_q_handle_stream(struct s5p_mfc_ctx *ctx, EncoderOutputStr *pOutStr) +static void __mfc_nal_q_handle_stream(struct mfc_ctx *ctx, EncoderOutputStr *pOutStr) { - struct s5p_mfc_enc *enc = ctx->enc_priv; + struct mfc_enc *enc = ctx->enc_priv; int slice_type; unsigned int strm_size; unsigned int pic_count; @@ -1085,21 +1085,21 @@ static void mfc_nal_q_handle_stream(struct s5p_mfc_ctx *ctx, EncoderOutputStr *p ctx->sequence++; /* handle input buffer */ - mfc_nal_q_handle_stream_input(ctx, pOutStr); + __mfc_nal_q_handle_stream_input(ctx, pOutStr); /* handle output buffer */ - mfc_nal_q_handle_stream_output(ctx, slice_type, strm_size, pOutStr); + __mfc_nal_q_handle_stream_output(ctx, slice_type, strm_size, pOutStr); mfc_debug_leave(); return; } -static void mfc_nal_q_handle_reuse_buffer(struct s5p_mfc_ctx *ctx, DecoderOutputStr *pOutStr) +static void __mfc_nal_q_handle_reuse_buffer(struct mfc_ctx *ctx, DecoderOutputStr *pOutStr) { - struct s5p_mfc_dec *dec = ctx->dec_priv; + struct mfc_dec *dec = ctx->dec_priv; unsigned int prev_flag, released_flag = 0; - struct s5p_mfc_buf *dst_mb; + struct mfc_buf *dst_mb; dma_addr_t disp_addr; int i; @@ -1107,7 +1107,7 @@ static void mfc_nal_q_handle_reuse_buffer(struct s5p_mfc_ctx *ctx, DecoderOutput disp_addr = pOutStr->DisplayAddr[0]; if (disp_addr) { mfc_debug(2, "[NALQ][DPB] decoding only but there is disp addr: 0x%llx\n", disp_addr); - dst_mb = s5p_mfc_get_move_buf_addr(&ctx->buf_queue_lock, + dst_mb = mfc_get_move_buf_addr(&ctx->buf_queue_lock, &ctx->dst_buf_queue, &ctx->dst_buf_nal_queue, disp_addr); if (dst_mb) { @@ -1128,7 +1128,7 @@ static void mfc_nal_q_handle_reuse_buffer(struct s5p_mfc_ctx *ctx, DecoderOutput for (i = 0; i < MFC_MAX_DPBS; i++) if (released_flag & (1 << i)) - if (s5p_mfc_move_reuse_buffer(ctx, i)) + if (mfc_move_reuse_buffer(ctx, i)) released_flag &= ~(1 << i); /* Not reused buffer should be released when there is a display frame */ @@ -1138,10 +1138,10 @@ static void mfc_nal_q_handle_reuse_buffer(struct s5p_mfc_ctx *ctx, DecoderOutput clear_bit(i, &dec->available_dpb); } -static void mfc_nal_q_handle_ref_frame(struct s5p_mfc_ctx *ctx, DecoderOutputStr *pOutStr) +static void __mfc_nal_q_handle_ref_frame(struct mfc_ctx *ctx, DecoderOutputStr *pOutStr) { - struct s5p_mfc_dec *dec = ctx->dec_priv; - struct s5p_mfc_buf *dst_mb; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_buf *dst_mb; dma_addr_t dec_addr; int index = 0; @@ -1149,7 +1149,7 @@ static void mfc_nal_q_handle_ref_frame(struct s5p_mfc_ctx *ctx, DecoderOutputStr dec_addr = pOutStr->DecodedAddr[0]; - dst_mb = s5p_mfc_find_move_buf_used(&ctx->buf_queue_lock, + dst_mb = mfc_find_move_buf_used(&ctx->buf_queue_lock, &ctx->ref_buf_queue, &ctx->dst_buf_nal_queue, dec_addr); if (dst_mb) { mfc_debug(2, "[NALQ][DPB] Found in dst queue = 0x%08llx, buf = 0x%08llx\n", @@ -1165,11 +1165,11 @@ static void mfc_nal_q_handle_ref_frame(struct s5p_mfc_ctx *ctx, DecoderOutputStr mfc_debug_leave(); } -static void mfc_nal_q_handle_frame_copy_timestamp(struct s5p_mfc_ctx *ctx, DecoderOutputStr *pOutStr) +static void __mfc_nal_q_handle_frame_copy_timestamp(struct mfc_ctx *ctx, DecoderOutputStr *pOutStr) { - struct s5p_mfc_dec *dec; - struct s5p_mfc_dev *dev; - struct s5p_mfc_buf *ref_mb, *src_mb; + struct mfc_dec *dec; + struct mfc_dev *dev; + struct mfc_buf *ref_mb, *src_mb; dma_addr_t dec_y_addr; mfc_debug_enter(); @@ -1185,28 +1185,28 @@ static void mfc_nal_q_handle_frame_copy_timestamp(struct s5p_mfc_ctx *ctx, Decod dec_y_addr = pOutStr->DecodedAddr[0]; /* Get the next source buffer */ - src_mb = s5p_mfc_get_buf(&ctx->buf_queue_lock, &ctx->src_buf_nal_queue, MFC_BUF_NO_TOUCH_USED); + src_mb = mfc_get_buf(&ctx->buf_queue_lock, &ctx->src_buf_nal_queue, MFC_BUF_NO_TOUCH_USED); if (!src_mb) { mfc_err_dev("[NALQ] no src buffers\n"); return; } - ref_mb = s5p_mfc_find_buf(&ctx->buf_queue_lock, &ctx->ref_buf_queue, dec_y_addr); + ref_mb = mfc_find_buf(&ctx->buf_queue_lock, &ctx->ref_buf_queue, dec_y_addr); if (ref_mb) ref_mb->vb.vb2_buf.timestamp = src_mb->vb.vb2_buf.timestamp; mfc_debug_leave(); } -static void mfc_nal_q_handle_frame_output_move(struct s5p_mfc_ctx *ctx, +static void __mfc_nal_q_handle_frame_output_move(struct mfc_ctx *ctx, dma_addr_t dspl_y_addr, unsigned int released_flag) { - struct s5p_mfc_dec *dec = ctx->dec_priv; - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_buf *dst_mb; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_dev *dev = ctx->dev; + struct mfc_buf *dst_mb; unsigned int index; - dst_mb = s5p_mfc_find_move_buf(&ctx->buf_queue_lock, + dst_mb = mfc_find_move_buf(&ctx->buf_queue_lock, &ctx->dst_buf_queue, &ctx->ref_buf_queue, dspl_y_addr, released_flag); if (dst_mb) { index = dst_mb->vb.vb2_buf.index; @@ -1219,23 +1219,23 @@ static void mfc_nal_q_handle_frame_output_move(struct s5p_mfc_ctx *ctx, dec->available_dpb &= ~(1 << index); released_flag &= ~(1 << index); mfc_debug(2, "[NALQ][DPB] Corrupted frame(%d), it will be re-used(release)\n", - s5p_mfc_get_warn(s5p_mfc_get_int_err())); + mfc_get_warn(mfc_get_int_err())); } else { dec->err_reuse_flag |= 1 << index; mfc_debug(2, "[NALQ][DPB] Corrupted frame(%d), it will be re-used(not released)\n", - s5p_mfc_get_warn(s5p_mfc_get_int_err())); + mfc_get_warn(mfc_get_int_err())); } dec->dynamic_used |= released_flag; } } -static void mfc_nal_q_handle_frame_output_del(struct s5p_mfc_ctx *ctx, +static void __mfc_nal_q_handle_frame_output_del(struct mfc_ctx *ctx, DecoderOutputStr *pOutStr, unsigned int err, unsigned int released_flag) { - struct s5p_mfc_dec *dec = ctx->dec_priv; - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_raw_info *raw = &ctx->raw_buf; - struct s5p_mfc_buf *ref_mb; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_dev *dev = ctx->dev; + struct mfc_raw_info *raw = &ctx->raw_buf; + struct mfc_buf *ref_mb; dma_addr_t dspl_y_addr; unsigned int frame_type; unsigned int dst_frame_status; @@ -1246,29 +1246,29 @@ static void mfc_nal_q_handle_frame_output_del(struct s5p_mfc_ctx *ctx, if (MFC_FEATURE_SUPPORT(dev, dev->pdata->color_aspect_dec)) { is_video_signal_type = ((pOutStr->VideoSignalType - >> S5P_FIMV_D_VIDEO_SIGNAL_TYPE_FLAG_SHIFT) - & S5P_FIMV_D_VIDEO_SIGNAL_TYPE_FLAG_MASK); + >> MFC_REG_D_VIDEO_SIGNAL_TYPE_FLAG_SHIFT) + & MFC_REG_D_VIDEO_SIGNAL_TYPE_FLAG_MASK); is_colour_description = ((pOutStr->VideoSignalType - >> S5P_FIMV_D_COLOUR_DESCRIPTION_FLAG_SHIFT) - & S5P_FIMV_D_COLOUR_DESCRIPTION_FLAG_MASK); + >> MFC_REG_D_COLOUR_DESCRIPTION_FLAG_SHIFT) + & MFC_REG_D_COLOUR_DESCRIPTION_FLAG_MASK); } if (MFC_FEATURE_SUPPORT(dev, dev->pdata->static_info_dec)) { - is_content_light = ((pOutStr->SeiAvail >> S5P_FIMV_D_SEI_AVAIL_CONTENT_LIGHT_SHIFT) - & S5P_FIMV_D_SEI_AVAIL_CONTENT_LIGHT_MASK); - is_display_colour = ((pOutStr->SeiAvail >> S5P_FIMV_D_SEI_AVAIL_MASTERING_DISPLAY_SHIFT) - & S5P_FIMV_D_SEI_AVAIL_MASTERING_DISPLAY_MASK); + is_content_light = ((pOutStr->SeiAvail >> MFC_REG_D_SEI_AVAIL_CONTENT_LIGHT_SHIFT) + & MFC_REG_D_SEI_AVAIL_CONTENT_LIGHT_MASK); + is_display_colour = ((pOutStr->SeiAvail >> MFC_REG_D_SEI_AVAIL_MASTERING_DISPLAY_SHIFT) + & MFC_REG_D_SEI_AVAIL_MASTERING_DISPLAY_MASK); } if (dec->immediate_display == 1) { dspl_y_addr = pOutStr->DecodedAddr[0]; - frame_type = pOutStr->DecodedFrameType & S5P_FIMV_DECODED_FRAME_MASK; + frame_type = pOutStr->DecodedFrameType & MFC_REG_DECODED_FRAME_MASK; } else { dspl_y_addr = pOutStr->DisplayAddr[0]; - frame_type = pOutStr->DisplayFrameType & S5P_FIMV_DISPLAY_FRAME_MASK; + frame_type = pOutStr->DisplayFrameType & MFC_REG_DISPLAY_FRAME_MASK; } - ref_mb = s5p_mfc_find_del_buf(&ctx->buf_queue_lock, &ctx->ref_buf_queue, dspl_y_addr); + ref_mb = mfc_find_del_buf(&ctx->buf_queue_lock, &ctx->ref_buf_queue, dspl_y_addr); if (ref_mb) { index = ref_mb->vb.vb2_buf.index; @@ -1301,7 +1301,7 @@ static void mfc_nal_q_handle_frame_output_del(struct s5p_mfc_ctx *ctx, } if (IS_VP9_DEC(ctx) && MFC_FEATURE_SUPPORT(dev, dev->pdata->color_aspect_dec)) { - if (dec->color_space != S5P_FIMV_D_COLOR_UNKNOWN) { + if (dec->color_space != MFC_REG_D_COLOR_UNKNOWN) { ref_mb->vb.reserved2 |= (1 << 3); mfc_debug(2, "[NALQ][HDR] color space parsed\n"); } @@ -1321,20 +1321,20 @@ static void mfc_nal_q_handle_frame_output_del(struct s5p_mfc_ctx *ctx, V4L2_BUF_FLAG_ERROR); switch (frame_type) { - case S5P_FIMV_DISPLAY_FRAME_I: + case MFC_REG_DISPLAY_FRAME_I: ref_mb->vb.flags |= V4L2_BUF_FLAG_KEYFRAME; break; - case S5P_FIMV_DISPLAY_FRAME_P: + case MFC_REG_DISPLAY_FRAME_P: ref_mb->vb.flags |= V4L2_BUF_FLAG_PFRAME; break; - case S5P_FIMV_DISPLAY_FRAME_B: + case MFC_REG_DISPLAY_FRAME_B: ref_mb->vb.flags |= V4L2_BUF_FLAG_BFRAME; break; default: break; } - disp_err = s5p_mfc_get_warn(pOutStr->ErrorCode); + disp_err = mfc_get_warn(pOutStr->ErrorCode); if (disp_err) { mfc_err_ctx("[NALQ] Warning for displayed frame: %d\n", disp_err); @@ -1345,11 +1345,11 @@ static void mfc_nal_q_handle_frame_output_del(struct s5p_mfc_ctx *ctx, &ctx->dst_ctrls[index], pOutStr) < 0) mfc_err_ctx("[NALQ] failed in get_buf_ctrls_val\n"); - s5p_mfc_handle_released_info(ctx, released_flag, index); + mfc_handle_released_info(ctx, released_flag, index); if (dec->immediate_display == 1) { dst_frame_status = pOutStr->DecodedStatus - & S5P_FIMV_DEC_STATUS_DECODED_STATUS_MASK; + & MFC_REG_DEC_STATUS_DECODED_STATUS_MASK; call_cop(ctx, get_buf_update_val, ctx, &ctx->dst_ctrls[index], @@ -1364,16 +1364,16 @@ static void mfc_nal_q_handle_frame_output_del(struct s5p_mfc_ctx *ctx, dec->immediate_display = 0; } - s5p_mfc_qos_update_last_framerate(ctx, ref_mb->vb.vb2_buf.timestamp); + mfc_qos_update_last_framerate(ctx, ref_mb->vb.vb2_buf.timestamp); vb2_buffer_done(&ref_mb->vb.vb2_buf, disp_err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); } } -static void mfc_nal_q_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err, +static void __mfc_nal_q_handle_frame_new(struct mfc_ctx *ctx, unsigned int err, DecoderOutputStr *pOutStr) { - struct s5p_mfc_dec *dec = ctx->dec_priv; + struct mfc_dec *dec = ctx->dec_priv; dma_addr_t dspl_y_addr; unsigned int frame_type; unsigned int prev_flag, released_flag = 0; @@ -1381,8 +1381,8 @@ static void mfc_nal_q_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err mfc_debug_enter(); - frame_type = pOutStr->DisplayFrameType & S5P_FIMV_DISPLAY_FRAME_MASK; - disp_err = s5p_mfc_get_warn(pOutStr->ErrorCode); + frame_type = pOutStr->DisplayFrameType & MFC_REG_DISPLAY_FRAME_MASK; + disp_err = mfc_get_warn(pOutStr->ErrorCode); ctx->sequence++; @@ -1390,13 +1390,13 @@ static void mfc_nal_q_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err if (dec->immediate_display == 1) { dspl_y_addr = pOutStr->DecodedAddr[0]; - frame_type = pOutStr->DecodedFrameType & S5P_FIMV_DECODED_FRAME_MASK; + frame_type = pOutStr->DecodedFrameType & MFC_REG_DECODED_FRAME_MASK; } mfc_debug(2, "[NALQ][FRAME] frame type: %d\n", frame_type); /* If frame is same as previous then skip and do not dequeue */ - if (frame_type == S5P_FIMV_DISPLAY_FRAME_NOT_CODED) { + if (frame_type == MFC_REG_DISPLAY_FRAME_NOT_CODED) { if (!CODEC_NOT_CODED(ctx)) return; } @@ -1409,21 +1409,21 @@ static void mfc_nal_q_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err prev_flag, dec->dynamic_used, released_flag); if ((IS_VC1_RCV_DEC(ctx) && - (disp_err == S5P_FIMV_ERR_SYNC_POINT_NOT_RECEIVED)) || - (disp_err == S5P_FIMV_ERR_BROKEN_LINK)) - mfc_nal_q_handle_frame_output_move(ctx, dspl_y_addr, released_flag); + (disp_err == MFC_REG_ERR_SYNC_POINT_NOT_RECEIVED)) || + (disp_err == MFC_REG_ERR_BROKEN_LINK)) + __mfc_nal_q_handle_frame_output_move(ctx, dspl_y_addr, released_flag); else - mfc_nal_q_handle_frame_output_del(ctx, pOutStr, err, released_flag); + __mfc_nal_q_handle_frame_output_del(ctx, pOutStr, err, released_flag); mfc_debug_leave(); } -static void mfc_nal_q_handle_frame_input(struct s5p_mfc_ctx *ctx, unsigned int err, +static void __mfc_nal_q_handle_frame_input(struct mfc_ctx *ctx, unsigned int err, DecoderOutputStr *pOutStr) { - struct s5p_mfc_dec *dec = ctx->dec_priv; - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_buf *src_mb; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_dev *dev = ctx->dev; + struct mfc_buf *src_mb; unsigned int index; int deleted = 0; unsigned long consumed; @@ -1433,7 +1433,7 @@ static void mfc_nal_q_handle_frame_input(struct s5p_mfc_ctx *ctx, unsigned int e */ if (dec->consumed) { mfc_err_dev("[NALQ] previous buffer was not fully consumed\n"); - src_mb = s5p_mfc_get_del_buf(&ctx->buf_queue_lock, &ctx->src_buf_nal_queue, + src_mb = mfc_get_del_buf(&ctx->buf_queue_lock, &ctx->src_buf_nal_queue, MFC_BUF_NO_TOUCH_USED); if (src_mb) vb2_buffer_done(&src_mb->vb.vb2_buf, VB2_BUF_STATE_DONE); @@ -1441,7 +1441,7 @@ static void mfc_nal_q_handle_frame_input(struct s5p_mfc_ctx *ctx, unsigned int e /* Check multi-frame */ consumed = pOutStr->DecodedNalSize; - src_mb = s5p_mfc_get_del_if_consumed(ctx, &ctx->src_buf_nal_queue, + src_mb = mfc_get_del_if_consumed(ctx, &ctx->src_buf_nal_queue, consumed, STUFF_BYTE, err, &deleted); if (!src_mb) { mfc_err_dev("[NALQ] no src buffers\n"); @@ -1481,10 +1481,10 @@ static void mfc_nal_q_handle_frame_input(struct s5p_mfc_ctx *ctx, unsigned int e vb2_buffer_done(&src_mb->vb.vb2_buf, VB2_BUF_STATE_DONE); } -void mfc_nal_q_handle_frame(struct s5p_mfc_ctx *ctx, DecoderOutputStr *pOutStr) +void __mfc_nal_q_handle_frame(struct mfc_ctx *ctx, DecoderOutputStr *pOutStr) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_dec *dec = ctx->dec_priv; + struct mfc_dev *dev = ctx->dev; + struct mfc_dec *dec = ctx->dec_priv; unsigned int dst_frame_status, sei_avail_status, need_empty_dpb; unsigned int res_change, need_dpb_change, need_scratch_change; unsigned int is_interlaced, err; @@ -1492,37 +1492,37 @@ void mfc_nal_q_handle_frame(struct s5p_mfc_ctx *ctx, DecoderOutputStr *pOutStr) mfc_debug_enter(); dst_frame_status = pOutStr->DisplayStatus - & S5P_FIMV_DISP_STATUS_DISPLAY_STATUS_MASK; + & MFC_REG_DISP_STATUS_DISPLAY_STATUS_MASK; need_empty_dpb = (pOutStr->DisplayStatus - >> S5P_FIMV_DISP_STATUS_NEED_EMPTY_DPB_SHIFT) - & S5P_FIMV_DISP_STATUS_NEED_EMPTY_DPB_MASK; + >> MFC_REG_DISP_STATUS_NEED_EMPTY_DPB_SHIFT) + & MFC_REG_DISP_STATUS_NEED_EMPTY_DPB_MASK; res_change = (pOutStr->DisplayStatus - >> S5P_FIMV_DISP_STATUS_RES_CHANGE_SHIFT) - & S5P_FIMV_DISP_STATUS_RES_CHANGE_MASK; + >> MFC_REG_DISP_STATUS_RES_CHANGE_SHIFT) + & MFC_REG_DISP_STATUS_RES_CHANGE_MASK; need_dpb_change = (pOutStr->DisplayStatus - >> S5P_FIMV_DISP_STATUS_NEED_DPB_CHANGE_SHIFT) - & S5P_FIMV_DISP_STATUS_NEED_DPB_CHANGE_MASK; + >> MFC_REG_DISP_STATUS_NEED_DPB_CHANGE_SHIFT) + & MFC_REG_DISP_STATUS_NEED_DPB_CHANGE_MASK; need_scratch_change = (pOutStr->DisplayStatus - >> S5P_FIMV_DISP_STATUS_NEED_SCRATCH_CHANGE_SHIFT) - & S5P_FIMV_DISP_STATUS_NEED_SCRATCH_CHANGE_MASK; + >> MFC_REG_DISP_STATUS_NEED_SCRATCH_CHANGE_SHIFT) + & MFC_REG_DISP_STATUS_NEED_SCRATCH_CHANGE_MASK; is_interlaced = (pOutStr->DisplayStatus - >> S5P_FIMV_DISP_STATUS_INTERLACE_SHIFT) - & S5P_FIMV_DISP_STATUS_INTERLACE_MASK; + >> MFC_REG_DISP_STATUS_INTERLACE_SHIFT) + & MFC_REG_DISP_STATUS_INTERLACE_MASK; sei_avail_status = pOutStr->SeiAvail; err = pOutStr->ErrorCode; if (dec->immediate_display == 1) dst_frame_status = pOutStr->DecodedStatus - & S5P_FIMV_DEC_STATUS_DECODED_STATUS_MASK; + & MFC_REG_DEC_STATUS_DECODED_STATUS_MASK; mfc_debug(2, "[NALQ][FRAME] frame status: %d\n", dst_frame_status); mfc_debug(2, "[NALQ][FRAME] display status: %d, type: %d, yaddr: %#x\n", - pOutStr->DisplayStatus & S5P_FIMV_DISP_STATUS_DISPLAY_STATUS_MASK, - pOutStr->DisplayFrameType & S5P_FIMV_DISPLAY_FRAME_MASK, + pOutStr->DisplayStatus & MFC_REG_DISP_STATUS_DISPLAY_STATUS_MASK, + pOutStr->DisplayFrameType & MFC_REG_DISPLAY_FRAME_MASK, pOutStr->DisplayAddr[0]); mfc_debug(2, "[NALQ][FRAME] decoded status: %d, type: %d, yaddr: %#x\n", - pOutStr->DecodedStatus & S5P_FIMV_DEC_STATUS_DECODED_STATUS_MASK, - pOutStr->DecodedFrameType & S5P_FIMV_DECODED_FRAME_MASK, + pOutStr->DecodedStatus & MFC_REG_DEC_STATUS_DECODED_STATUS_MASK, + pOutStr->DecodedFrameType & MFC_REG_DECODED_FRAME_MASK, pOutStr->DecodedAddr[0]); mfc_debug(4, "[NALQ][HDR] SEI available status: %x\n", sei_avail_status); mfc_debug(2, "[NALQ][DPB] Used flag: old = %08x, new = %08x\n", @@ -1534,7 +1534,7 @@ void mfc_nal_q_handle_frame(struct s5p_mfc_ctx *ctx, DecoderOutputStr *pOutStr) } if (res_change) { mfc_debug(2, "[NALQ][DRC] Resolution change set to %d\n", res_change); - s5p_mfc_change_state(ctx, MFCINST_RES_CHANGE_INIT); + mfc_change_state(ctx, MFCINST_RES_CHANGE_INIT); ctx->wait_state = WAIT_DECODING; dev->nal_q_handle->nal_q_exception = 1; mfc_info_ctx("[NALQ][DRC] nal_q_exception is set (res change)\n"); @@ -1561,34 +1561,34 @@ void mfc_nal_q_handle_frame(struct s5p_mfc_ctx *ctx, DecoderOutputStr *pOutStr) goto leave_handle_frame; } - if (s5p_mfc_is_queue_count_same(&ctx->buf_queue_lock, &ctx->src_buf_nal_queue, 0) && - s5p_mfc_is_queue_count_same(&ctx->buf_queue_lock, &ctx->dst_buf_nal_queue, 0)) { + if (mfc_is_queue_count_same(&ctx->buf_queue_lock, &ctx->src_buf_nal_queue, 0) && + mfc_is_queue_count_same(&ctx->buf_queue_lock, &ctx->dst_buf_nal_queue, 0)) { mfc_err_dev("[NALQ] Queue count is zero for src/dst\n"); goto leave_handle_frame; } switch (dst_frame_status) { - case S5P_FIMV_DEC_STATUS_DECODING_DISPLAY: - mfc_nal_q_handle_ref_frame(ctx, pOutStr); - mfc_nal_q_handle_frame_copy_timestamp(ctx, pOutStr); + case MFC_REG_DEC_STATUS_DECODING_DISPLAY: + __mfc_nal_q_handle_ref_frame(ctx, pOutStr); + __mfc_nal_q_handle_frame_copy_timestamp(ctx, pOutStr); break; - case S5P_FIMV_DEC_STATUS_DECODING_ONLY: - mfc_nal_q_handle_ref_frame(ctx, pOutStr); - mfc_nal_q_handle_reuse_buffer(ctx, pOutStr); + case MFC_REG_DEC_STATUS_DECODING_ONLY: + __mfc_nal_q_handle_ref_frame(ctx, pOutStr); + __mfc_nal_q_handle_reuse_buffer(ctx, pOutStr); break; default: break; } /* A frame has been decoded and is in the buffer */ - if (s5p_mfc_dec_status_display(dst_frame_status)) - mfc_nal_q_handle_frame_new(ctx, err, pOutStr); + if (mfc_dec_status_display(dst_frame_status)) + __mfc_nal_q_handle_frame_new(ctx, err, pOutStr); else mfc_debug(2, "[NALQ] No display frame\n"); /* Mark source buffer as complete */ - if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY) - mfc_nal_q_handle_frame_input(ctx, err, pOutStr); + if (dst_frame_status != MFC_REG_DEC_STATUS_DISPLAY_ONLY) + __mfc_nal_q_handle_frame_input(ctx, err, pOutStr); else mfc_debug(2, "[NALQ][DPB] can't support display only in NAL-Q, is_dpb_full: %d\n", dec->is_dpb_full); @@ -1597,12 +1597,12 @@ leave_handle_frame: mfc_debug_leave(); } -int mfc_nal_q_handle_error(struct s5p_mfc_ctx *ctx, EncoderOutputStr *pOutStr, int err) +int __mfc_nal_q_handle_error(struct mfc_ctx *ctx, EncoderOutputStr *pOutStr, int err) { - struct s5p_mfc_dev *dev; - struct s5p_mfc_dec *dec; - struct s5p_mfc_enc *enc; - struct s5p_mfc_buf *src_mb; + struct mfc_dev *dev; + struct mfc_dec *dec; + struct mfc_enc *enc; + struct mfc_buf *src_mb; int stop_nal_q = 1; mfc_debug_enter(); @@ -1629,7 +1629,7 @@ int mfc_nal_q_handle_error(struct s5p_mfc_ctx *ctx, EncoderOutputStr *pOutStr, i mfc_err_dev("[NALQ] no mfc decoder to run\n"); goto end; } - src_mb = s5p_mfc_get_del_buf(&ctx->buf_queue_lock, + src_mb = mfc_get_del_buf(&ctx->buf_queue_lock, &ctx->src_buf_nal_queue, MFC_BUF_NO_TOUCH_USED); if (!src_mb) { @@ -1649,8 +1649,8 @@ int mfc_nal_q_handle_error(struct s5p_mfc_ctx *ctx, EncoderOutputStr *pOutStr, i * If the buffer full error occurs in NAL-Q mode, * one input buffer is returned and the NAL-Q mode continues. */ - if (err == S5P_FIMV_ERR_BUFFER_FULL) { - src_mb = s5p_mfc_get_del_buf(&ctx->buf_queue_lock, + if (err == MFC_REG_ERR_BUFFER_FULL) { + src_mb = mfc_get_del_buf(&ctx->buf_queue_lock, &ctx->src_buf_nal_queue, MFC_BUF_NO_TOUCH_USED); if (!src_mb) @@ -1669,11 +1669,11 @@ end: return stop_nal_q; } -int s5p_mfc_nal_q_handle_out_buf(struct s5p_mfc_dev *dev, EncoderOutputStr *pOutStr) +int mfc_nal_q_handle_out_buf(struct mfc_dev *dev, EncoderOutputStr *pOutStr) { - struct s5p_mfc_ctx *ctx; - struct s5p_mfc_enc *enc; - struct s5p_mfc_dec *dec; + struct mfc_ctx *ctx; + struct mfc_enc *enc; + struct mfc_dec *dec; int ctx_num; mfc_debug_enter(); @@ -1698,9 +1698,9 @@ int s5p_mfc_nal_q_handle_out_buf(struct s5p_mfc_dev *dev, EncoderOutputStr *pOut mfc_debug(2, "[NALQ] Int ctx is %d(%s)\n", ctx_num, ctx->type == MFCINST_ENCODER ? "enc" : "dec"); - if (s5p_mfc_get_err(pOutStr->ErrorCode) && - (s5p_mfc_get_err(pOutStr->ErrorCode) < S5P_FIMV_ERR_FRAME_CONCEAL)) { - if (mfc_nal_q_handle_error(ctx, pOutStr, s5p_mfc_get_err(pOutStr->ErrorCode))) + if (mfc_get_err(pOutStr->ErrorCode) && + (mfc_get_err(pOutStr->ErrorCode) < MFC_REG_ERR_FRAME_CONCEAL)) { + if (__mfc_nal_q_handle_error(ctx, pOutStr, mfc_get_err(pOutStr->ErrorCode))) return 0; } @@ -1710,14 +1710,14 @@ int s5p_mfc_nal_q_handle_out_buf(struct s5p_mfc_dev *dev, EncoderOutputStr *pOut mfc_err_dev("[NALQ] no mfc encoder to run\n"); return -EINVAL; } - mfc_nal_q_handle_stream(ctx, pOutStr); + __mfc_nal_q_handle_stream(ctx, pOutStr); } else if (ctx->type == MFCINST_DECODER) { dec = ctx->dec_priv; if (!dec) { mfc_err_dev("[NALQ] no mfc decoder to run\n"); return -EINVAL; } - mfc_nal_q_handle_frame(ctx, (DecoderOutputStr *)pOutStr); + __mfc_nal_q_handle_frame(ctx, (DecoderOutputStr *)pOutStr); } mfc_debug_leave(); @@ -1728,7 +1728,7 @@ int s5p_mfc_nal_q_handle_out_buf(struct s5p_mfc_dev *dev, EncoderOutputStr *pOut /* * This function should be called in NAL_Q_STATE_STARTED state. */ -int s5p_mfc_nal_q_enqueue_in_buf(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx, +int mfc_nal_q_enqueue_in_buf(struct mfc_dev *dev, struct mfc_ctx *ctx, nal_queue_in_handle *nal_q_in_handle) { unsigned long flags; @@ -1754,8 +1754,8 @@ int s5p_mfc_nal_q_enqueue_in_buf(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ct spin_lock_irqsave(&nal_q_in_handle->nal_q_handle->lock, flags); - input_count = s5p_mfc_get_nal_q_input_count(); - input_exe_count = s5p_mfc_get_nal_q_input_exe_count(); + input_count = mfc_get_nal_q_input_count(); + input_exe_count = mfc_get_nal_q_input_exe_count(); input_diff = input_count - input_exe_count; /* @@ -1782,9 +1782,9 @@ int s5p_mfc_nal_q_enqueue_in_buf(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ct memset(pStr, 0, NAL_Q_IN_ENTRY_SIZE); if (ctx->type == MFCINST_ENCODER) - ret = mfc_nal_q_run_in_buf_enc(ctx, pStr); + ret = __mfc_nal_q_run_in_buf_enc(ctx, pStr); else if (ctx->type == MFCINST_DECODER) - ret = mfc_nal_q_run_in_buf_dec(ctx, (DecoderInputStr *)pStr); + ret = __mfc_nal_q_run_in_buf_dec(ctx, (DecoderInputStr *)pStr); if (ret != 0) { mfc_debug(2, "[NALQ] Failed to set input queue\n"); @@ -1801,10 +1801,10 @@ int s5p_mfc_nal_q_enqueue_in_buf(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ct } input_count++; - s5p_mfc_update_nal_queue_input_count(dev, input_count); + mfc_update_nal_queue_input_count(dev, input_count); if (input_diff == 0) - s5p_mfc_watchdog_start_tick(dev); + mfc_watchdog_start_tick(dev); spin_unlock_irqrestore(&nal_q_in_handle->nal_q_handle->lock, flags); @@ -1820,10 +1820,10 @@ int s5p_mfc_nal_q_enqueue_in_buf(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ct /* * This function should be called in NAL_Q_STATE_STARTED state. */ -EncoderOutputStr *s5p_mfc_nal_q_dequeue_out_buf(struct s5p_mfc_dev *dev, +EncoderOutputStr *mfc_nal_q_dequeue_out_buf(struct mfc_dev *dev, nal_queue_out_handle *nal_q_out_handle, unsigned int *reason) { - struct s5p_mfc_ctx *ctx; + struct mfc_ctx *ctx; unsigned long flags; unsigned int output_count = 0; unsigned int output_exe_count = 0; @@ -1842,7 +1842,7 @@ EncoderOutputStr *s5p_mfc_nal_q_dequeue_out_buf(struct s5p_mfc_dev *dev, spin_lock_irqsave(&nal_q_out_handle->nal_q_handle->lock, flags); - output_count = s5p_mfc_get_nal_q_output_count(); + output_count = mfc_get_nal_q_output_count(); output_exe_count = nal_q_out_handle->out_exe_count; output_diff = output_count - output_exe_count; @@ -1866,7 +1866,7 @@ EncoderOutputStr *s5p_mfc_nal_q_dequeue_out_buf(struct s5p_mfc_dev *dev, index = output_exe_count % NAL_Q_OUT_QUEUE_SIZE; pStr = &(nal_q_out_handle->nal_q_out_addr->entry[index].enc); - nal_q_out_handle->nal_q_ctx = mfc_nal_q_find_ctx(dev, pStr); + nal_q_out_handle->nal_q_ctx = __mfc_nal_q_find_ctx(dev, pStr); if (nal_q_out_handle->nal_q_ctx < 0) { mfc_err_dev("[NALQ] Can't find ctx in nal q\n"); pStr = NULL; @@ -1885,15 +1885,15 @@ EncoderOutputStr *s5p_mfc_nal_q_dequeue_out_buf(struct s5p_mfc_dev *dev, nal_q_out_handle->out_exe_count++; if (pStr->ErrorCode) { - *reason = S5P_FIMV_R2H_CMD_ERR_RET; + *reason = MFC_REG_R2H_CMD_ERR_RET; mfc_err_dev("[NALQ] Error : %d\n", pStr->ErrorCode); } - input_diff = s5p_mfc_get_nal_q_input_count() - s5p_mfc_get_nal_q_input_exe_count(); + input_diff = mfc_get_nal_q_input_count() - mfc_get_nal_q_input_exe_count(); if (input_diff == 0) { - s5p_mfc_watchdog_stop_tick(dev); + mfc_watchdog_stop_tick(dev); } else if (input_diff > 0) { - s5p_mfc_watchdog_reset_tick(dev); + mfc_watchdog_reset_tick(dev); } spin_unlock_irqrestore(&nal_q_out_handle->nal_q_handle->lock, flags); @@ -1909,89 +1909,89 @@ EncoderOutputStr *s5p_mfc_nal_q_dequeue_out_buf(struct s5p_mfc_dev *dev, #if 0 /* not used function - only for reference sfr <-> structure */ -void s5p_mfc_nal_q_fill_DecoderInputStr(struct s5p_mfc_dev *dev, DecoderInputStr *pStr) +void mfc_nal_q_fill_DecoderInputStr(struct mfc_dev *dev, DecoderInputStr *pStr) { pStr->StartCode = 0xAAAAAAAA; // Decoder input start -// pStr->CommandId = MFC_READL(S5P_FIMV_HOST2RISC_CMD); // 0x1100 - pStr->InstanceId = MFC_READL(S5P_FIMV_INSTANCE_ID); // 0xF008 - pStr->PictureTag = MFC_READL(S5P_FIMV_D_PICTURE_TAG); // 0xF5C8 - pStr->CpbBufferAddr = MFC_READL(S5P_FIMV_D_CPB_BUFFER_ADDR); // 0xF5B0 - pStr->CpbBufferSize = MFC_READL(S5P_FIMV_D_CPB_BUFFER_SIZE); // 0xF5B4 - pStr->CpbBufferOffset = MFC_READL(S5P_FIMV_D_CPB_BUFFER_OFFSET); // 0xF5C0 - pStr->StreamDataSize = MFC_READL(S5P_FIMV_D_STREAM_DATA_SIZE); // 0xF5D0 - pStr->AvailableDpbFlagUpper = MFC_READL(S5P_FIMV_D_AVAILABLE_DPB_FLAG_UPPER);// 0xF5B8 - pStr->AvailableDpbFlagLower = MFC_READL(S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER);// 0xF5BC - pStr->DynamicDpbFlagUpper = MFC_READL(S5P_FIMV_D_DYNAMIC_DPB_FLAG_UPPER); // 0xF5D4 - pStr->DynamicDpbFlagLower = MFC_READL(S5P_FIMV_D_DYNAMIC_DPB_FLAG_LOWER); // 0xF5D8 - pStr->FirstPlaneDpb = MFC_READL(S5P_FIMV_D_FIRST_PLANE_DPB0); // 0xF160+(index*4) - pStr->SecondPlaneDpb = MFC_READL(S5P_FIMV_D_SECOND_PLANE_DPB0); // 0xF260+(index*4) - pStr->ThirdPlaneDpb = MFC_READL(S5P_FIMV_D_THIRD_PLANE_DPB0); // 0xF360+(index*4) - pStr->FirstPlaneDpbSize = MFC_READL(S5P_FIMV_D_FIRST_PLANE_DPB_SIZE); // 0xF144 - pStr->SecondPlaneDpbSize = MFC_READL(S5P_FIMV_D_SECOND_PLANE_DPB_SIZE); // 0xF148 - pStr->ThirdPlaneDpbSize = MFC_READL(S5P_FIMV_D_THIRD_PLANE_DPB_SIZE); // 0xF14C - pStr->NalStartOptions = MFC_READL(0xF5AC);// S5P_FIMV_D_NAL_START_OPTIONS 0xF5AC - pStr->FirstPlaneStrideSize = MFC_READL(S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE);// 0xF138 - pStr->SecondPlaneStrideSize = MFC_READL(S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE);// 0xF13C - pStr->ThirdPlaneStrideSize = MFC_READL(S5P_FIMV_D_THIRD_PLANE_DPB_STRIDE_SIZE);// 0xF140 - pStr->FirstPlane2BitDpbSize = MFC_READL(S5P_FIMV_D_FIRST_PLANE_2BIT_DPB_SIZE);// 0xF578 - pStr->SecondPlane2BitDpbSize = MFC_READL(S5P_FIMV_D_SECOND_PLANE_2BIT_DPB_SIZE);// 0xF57C - pStr->FirstPlane2BitStrideSize = MFC_READL(S5P_FIMV_D_FIRST_PLANE_2BIT_DPB_STRIDE_SIZE);// 0xF580 - pStr->SecondPlane2BitStrideSize = MFC_READL(S5P_FIMV_D_SECOND_PLANE_2BIT_DPB_STRIDE_SIZE);// 0xF584 - pStr->ScratchBufAddr = MFC_READL(S5P_FIMV_D_SCRATCH_BUFFER_ADDR); // 0xF560 - pStr->ScratchBufSize = MFC_READL(S5P_FIMV_D_SCRATCH_BUFFER_SIZE); // 0xF564 +// pStr->CommandId = MFC_READL(MFC_REG_HOST2RISC_CMD); // 0x1100 + pStr->InstanceId = MFC_READL(MFC_REG_INSTANCE_ID); // 0xF008 + pStr->PictureTag = MFC_READL(MFC_REG_D_PICTURE_TAG); // 0xF5C8 + pStr->CpbBufferAddr = MFC_READL(MFC_REG_D_CPB_BUFFER_ADDR); // 0xF5B0 + pStr->CpbBufferSize = MFC_READL(MFC_REG_D_CPB_BUFFER_SIZE); // 0xF5B4 + pStr->CpbBufferOffset = MFC_READL(MFC_REG_D_CPB_BUFFER_OFFSET); // 0xF5C0 + pStr->StreamDataSize = MFC_READL(MFC_REG_D_STREAM_DATA_SIZE); // 0xF5D0 + pStr->AvailableDpbFlagUpper = MFC_READL(MFC_REG_D_AVAILABLE_DPB_FLAG_UPPER);// 0xF5B8 + pStr->AvailableDpbFlagLower = MFC_READL(MFC_REG_D_AVAILABLE_DPB_FLAG_LOWER);// 0xF5BC + pStr->DynamicDpbFlagUpper = MFC_READL(MFC_REG_D_DYNAMIC_DPB_FLAG_UPPER); // 0xF5D4 + pStr->DynamicDpbFlagLower = MFC_READL(MFC_REG_D_DYNAMIC_DPB_FLAG_LOWER); // 0xF5D8 + pStr->FirstPlaneDpb = MFC_READL(MFC_REG_D_FIRST_PLANE_DPB0); // 0xF160+(index*4) + pStr->SecondPlaneDpb = MFC_READL(MFC_REG_D_SECOND_PLANE_DPB0); // 0xF260+(index*4) + pStr->ThirdPlaneDpb = MFC_READL(MFC_REG_D_THIRD_PLANE_DPB0); // 0xF360+(index*4) + pStr->FirstPlaneDpbSize = MFC_READL(MFC_REG_D_FIRST_PLANE_DPB_SIZE); // 0xF144 + pStr->SecondPlaneDpbSize = MFC_READL(MFC_REG_D_SECOND_PLANE_DPB_SIZE); // 0xF148 + pStr->ThirdPlaneDpbSize = MFC_READL(MFC_REG_D_THIRD_PLANE_DPB_SIZE); // 0xF14C + pStr->NalStartOptions = MFC_READL(0xF5AC);// MFC_REG_D_NAL_START_OPTIONS 0xF5AC + pStr->FirstPlaneStrideSize = MFC_READL(MFC_REG_D_FIRST_PLANE_DPB_STRIDE_SIZE);// 0xF138 + pStr->SecondPlaneStrideSize = MFC_READL(MFC_REG_D_SECOND_PLANE_DPB_STRIDE_SIZE);// 0xF13C + pStr->ThirdPlaneStrideSize = MFC_READL(MFC_REG_D_THIRD_PLANE_DPB_STRIDE_SIZE);// 0xF140 + pStr->FirstPlane2BitDpbSize = MFC_READL(MFC_REG_D_FIRST_PLANE_2BIT_DPB_SIZE);// 0xF578 + pStr->SecondPlane2BitDpbSize = MFC_READL(MFC_REG_D_SECOND_PLANE_2BIT_DPB_SIZE);// 0xF57C + pStr->FirstPlane2BitStrideSize = MFC_READL(MFC_REG_D_FIRST_PLANE_2BIT_DPB_STRIDE_SIZE);// 0xF580 + pStr->SecondPlane2BitStrideSize = MFC_READL(MFC_REG_D_SECOND_PLANE_2BIT_DPB_STRIDE_SIZE);// 0xF584 + pStr->ScratchBufAddr = MFC_READL(MFC_REG_D_SCRATCH_BUFFER_ADDR); // 0xF560 + pStr->ScratchBufSize = MFC_READL(MFC_REG_D_SCRATCH_BUFFER_SIZE); // 0xF564 } -void s5p_mfc_nal_q_flush_DecoderOutputStr(struct s5p_mfc_dev *dev, DecoderOutputStr *pStr) +void mfc_nal_q_flush_DecoderOutputStr(struct mfc_dev *dev, DecoderOutputStr *pStr) { //pStr->StartCode; // 0xAAAAAAAA; // Decoder output start -// MFC_WRITEL(pStr->CommandId, S5P_FIMV_RISC2HOST_CMD); // 0x1104 - MFC_WRITEL(pStr->InstanceId, S5P_FIMV_RET_INSTANCE_ID); // 0xF070 - MFC_WRITEL(pStr->ErrorCode, S5P_FIMV_ERROR_CODE); // 0xF074 - MFC_WRITEL(pStr->PictureTagTop, S5P_FIMV_D_RET_PICTURE_TAG_TOP); // 0xF674 - MFC_WRITEL(pStr->PictureTimeTop, S5P_FIMV_D_RET_PICTURE_TIME_TOP); // 0xF67C - MFC_WRITEL(pStr->DisplayFrameWidth, S5P_FIMV_D_DISPLAY_FRAME_WIDTH); // 0xF600 - MFC_WRITEL(pStr->DisplayFrameHeight, S5P_FIMV_D_DISPLAY_FRAME_HEIGHT); // 0xF604 - MFC_WRITEL(pStr->DisplayStatus, S5P_FIMV_D_DISPLAY_STATUS); // 0xF608 - MFC_WRITEL(pStr->DisplayFirstPlaneAddr, S5P_FIMV_D_DISPLAY_FIRST_PLANE_ADDR); // 0xF60C - MFC_WRITEL(pStr->DisplaySecondPlaneAddr, S5P_FIMV_D_DISPLAY_SECOND_PLANE_ADDR); // 0xF610 - MFC_WRITEL(pStr->DisplayThirdPlaneAddr,S5P_FIMV_D_DISPLAY_THIRD_PLANE_ADDR); // 0xF614 - MFC_WRITEL(pStr->DisplayFrameType, S5P_FIMV_D_DISPLAY_FRAME_TYPE); // 0xF618 - MFC_WRITEL(pStr->DisplayCropInfo1, S5P_FIMV_D_DISPLAY_CROP_INFO1); // 0xF61C - MFC_WRITEL(pStr->DisplayCropInfo2, S5P_FIMV_D_DISPLAY_CROP_INFO2); // 0xF620 - MFC_WRITEL(pStr->DisplayPictureProfile, S5P_FIMV_D_DISPLAY_PICTURE_PROFILE); // 0xF624 - MFC_WRITEL(pStr->DisplayAspectRatio, S5P_FIMV_D_DISPLAY_ASPECT_RATIO); // 0xF634 - MFC_WRITEL(pStr->DisplayExtendedAr, S5P_FIMV_D_DISPLAY_EXTENDED_AR); // 0xF638 - MFC_WRITEL(pStr->DecodedNalSize, S5P_FIMV_D_DECODED_NAL_SIZE); // 0xF664 - MFC_WRITEL(pStr->UsedDpbFlagUpper, S5P_FIMV_D_USED_DPB_FLAG_UPPER); // 0xF720 - MFC_WRITEL(pStr->UsedDpbFlagLower, S5P_FIMV_D_USED_DPB_FLAG_LOWER); // 0xF724 - MFC_WRITEL(pStr->SeiAvail, S5P_FIMV_D_SEI_AVAIL); // 0xF6DC - MFC_WRITEL(pStr->FramePackArrgmentId, S5P_FIMV_D_FRAME_PACK_ARRGMENT_ID); // 0xF6E0 - MFC_WRITEL(pStr->FramePackSeiInfo, S5P_FIMV_D_FRAME_PACK_SEI_INFO); // 0xF6E4 - MFC_WRITEL(pStr->FramePackGridPos, S5P_FIMV_D_FRAME_PACK_GRID_POS); // 0xF6E8 - MFC_WRITEL(pStr->DisplayRecoverySeiInfo, S5P_FIMV_D_DISPLAY_RECOVERY_SEI_INFO); // 0xF6EC - MFC_WRITEL(pStr->H264Info, S5P_FIMV_D_H264_INFO); // 0xF690 - MFC_WRITEL(pStr->DisplayFirstCrc, S5P_FIMV_D_DISPLAY_FIRST_PLANE_CRC); // 0xF628 - MFC_WRITEL(pStr->DisplaySecondCrc, S5P_FIMV_D_DISPLAY_SECOND_PLANE_CRC); // 0xF62C - MFC_WRITEL(pStr->DisplayThirdCrc, S5P_FIMV_D_DISPLAY_THIRD_PLANE_CRC); // 0xF630 - MFC_WRITEL(pStr->DisplayFirst2BitCrc, S5P_FIMV_D_DISPLAY_FIRST_PLANE_2BIT_CRC); // 0xF6FC - MFC_WRITEL(pStr->DisplaySecond2BitCrc, S5P_FIMV_D_DISPLAY_SECOND_PLANE_2BIT_CRC);// 0xF700 - MFC_WRITEL(pStr->DecodedFrameWidth, S5P_FIMV_D_DECODED_FRAME_WIDTH); // 0xF63C - MFC_WRITEL(pStr->DecodedFrameHeight, S5P_FIMV_D_DECODED_FRAME_HEIGHT); // 0xF640 - MFC_WRITEL(pStr->DecodedStatus, S5P_FIMV_D_DECODED_STATUS); // 0xF644 - MFC_WRITEL(pStr->DecodedFirstPlaneAddr, S5P_FIMV_D_DECODED_FIRST_PLANE_ADDR); // 0xF648 - MFC_WRITEL(pStr->DecodedSecondPlaneAddr, S5P_FIMV_D_DECODED_SECOND_PLANE_ADDR); // 0xF64C - MFC_WRITEL(pStr->DecodedThirdPlaneAddr, S5P_FIMV_D_DECODED_THIRD_PLANE_ADDR); // 0xF650 - MFC_WRITEL(pStr->DecodedFrameType, S5P_FIMV_D_DECODED_FRAME_TYPE); // 0xF654 - MFC_WRITEL(pStr->DecodedCropInfo1, S5P_FIMV_D_DECODED_CROP_INFO1); // 0xF658 - MFC_WRITEL(pStr->DecodedCropInfo2, S5P_FIMV_D_DECODED_CROP_INFO2); // 0xF65C - MFC_WRITEL(pStr->DecodedPictureProfile, S5P_FIMV_D_DECODED_PICTURE_PROFILE); // 0xF660 - MFC_WRITEL(pStr->DecodedRecoverySeiInfo, S5P_FIMV_D_DECODED_RECOVERY_SEI_INFO); // 0xF6F0 - MFC_WRITEL(pStr->DecodedFirstCrc, S5P_FIMV_D_DECODED_FIRST_PLANE_CRC); // 0xF668 - MFC_WRITEL(pStr->DecodedSecondCrc, S5P_FIMV_D_DECODED_SECOND_PLANE_CRC); // 0xF66C - MFC_WRITEL(pStr->DecodedThirdCrc, S5P_FIMV_D_DECODED_THIRD_PLANE_CRC); // 0xF670 - MFC_WRITEL(pStr->DecodedFirst2BitCrc, S5P_FIMV_D_DECODED_FIRST_PLANE_2BIT_CRC); // 0xF704 - MFC_WRITEL(pStr->DecodedSecond2BitCrc, S5P_FIMV_D_DECODED_SECOND_PLANE_2BIT_CRC);// 0xF708 - MFC_WRITEL(pStr->PictureTagBot, S5P_FIMV_D_RET_PICTURE_TAG_BOT); // 0xF678 - MFC_WRITEL(pStr->PictureTimeBot, S5P_FIMV_D_RET_PICTURE_TIME_BOT); // 0xF680 +// MFC_WRITEL(pStr->CommandId, MFC_REG_RISC2HOST_CMD); // 0x1104 + MFC_WRITEL(pStr->InstanceId, MFC_REG_RET_INSTANCE_ID); // 0xF070 + MFC_WRITEL(pStr->ErrorCode, MFC_REG_ERROR_CODE); // 0xF074 + MFC_WRITEL(pStr->PictureTagTop, MFC_REG_D_RET_PICTURE_TAG_TOP); // 0xF674 + MFC_WRITEL(pStr->PictureTimeTop, MFC_REG_D_RET_PICTURE_TIME_TOP); // 0xF67C + MFC_WRITEL(pStr->DisplayFrameWidth, MFC_REG_D_DISPLAY_FRAME_WIDTH); // 0xF600 + MFC_WRITEL(pStr->DisplayFrameHeight, MFC_REG_D_DISPLAY_FRAME_HEIGHT); // 0xF604 + MFC_WRITEL(pStr->DisplayStatus, MFC_REG_D_DISPLAY_STATUS); // 0xF608 + MFC_WRITEL(pStr->DisplayFirstPlaneAddr, MFC_REG_D_DISPLAY_FIRST_PLANE_ADDR); // 0xF60C + MFC_WRITEL(pStr->DisplaySecondPlaneAddr, MFC_REG_D_DISPLAY_SECOND_PLANE_ADDR); // 0xF610 + MFC_WRITEL(pStr->DisplayThirdPlaneAddr,MFC_REG_D_DISPLAY_THIRD_PLANE_ADDR); // 0xF614 + MFC_WRITEL(pStr->DisplayFrameType, MFC_REG_D_DISPLAY_FRAME_TYPE); // 0xF618 + MFC_WRITEL(pStr->DisplayCropInfo1, MFC_REG_D_DISPLAY_CROP_INFO1); // 0xF61C + MFC_WRITEL(pStr->DisplayCropInfo2, MFC_REG_D_DISPLAY_CROP_INFO2); // 0xF620 + MFC_WRITEL(pStr->DisplayPictureProfile, MFC_REG_D_DISPLAY_PICTURE_PROFILE); // 0xF624 + MFC_WRITEL(pStr->DisplayAspectRatio, MFC_REG_D_DISPLAY_ASPECT_RATIO); // 0xF634 + MFC_WRITEL(pStr->DisplayExtendedAr, MFC_REG_D_DISPLAY_EXTENDED_AR); // 0xF638 + MFC_WRITEL(pStr->DecodedNalSize, MFC_REG_D_DECODED_NAL_SIZE); // 0xF664 + MFC_WRITEL(pStr->UsedDpbFlagUpper, MFC_REG_D_USED_DPB_FLAG_UPPER); // 0xF720 + MFC_WRITEL(pStr->UsedDpbFlagLower, MFC_REG_D_USED_DPB_FLAG_LOWER); // 0xF724 + MFC_WRITEL(pStr->SeiAvail, MFC_REG_D_SEI_AVAIL); // 0xF6DC + MFC_WRITEL(pStr->FramePackArrgmentId, MFC_REG_D_FRAME_PACK_ARRGMENT_ID); // 0xF6E0 + MFC_WRITEL(pStr->FramePackSeiInfo, MFC_REG_D_FRAME_PACK_SEI_INFO); // 0xF6E4 + MFC_WRITEL(pStr->FramePackGridPos, MFC_REG_D_FRAME_PACK_GRID_POS); // 0xF6E8 + MFC_WRITEL(pStr->DisplayRecoverySeiInfo, MFC_REG_D_DISPLAY_RECOVERY_SEI_INFO); // 0xF6EC + MFC_WRITEL(pStr->H264Info, MFC_REG_D_H264_INFO); // 0xF690 + MFC_WRITEL(pStr->DisplayFirstCrc, MFC_REG_D_DISPLAY_FIRST_PLANE_CRC); // 0xF628 + MFC_WRITEL(pStr->DisplaySecondCrc, MFC_REG_D_DISPLAY_SECOND_PLANE_CRC); // 0xF62C + MFC_WRITEL(pStr->DisplayThirdCrc, MFC_REG_D_DISPLAY_THIRD_PLANE_CRC); // 0xF630 + MFC_WRITEL(pStr->DisplayFirst2BitCrc, MFC_REG_D_DISPLAY_FIRST_PLANE_2BIT_CRC); // 0xF6FC + MFC_WRITEL(pStr->DisplaySecond2BitCrc, MFC_REG_D_DISPLAY_SECOND_PLANE_2BIT_CRC);// 0xF700 + MFC_WRITEL(pStr->DecodedFrameWidth, MFC_REG_D_DECODED_FRAME_WIDTH); // 0xF63C + MFC_WRITEL(pStr->DecodedFrameHeight, MFC_REG_D_DECODED_FRAME_HEIGHT); // 0xF640 + MFC_WRITEL(pStr->DecodedStatus, MFC_REG_D_DECODED_STATUS); // 0xF644 + MFC_WRITEL(pStr->DecodedFirstPlaneAddr, MFC_REG_D_DECODED_FIRST_PLANE_ADDR); // 0xF648 + MFC_WRITEL(pStr->DecodedSecondPlaneAddr, MFC_REG_D_DECODED_SECOND_PLANE_ADDR); // 0xF64C + MFC_WRITEL(pStr->DecodedThirdPlaneAddr, MFC_REG_D_DECODED_THIRD_PLANE_ADDR); // 0xF650 + MFC_WRITEL(pStr->DecodedFrameType, MFC_REG_D_DECODED_FRAME_TYPE); // 0xF654 + MFC_WRITEL(pStr->DecodedCropInfo1, MFC_REG_D_DECODED_CROP_INFO1); // 0xF658 + MFC_WRITEL(pStr->DecodedCropInfo2, MFC_REG_D_DECODED_CROP_INFO2); // 0xF65C + MFC_WRITEL(pStr->DecodedPictureProfile, MFC_REG_D_DECODED_PICTURE_PROFILE); // 0xF660 + MFC_WRITEL(pStr->DecodedRecoverySeiInfo, MFC_REG_D_DECODED_RECOVERY_SEI_INFO); // 0xF6F0 + MFC_WRITEL(pStr->DecodedFirstCrc, MFC_REG_D_DECODED_FIRST_PLANE_CRC); // 0xF668 + MFC_WRITEL(pStr->DecodedSecondCrc, MFC_REG_D_DECODED_SECOND_PLANE_CRC); // 0xF66C + MFC_WRITEL(pStr->DecodedThirdCrc, MFC_REG_D_DECODED_THIRD_PLANE_CRC); // 0xF670 + MFC_WRITEL(pStr->DecodedFirst2BitCrc, MFC_REG_D_DECODED_FIRST_PLANE_2BIT_CRC); // 0xF704 + MFC_WRITEL(pStr->DecodedSecond2BitCrc, MFC_REG_D_DECODED_SECOND_PLANE_2BIT_CRC);// 0xF708 + MFC_WRITEL(pStr->PictureTagBot, MFC_REG_D_RET_PICTURE_TAG_BOT); // 0xF678 + MFC_WRITEL(pStr->PictureTimeBot, MFC_REG_D_RET_PICTURE_TIME_BOT); // 0xF680 } #endif diff --git a/drivers/media/platform/exynos/mfc/mfc_nal_q.h b/drivers/media/platform/exynos/mfc/mfc_nal_q.h index ccf7900e3a4f..bbf1557b1d52 100644 --- a/drivers/media/platform/exynos/mfc/mfc_nal_q.h +++ b/drivers/media/platform/exynos/mfc/mfc_nal_q.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_nal_q.h + * drivers/media/platform/exynos/mfc/mfc_nal_q.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -15,25 +15,25 @@ #include "mfc_common.h" -int s5p_mfc_nal_q_check_enable(struct s5p_mfc_dev *dev); +int mfc_nal_q_check_enable(struct mfc_dev *dev); -void s5p_mfc_nal_q_clock_on(struct s5p_mfc_dev *dev, nal_queue_handle *nal_q_handle); -void s5p_mfc_nal_q_clock_off(struct s5p_mfc_dev *dev, nal_queue_handle *nal_q_handle); -void s5p_mfc_nal_q_cleanup_clock(struct s5p_mfc_dev *dev); +void mfc_nal_q_clock_on(struct mfc_dev *dev, nal_queue_handle *nal_q_handle); +void mfc_nal_q_clock_off(struct mfc_dev *dev, nal_queue_handle *nal_q_handle); +void mfc_nal_q_cleanup_clock(struct mfc_dev *dev); -nal_queue_handle *s5p_mfc_nal_q_create(struct s5p_mfc_dev *dev); -int s5p_mfc_nal_q_destroy(struct s5p_mfc_dev *dev, nal_queue_handle *nal_q_handle); +nal_queue_handle *mfc_nal_q_create(struct mfc_dev *dev); +int mfc_nal_q_destroy(struct mfc_dev *dev, nal_queue_handle *nal_q_handle); -void s5p_mfc_nal_q_init(struct s5p_mfc_dev *dev, nal_queue_handle *nal_q_handle); -void s5p_mfc_nal_q_start(struct s5p_mfc_dev *dev, nal_queue_handle *nal_q_handle); -void s5p_mfc_nal_q_stop(struct s5p_mfc_dev *dev, nal_queue_handle *nal_q_handle); -void s5p_mfc_nal_q_stop_if_started(struct s5p_mfc_dev *dev); -void s5p_mfc_nal_q_cleanup_queue(struct s5p_mfc_dev *dev); +void mfc_nal_q_init(struct mfc_dev *dev, nal_queue_handle *nal_q_handle); +void mfc_nal_q_start(struct mfc_dev *dev, nal_queue_handle *nal_q_handle); +void mfc_nal_q_stop(struct mfc_dev *dev, nal_queue_handle *nal_q_handle); +void mfc_nal_q_stop_if_started(struct mfc_dev *dev); +void mfc_nal_q_cleanup_queue(struct mfc_dev *dev); -int s5p_mfc_nal_q_handle_out_buf(struct s5p_mfc_dev *dev, EncoderOutputStr *pOutStr); -int s5p_mfc_nal_q_enqueue_in_buf(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx, +int mfc_nal_q_handle_out_buf(struct mfc_dev *dev, EncoderOutputStr *pOutStr); +int mfc_nal_q_enqueue_in_buf(struct mfc_dev *dev, struct mfc_ctx *ctx, nal_queue_in_handle *nal_q_in_handle); -EncoderOutputStr *s5p_mfc_nal_q_dequeue_out_buf(struct s5p_mfc_dev *dev, +EncoderOutputStr *mfc_nal_q_dequeue_out_buf(struct mfc_dev *dev, nal_queue_out_handle *nal_q_out_handle, unsigned int *reason); #endif /* __MFC_NAL_Q_H */ diff --git a/drivers/media/platform/exynos/mfc/mfc_opr.c b/drivers/media/platform/exynos/mfc/mfc_opr.c index 4fe9df0843b4..776e67363375 100644 --- a/drivers/media/platform/exynos/mfc/mfc_opr.c +++ b/drivers/media/platform/exynos/mfc/mfc_opr.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_opr.c + * drivers/media/platform/exynos/mfc/mfc_opr.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -19,11 +19,11 @@ #include "mfc_utils.h" #include "mfc_mem.h" -int s5p_mfc_run_dec_init(struct s5p_mfc_ctx *ctx) +int mfc_run_dec_init(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev; - struct s5p_mfc_buf *src_mb; - struct s5p_mfc_dec *dec = NULL; + struct mfc_dev *dev; + struct mfc_buf *src_mb; + struct mfc_dec *dec = NULL; if (!ctx) { mfc_err_dev("no mfc context to run\n"); @@ -38,7 +38,7 @@ int s5p_mfc_run_dec_init(struct s5p_mfc_ctx *ctx) /* Initializing decoding - parsing header */ /* Get the next source buffer */ - src_mb = s5p_mfc_get_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, MFC_BUF_NO_TOUCH_USED); + src_mb = mfc_get_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, MFC_BUF_NO_TOUCH_USED); if (!src_mb) { mfc_err_dev("no src buffers\n"); return -EAGAIN; @@ -49,42 +49,42 @@ int s5p_mfc_run_dec_init(struct s5p_mfc_ctx *ctx) src_mb->vb.vb2_buf.planes[0].bytesused, dec->consumed); if (dec->consumed) { - s5p_mfc_set_dec_stream_buffer(ctx, src_mb, dec->consumed, dec->remained_size); + mfc_set_dec_stream_buffer(ctx, src_mb, dec->consumed, dec->remained_size); } else { /* decoder src buffer CFW PROT */ if (ctx->is_drm) { int index = src_mb->vb.vb2_buf.index; - s5p_mfc_stream_protect(ctx, src_mb, index); + mfc_stream_protect(ctx, src_mb, index); } - s5p_mfc_set_dec_stream_buffer(ctx, src_mb, + mfc_set_dec_stream_buffer(ctx, src_mb, 0, src_mb->vb.vb2_buf.planes[0].bytesused); } mfc_debug(2, "Header addr: 0x%08llx\n", src_mb->addr[0][0]); - s5p_mfc_clean_ctx_int_flags(ctx); - s5p_mfc_init_decode(ctx); + mfc_clean_ctx_int_flags(ctx); + mfc_init_decode(ctx); return 0; } -static int mfc_check_last_frame(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *mfc_buf) +static int __mfc_check_last_frame(struct mfc_ctx *ctx, struct mfc_buf *mfc_buf) { if (mfc_buf->vb.reserved2 & FLAG_LAST_FRAME) { mfc_debug(2, "Setting ctx->state to FINISHING\n"); - s5p_mfc_change_state(ctx, MFCINST_FINISHING); + mfc_change_state(ctx, MFCINST_FINISHING); return 1; } return 0; } -int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx) +int mfc_run_dec_frame(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev; - struct s5p_mfc_buf *src_mb, *dst_mb; - struct s5p_mfc_dec *dec; + struct mfc_dev *dev; + struct mfc_buf *src_mb, *dst_mb; + struct mfc_dec *dec; int last_frame = 0; unsigned int index; @@ -99,14 +99,14 @@ int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx) return -EINVAL; } - if (s5p_mfc_is_queue_count_same(&ctx->buf_queue_lock, &ctx->dst_buf_queue, 0) && - s5p_mfc_is_queue_count_smaller(&ctx->buf_queue_lock, + if (mfc_is_queue_count_same(&ctx->buf_queue_lock, &ctx->dst_buf_queue, 0) && + mfc_is_queue_count_smaller(&ctx->buf_queue_lock, &ctx->ref_buf_queue, (ctx->dpb_count + 5))) { return -EAGAIN; } /* Get the next source buffer */ - src_mb = s5p_mfc_get_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, MFC_BUF_SET_USED); + src_mb = mfc_get_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, MFC_BUF_SET_USED); if (!src_mb) { mfc_debug(2, "no src buffers\n"); return -EAGAIN; @@ -116,7 +116,7 @@ int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx) if (ctx->is_drm) { if (!dec->consumed) { index = src_mb->vb.vb2_buf.index; - s5p_mfc_stream_protect(ctx, src_mb, index); + mfc_stream_protect(ctx, src_mb, index); } } @@ -124,12 +124,12 @@ int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx) src_mb->vb.vb2_buf.planes[0].bytesused = 0; if (dec->consumed) - s5p_mfc_set_dec_stream_buffer(ctx, src_mb, dec->consumed, dec->remained_size); + mfc_set_dec_stream_buffer(ctx, src_mb, dec->consumed, dec->remained_size); else - s5p_mfc_set_dec_stream_buffer(ctx, src_mb, 0, src_mb->vb.vb2_buf.planes[0].bytesused); + mfc_set_dec_stream_buffer(ctx, src_mb, 0, src_mb->vb.vb2_buf.planes[0].bytesused); /* Try to use the non-referenced DPB on dst-queue */ - dst_mb = s5p_mfc_search_for_dpb(ctx, dec->dynamic_used); + dst_mb = mfc_search_for_dpb(ctx, dec->dynamic_used); if (!dst_mb) { mfc_debug(2, "[DPB] couldn't find dst buffers\n"); return -EAGAIN; @@ -139,21 +139,21 @@ int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx) if (call_cop(ctx, set_buf_ctrls_val, ctx, &ctx->src_ctrls[index]) < 0) mfc_err_ctx("failed in set_buf_ctrls_val\n"); - s5p_mfc_set_dynamic_dpb(ctx, dst_mb); + mfc_set_dynamic_dpb(ctx, dst_mb); - s5p_mfc_clean_ctx_int_flags(ctx); + mfc_clean_ctx_int_flags(ctx); - last_frame = mfc_check_last_frame(ctx, src_mb); - s5p_mfc_decode_one_frame(ctx, last_frame); + last_frame = __mfc_check_last_frame(ctx, src_mb); + mfc_decode_one_frame(ctx, last_frame); return 0; } -int s5p_mfc_run_dec_last_frames(struct s5p_mfc_ctx *ctx) +int mfc_run_dec_last_frames(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev; - struct s5p_mfc_buf *src_mb, *dst_mb; - struct s5p_mfc_dec *dec; + struct mfc_dev *dev; + struct mfc_buf *src_mb, *dst_mb; + struct mfc_dec *dec; if (!ctx) { mfc_err_dev("no mfc context to run\n"); @@ -172,54 +172,54 @@ int s5p_mfc_run_dec_last_frames(struct s5p_mfc_ctx *ctx) return -EINVAL; } - if (s5p_mfc_is_queue_count_same(&ctx->buf_queue_lock, &ctx->dst_buf_queue, 0)) { + if (mfc_is_queue_count_same(&ctx->buf_queue_lock, &ctx->dst_buf_queue, 0)) { mfc_debug(2, "no dst buffer\n"); return -EAGAIN; } /* Get the next source buffer */ - src_mb = s5p_mfc_get_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, MFC_BUF_SET_USED); + src_mb = mfc_get_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, MFC_BUF_SET_USED); /* Frames are being decoded */ if (!src_mb) { mfc_debug(2, "no src buffers\n"); - s5p_mfc_set_dec_stream_buffer(ctx, 0, 0, 0); + mfc_set_dec_stream_buffer(ctx, 0, 0, 0); } else { if (dec->consumed) { - s5p_mfc_set_dec_stream_buffer(ctx, src_mb, dec->consumed, dec->remained_size); + mfc_set_dec_stream_buffer(ctx, src_mb, dec->consumed, dec->remained_size); } else { /* decoder src buffer CFW PROT */ if (ctx->is_drm) { int index = src_mb->vb.vb2_buf.index; - s5p_mfc_stream_protect(ctx, src_mb, index); + mfc_stream_protect(ctx, src_mb, index); } - s5p_mfc_set_dec_stream_buffer(ctx, src_mb, 0, 0); + mfc_set_dec_stream_buffer(ctx, src_mb, 0, 0); } } /* Try to use the non-referenced DPB on dst-queue */ - dst_mb = s5p_mfc_search_for_dpb(ctx, dec->dynamic_used); + dst_mb = mfc_search_for_dpb(ctx, dec->dynamic_used); if (!dst_mb) { mfc_debug(2, "[DPB] couldn't find dst buffers\n"); return -EAGAIN; } - s5p_mfc_set_dynamic_dpb(ctx, dst_mb); + mfc_set_dynamic_dpb(ctx, dst_mb); - s5p_mfc_clean_ctx_int_flags(ctx); - s5p_mfc_decode_one_frame(ctx, 1); + mfc_clean_ctx_int_flags(ctx); + mfc_decode_one_frame(ctx, 1); return 0; } -int s5p_mfc_run_enc_init(struct s5p_mfc_ctx *ctx) +int mfc_run_enc_init(struct mfc_ctx *ctx) { - struct s5p_mfc_buf *dst_mb; + struct mfc_buf *dst_mb; int ret; - dst_mb = s5p_mfc_get_buf(&ctx->buf_queue_lock, &ctx->dst_buf_queue, MFC_BUF_NO_TOUCH_USED); + dst_mb = mfc_get_buf(&ctx->buf_queue_lock, &ctx->dst_buf_queue, MFC_BUF_NO_TOUCH_USED); if (!dst_mb) { mfc_debug(2, "no dst buffers\n"); return -EAGAIN; @@ -229,31 +229,31 @@ int s5p_mfc_run_enc_init(struct s5p_mfc_ctx *ctx) if (ctx->is_drm) { int index = dst_mb->vb.vb2_buf.index; - s5p_mfc_stream_protect(ctx, dst_mb, index); + mfc_stream_protect(ctx, dst_mb, index); } - s5p_mfc_set_enc_stream_buffer(ctx, dst_mb); + mfc_set_enc_stream_buffer(ctx, dst_mb); - s5p_mfc_set_enc_stride(ctx); + mfc_set_enc_stride(ctx); mfc_debug(2, "Header addr: 0x%08llx\n", dst_mb->addr[0][0]); - s5p_mfc_clean_ctx_int_flags(ctx); + mfc_clean_ctx_int_flags(ctx); - ret = s5p_mfc_init_encode(ctx); + ret = mfc_init_encode(ctx); return ret; } -int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx) +int mfc_run_enc_frame(struct mfc_ctx *ctx) { - struct s5p_mfc_buf *dst_mb; - struct s5p_mfc_buf *src_mb; - struct s5p_mfc_raw_info *raw; + struct mfc_buf *dst_mb; + struct mfc_buf *src_mb; + struct mfc_raw_info *raw; unsigned int index, i; int last_frame = 0; raw = &ctx->raw_buf; /* Get the next source buffer */ - src_mb = s5p_mfc_get_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, MFC_BUF_SET_USED); + src_mb = mfc_get_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, MFC_BUF_SET_USED); if (!src_mb) { mfc_debug(2, "no src buffers\n"); return -EAGAIN; @@ -263,21 +263,21 @@ int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx) /* last image in a buffer container */ if (src_mb->next_index == (src_mb->num_valid_bufs - 1)) { mfc_debug(4, "[BUFCON] last image in a container\n"); - last_frame = mfc_check_last_frame(ctx, src_mb); + last_frame = __mfc_check_last_frame(ctx, src_mb); } } else { - last_frame = mfc_check_last_frame(ctx, src_mb); + last_frame = __mfc_check_last_frame(ctx, src_mb); } index = src_mb->vb.vb2_buf.index; /* encoder src buffer CFW PROT */ if (ctx->is_drm) - s5p_mfc_raw_protect(ctx, src_mb, index); + mfc_raw_protect(ctx, src_mb, index); - s5p_mfc_set_enc_frame_buffer(ctx, src_mb, raw->num_planes); + mfc_set_enc_frame_buffer(ctx, src_mb, raw->num_planes); - dst_mb = s5p_mfc_get_buf(&ctx->buf_queue_lock, &ctx->dst_buf_queue, MFC_BUF_SET_USED); + dst_mb = mfc_get_buf(&ctx->buf_queue_lock, &ctx->dst_buf_queue, MFC_BUF_SET_USED); if (!dst_mb) { mfc_debug(2, "no dst buffers\n"); return -EAGAIN; @@ -286,51 +286,51 @@ int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx) /* encoder dst buffer CFW PROT */ if (ctx->is_drm) { i = dst_mb->vb.vb2_buf.index; - s5p_mfc_stream_protect(ctx, dst_mb, i); + mfc_stream_protect(ctx, dst_mb, i); } mfc_debug(2, "nal start : src index from src_buf_queue:%d\n", src_mb->vb.vb2_buf.index); mfc_debug(2, "nal start : dst index from dst_buf_queue:%d\n", dst_mb->vb.vb2_buf.index); - s5p_mfc_set_enc_stream_buffer(ctx, dst_mb); + mfc_set_enc_stream_buffer(ctx, dst_mb); if (call_cop(ctx, set_buf_ctrls_val, ctx, &ctx->src_ctrls[index]) < 0) mfc_err_ctx("failed in set_buf_ctrls_val\n"); - s5p_mfc_clean_ctx_int_flags(ctx); - s5p_mfc_encode_one_frame(ctx, last_frame); + mfc_clean_ctx_int_flags(ctx); + mfc_encode_one_frame(ctx, last_frame); return 0; } -int s5p_mfc_run_enc_last_frames(struct s5p_mfc_ctx *ctx) +int mfc_run_enc_last_frames(struct mfc_ctx *ctx) { - struct s5p_mfc_buf *dst_mb; - struct s5p_mfc_raw_info *raw; + struct mfc_buf *dst_mb; + struct mfc_raw_info *raw; raw = &ctx->raw_buf; - dst_mb = s5p_mfc_get_buf(&ctx->buf_queue_lock, &ctx->dst_buf_queue, MFC_BUF_SET_USED); + dst_mb = mfc_get_buf(&ctx->buf_queue_lock, &ctx->dst_buf_queue, MFC_BUF_SET_USED); if (!dst_mb) { mfc_debug(2, "no dst buffers\n"); return -EAGAIN; } mfc_debug(2, "Set address zero for all planes\n"); - s5p_mfc_set_enc_frame_buffer(ctx, 0, raw->num_planes); + mfc_set_enc_frame_buffer(ctx, 0, raw->num_planes); /* encoder dst buffer CFW PROT */ if (ctx->is_drm) { int index = dst_mb->vb.vb2_buf.index; - s5p_mfc_stream_protect(ctx, dst_mb, index); + mfc_stream_protect(ctx, dst_mb, index); } - s5p_mfc_set_enc_stream_buffer(ctx, dst_mb); + mfc_set_enc_stream_buffer(ctx, dst_mb); - s5p_mfc_clean_ctx_int_flags(ctx); - s5p_mfc_encode_one_frame(ctx, 1); + mfc_clean_ctx_int_flags(ctx); + mfc_encode_one_frame(ctx, 1); return 0; } diff --git a/drivers/media/platform/exynos/mfc/mfc_opr.h b/drivers/media/platform/exynos/mfc/mfc_opr.h index 36bd24ff114c..75b2984f9c6c 100644 --- a/drivers/media/platform/exynos/mfc/mfc_opr.h +++ b/drivers/media/platform/exynos/mfc/mfc_opr.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_opr.h + * drivers/media/platform/exynos/mfc/mfc_opr.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -15,11 +15,11 @@ #include "mfc_common.h" -int s5p_mfc_run_dec_init(struct s5p_mfc_ctx *ctx); -int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx); -int s5p_mfc_run_dec_last_frames(struct s5p_mfc_ctx *ctx); -int s5p_mfc_run_enc_init(struct s5p_mfc_ctx *ctx); -int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx); -int s5p_mfc_run_enc_last_frames(struct s5p_mfc_ctx *ctx); +int mfc_run_dec_init(struct mfc_ctx *ctx); +int mfc_run_dec_frame(struct mfc_ctx *ctx); +int mfc_run_dec_last_frames(struct mfc_ctx *ctx); +int mfc_run_enc_init(struct mfc_ctx *ctx); +int mfc_run_enc_frame(struct mfc_ctx *ctx); +int mfc_run_enc_last_frames(struct mfc_ctx *ctx); #endif /* __MFC_OPR_H */ diff --git a/drivers/media/platform/exynos/mfc/mfc_otf.c b/drivers/media/platform/exynos/mfc/mfc_otf.c index 08ed51de234c..c16c94c86f1a 100644 --- a/drivers/media/platform/exynos/mfc/mfc_otf.c +++ b/drivers/media/platform/exynos/mfc/mfc_otf.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_otf.c + * drivers/media/platform/exynos/mfc/mfc_otf.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -34,7 +34,7 @@ #include "mfc_buf.h" #include "mfc_mem.h" -static struct s5p_mfc_fmt *mfc_enc_hwfc_find_format(unsigned int pixelformat) +static struct mfc_fmt *__mfc_enc_hwfc_find_format(unsigned int pixelformat) { unsigned long i; @@ -42,7 +42,7 @@ static struct s5p_mfc_fmt *mfc_enc_hwfc_find_format(unsigned int pixelformat) for (i = 0; i < NUM_FORMATS; i++) { if (enc_hwfc_formats[i].fourcc == pixelformat) - return (struct s5p_mfc_fmt *)&enc_hwfc_formats[i]; + return (struct mfc_fmt *)&enc_hwfc_formats[i]; } mfc_debug_leave(); @@ -50,14 +50,14 @@ static struct s5p_mfc_fmt *mfc_enc_hwfc_find_format(unsigned int pixelformat) return NULL; } -static int mfc_otf_set_buf_info(struct s5p_mfc_ctx *ctx) +static int __mfc_otf_set_buf_info(struct mfc_ctx *ctx) { struct _otf_handle *handle = ctx->otf_handle; struct _otf_buf_info *buf_info = &handle->otf_buf_info; mfc_debug_enter(); - ctx->src_fmt = mfc_enc_hwfc_find_format(buf_info->pixel_format); + ctx->src_fmt = __mfc_enc_hwfc_find_format(buf_info->pixel_format); if (!ctx->src_fmt) { mfc_err_ctx("[OTF] failed to set source format\n"); return -EINVAL; @@ -76,20 +76,20 @@ static int mfc_otf_set_buf_info(struct s5p_mfc_ctx *ctx) ctx->buf_stride = ALIGN(ctx->img_width, 16); /* calculate source size */ - s5p_mfc_enc_calc_src_size(ctx); + mfc_enc_calc_src_size(ctx); mfc_debug_leave(); return 0; } -static int mfc_otf_map_buf(struct s5p_mfc_ctx *ctx) +static int __mfc_otf_map_buf(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; struct _otf_handle *handle = ctx->otf_handle; struct _otf_buf_addr *buf_addr = &handle->otf_buf_addr; struct _otf_buf_info *buf_info = &handle->otf_buf_info; - struct s5p_mfc_raw_info *raw = &ctx->raw_buf; + struct mfc_raw_info *raw = &ctx->raw_buf; int i; mfc_debug_enter(); @@ -129,7 +129,7 @@ static int mfc_otf_map_buf(struct s5p_mfc_ctx *ctx) return 0; } -static void mfc_otf_unmap_buf(struct s5p_mfc_ctx *ctx) +static void __mfc_otf_unmap_buf(struct mfc_ctx *ctx) { struct _otf_handle *handle = ctx->otf_handle; struct _otf_buf_addr *buf_addr = &handle->otf_buf_addr; @@ -152,7 +152,7 @@ static void mfc_otf_unmap_buf(struct s5p_mfc_ctx *ctx) mfc_debug_leave(); } -static void mfc_otf_put_buf(struct s5p_mfc_ctx *ctx) +static void __mfc_otf_put_buf(struct mfc_ctx *ctx) { struct _otf_handle *handle = ctx->otf_handle; struct _otf_buf_info *buf_info = &handle->otf_buf_info; @@ -171,7 +171,7 @@ static void mfc_otf_put_buf(struct s5p_mfc_ctx *ctx) } -static int mfc_otf_init_hwfc_buf(struct s5p_mfc_ctx *ctx) +static int __mfc_otf_init_hwfc_buf(struct mfc_ctx *ctx) { #ifdef CONFIG_VIDEO_EXYNOS_REPEATER struct shared_buffer_info *shared_buf_info; @@ -192,16 +192,16 @@ static int mfc_otf_init_hwfc_buf(struct s5p_mfc_ctx *ctx) mfc_debug(2, "[OTF] recieved buffer information\n"); /* set buffer information to ctx, and calculate buffer size */ - if (mfc_otf_set_buf_info(ctx)) { + if (__mfc_otf_set_buf_info(ctx)) { mfc_err_ctx("[OTF] failed to set buffer information\n"); - mfc_otf_put_buf(ctx); + __mfc_otf_put_buf(ctx); return -EINVAL; } - if (mfc_otf_map_buf(ctx)) { + if (__mfc_otf_map_buf(ctx)) { mfc_err_ctx("[OTF] failed to map buffers\n"); - mfc_otf_unmap_buf(ctx); - mfc_otf_put_buf(ctx); + __mfc_otf_unmap_buf(ctx); + __mfc_otf_put_buf(ctx); return -EINVAL; } mfc_debug(2, "[OTF] HWFC buffer initialized\n"); @@ -211,18 +211,18 @@ static int mfc_otf_init_hwfc_buf(struct s5p_mfc_ctx *ctx) return 0; } -static void mfc_otf_deinit_hwfc_buf(struct s5p_mfc_ctx *ctx) +static void __mfc_otf_deinit_hwfc_buf(struct mfc_ctx *ctx) { mfc_debug_enter(); - mfc_otf_unmap_buf(ctx); - mfc_otf_put_buf(ctx); + __mfc_otf_unmap_buf(ctx); + __mfc_otf_put_buf(ctx); mfc_debug(2, "[OTF] HWFC buffer de-initialized\n"); mfc_debug_leave(); } -static int mfc_otf_create_handle(struct s5p_mfc_ctx *ctx) +static int __mfc_otf_create_handle(struct mfc_ctx *ctx) { struct _otf_handle *otf_handle; @@ -245,7 +245,7 @@ static int mfc_otf_create_handle(struct s5p_mfc_ctx *ctx) return 0; } -static void mfc_otf_destroy_handle(struct s5p_mfc_ctx *ctx) +static void __mfc_otf_destroy_handle(struct mfc_ctx *ctx) { mfc_debug_enter(); @@ -261,9 +261,9 @@ static void mfc_otf_destroy_handle(struct s5p_mfc_ctx *ctx) mfc_debug_leave(); } -int s5p_mfc_otf_create(struct s5p_mfc_ctx *ctx) +int mfc_otf_create(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev; + struct mfc_dev *dev; int i; mfc_debug_enter(); @@ -286,16 +286,16 @@ int s5p_mfc_otf_create(struct s5p_mfc_ctx *ctx) } } - if (mfc_otf_create_handle(ctx)) { + if (__mfc_otf_create_handle(ctx)) { mfc_err_dev("[OTF] otf_handle is not created\n"); return -EINVAL; } if (otf_dump) { /* It is for debugging. Do not return error */ - if (s5p_mfc_otf_alloc_stream_buf(ctx)) { + if (mfc_otf_alloc_stream_buf(ctx)) { mfc_err_dev("[OTF] stream buffer allocation failed\n"); - s5p_mfc_otf_release_stream_buf(ctx); + mfc_otf_release_stream_buf(ctx); } } @@ -306,7 +306,7 @@ int s5p_mfc_otf_create(struct s5p_mfc_ctx *ctx) return 0; } -void s5p_mfc_otf_destroy(struct s5p_mfc_ctx *ctx) +void mfc_otf_destroy(struct mfc_ctx *ctx) { mfc_debug_enter(); @@ -315,14 +315,14 @@ void s5p_mfc_otf_destroy(struct s5p_mfc_ctx *ctx) return; } - s5p_mfc_otf_release_stream_buf(ctx); - mfc_otf_destroy_handle(ctx); + mfc_otf_release_stream_buf(ctx); + __mfc_otf_destroy_handle(ctx); mfc_debug(2, "[OTF] otf_destroy is completed\n"); mfc_debug_leave(); } -int s5p_mfc_otf_init(struct s5p_mfc_ctx *ctx) +int mfc_otf_init(struct mfc_ctx *ctx) { mfc_debug_enter(); @@ -336,7 +336,7 @@ int s5p_mfc_otf_init(struct s5p_mfc_ctx *ctx) return -EINVAL; } - if (mfc_otf_init_hwfc_buf(ctx)) { + if (__mfc_otf_init_hwfc_buf(ctx)) { mfc_err_dev("[OTF] HWFC init failed\n"); return -EINVAL; } @@ -348,7 +348,7 @@ int s5p_mfc_otf_init(struct s5p_mfc_ctx *ctx) return 0; } -void s5p_mfc_otf_deinit(struct s5p_mfc_ctx *ctx) +void mfc_otf_deinit(struct mfc_ctx *ctx) { mfc_debug_enter(); @@ -357,15 +357,15 @@ void s5p_mfc_otf_deinit(struct s5p_mfc_ctx *ctx) return; } - mfc_otf_deinit_hwfc_buf(ctx); + __mfc_otf_deinit_hwfc_buf(ctx); mfc_debug(2, "[OTF] deinit_otf is completed\n"); mfc_debug_leave(); } -int s5p_mfc_otf_ctx_ready(struct s5p_mfc_ctx *ctx) +int mfc_otf_ctx_ready(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; struct _otf_handle *handle; mfc_debug_enter(); @@ -398,26 +398,26 @@ int s5p_mfc_otf_ctx_ready(struct s5p_mfc_ctx *ctx) return 0; } -int s5p_mfc_otf_run_enc_init(struct s5p_mfc_ctx *ctx) +int mfc_otf_run_enc_init(struct mfc_ctx *ctx) { int ret; mfc_debug_enter(); - s5p_mfc_set_enc_stride(ctx); - s5p_mfc_clean_ctx_int_flags(ctx); - ret = s5p_mfc_init_encode(ctx); + mfc_set_enc_stride(ctx); + mfc_clean_ctx_int_flags(ctx); + ret = mfc_init_encode(ctx); mfc_debug_leave(); return ret; } -int s5p_mfc_otf_run_enc_frame(struct s5p_mfc_ctx *ctx) +int mfc_otf_run_enc_frame(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; struct _otf_handle *handle = ctx->otf_handle; - struct s5p_mfc_raw_info *raw; + struct mfc_raw_info *raw; mfc_debug_enter(); @@ -439,9 +439,9 @@ int s5p_mfc_otf_run_enc_frame(struct s5p_mfc_ctx *ctx) return -EINVAL; } - s5p_mfc_otf_set_frame_addr(ctx, raw->num_planes); - s5p_mfc_otf_set_stream_size(ctx, raw->total_plane_size); - s5p_mfc_otf_set_hwfc_index(ctx, handle->otf_job_id); + mfc_otf_set_frame_addr(ctx, raw->num_planes); + mfc_otf_set_stream_size(ctx, raw->total_plane_size); + mfc_otf_set_hwfc_index(ctx, handle->otf_job_id); if (call_cop(ctx, init_buf_ctrls, ctx, MFC_CTRL_TYPE_SRC, handle->otf_buf_index) < 0) mfc_err_ctx("failed in init_buf_ctrls\n"); @@ -451,37 +451,37 @@ int s5p_mfc_otf_run_enc_frame(struct s5p_mfc_ctx *ctx) mfc_err_ctx("[OTF] failed in set_buf_ctrls_val\n"); /* Change timestamp usec -> nsec */ - s5p_mfc_qos_update_last_framerate(ctx, handle->otf_time_stamp * 1000); - s5p_mfc_qos_update_framerate(ctx); + mfc_qos_update_last_framerate(ctx, handle->otf_time_stamp * 1000); + mfc_qos_update_framerate(ctx); /* Set stream buffer size to handle buffer full */ - s5p_mfc_clean_ctx_int_flags(ctx); - s5p_mfc_encode_one_frame(ctx, 0); + mfc_clean_ctx_int_flags(ctx); + mfc_encode_one_frame(ctx, 0); mfc_debug_leave(); return 0; } -int s5p_mfc_otf_handle_seq(struct s5p_mfc_ctx *ctx) +int mfc_otf_handle_seq(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_enc *enc = ctx->enc_priv; + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; mfc_debug_enter(); - enc->header_size = s5p_mfc_get_enc_strm_size(); - ctx->dpb_count = s5p_mfc_get_enc_dpb_count(); - ctx->scratch_buf_size = s5p_mfc_get_enc_scratch_size(); + enc->header_size = mfc_get_enc_strm_size(); + ctx->dpb_count = mfc_get_enc_dpb_count(); + ctx->scratch_buf_size = mfc_get_enc_scratch_size(); mfc_debug(2, "[OTF][STREAM] encoded slice type: %d, header size: %d, display order: %d\n", - s5p_mfc_get_enc_slice_type(), enc->header_size, - s5p_mfc_get_enc_pic_count()); + mfc_get_enc_slice_type(), enc->header_size, + mfc_get_enc_pic_count()); mfc_debug(2, "[OTF] cpb_count: %d, scratch size: %zu\n", ctx->dpb_count, ctx->scratch_buf_size); - s5p_mfc_change_state(ctx, MFCINST_HEAD_PARSED); + mfc_change_state(ctx, MFCINST_HEAD_PARSED); - if (s5p_mfc_alloc_codec_buffers(ctx)) { + if (mfc_alloc_codec_buffers(ctx)) { mfc_err_ctx("[OTF] Failed to allocate encoding buffers\n"); return -EINVAL; } @@ -491,15 +491,15 @@ int s5p_mfc_otf_handle_seq(struct s5p_mfc_ctx *ctx) return 0; } -int s5p_mfc_otf_handle_stream(struct s5p_mfc_ctx *ctx) +int mfc_otf_handle_stream(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_enc *enc = ctx->enc_priv; + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; struct _otf_handle *handle = ctx->otf_handle; struct _otf_debug *debug = &handle->otf_debug; - struct s5p_mfc_special_buf *buf; + struct mfc_special_buf *buf; struct _otf_buf_addr *buf_addr = &handle->otf_buf_addr; - struct s5p_mfc_raw_info *raw; + struct mfc_raw_info *raw; dma_addr_t enc_addr[3] = { 0, 0, 0 }; int slice_type, i; unsigned int strm_size; @@ -513,9 +513,9 @@ int s5p_mfc_otf_handle_stream(struct s5p_mfc_ctx *ctx) mfc_encoding_end(); #endif - slice_type = s5p_mfc_get_enc_slice_type(); - pic_count = s5p_mfc_get_enc_pic_count(); - strm_size = s5p_mfc_get_enc_strm_size(); + slice_type = mfc_get_enc_slice_type(); + pic_count = mfc_get_enc_pic_count(); + strm_size = mfc_get_enc_strm_size(); mfc_debug(2, "[OTF][STREAM] encoded slice type: %d, size: %d, display order: %d\n", slice_type, strm_size, pic_count); @@ -525,7 +525,7 @@ int s5p_mfc_otf_handle_stream(struct s5p_mfc_ctx *ctx) raw = &ctx->raw_buf; if (strm_size > 0) { - s5p_mfc_get_enc_frame_buffer(ctx, &enc_addr[0], raw->num_planes); + mfc_get_enc_frame_buffer(ctx, &enc_addr[0], raw->num_planes); for (i = 0; i < raw->num_planes; i++) mfc_debug(2, "[OTF][BUFINFO] ctx[%d] get src addr[%d]: 0x%08llx\n", @@ -575,18 +575,18 @@ int s5p_mfc_otf_handle_stream(struct s5p_mfc_ctx *ctx) return 0; } -void s5p_mfc_otf_handle_error(struct s5p_mfc_ctx *ctx, +void mfc_otf_handle_error(struct mfc_ctx *ctx, unsigned int reason, unsigned int err) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; struct _otf_handle *handle = ctx->otf_handle; int enc_ret = -HWFC_ERR_MFC; mfc_debug_enter(); mfc_err_ctx("[OTF] Interrupt Error: display: %d, decoded: %d\n", - s5p_mfc_get_warn(err), s5p_mfc_get_err(err)); - err = s5p_mfc_get_err(err); + mfc_get_warn(err), mfc_get_err(err)); + err = mfc_get_err(err); /* Error recovery is dependent on the state of context */ switch (ctx->state) { @@ -597,12 +597,12 @@ void s5p_mfc_otf_handle_error(struct s5p_mfc_ctx *ctx, mfc_err_ctx("[OTF] error happened during init/de-init\n"); break; case MFCINST_RUNNING: - if (err == S5P_FIMV_ERR_MFC_TIMEOUT) { + if (err == MFC_REG_ERR_MFC_TIMEOUT) { mfc_err_ctx("[OTF] MFC TIMEOUT. go to error state\n"); - s5p_mfc_change_state(ctx, MFCINST_ERROR); + mfc_change_state(ctx, MFCINST_ERROR); enc_ret = -HWFC_ERR_MFC_TIMEOUT; - } else if (err == S5P_FIMV_ERR_TS_MUX_TIMEOUT || - err == S5P_FIMV_ERR_G2D_TIMEOUT) { + } else if (err == MFC_REG_ERR_TS_MUX_TIMEOUT || + err == MFC_REG_ERR_G2D_TIMEOUT) { mfc_err_ctx("[OTF] TS-MUX or G2D TIMEOUT. skip this frame\n"); enc_ret = -HWFC_ERR_MFC_TIMEOUT; } else { @@ -632,12 +632,12 @@ void s5p_mfc_otf_handle_error(struct s5p_mfc_ctx *ctx, break; } - s5p_mfc_wake_up_dev(dev, reason, err); + mfc_wake_up_dev(dev, reason, err); mfc_debug_leave(); } -int mfc_hwfc_check_run(struct s5p_mfc_ctx *ctx) +int __mfc_hwfc_check_run(struct mfc_ctx *ctx) { struct _otf_handle *handle = ctx->otf_handle; @@ -663,9 +663,9 @@ int mfc_hwfc_check_run(struct s5p_mfc_ctx *ctx) int s5p_mfc_hwfc_encode(int buf_index, int job_id, struct encoding_param *param) { - struct s5p_mfc_dev *dev = g_mfc_dev; + struct mfc_dev *dev = g_mfc_dev; struct _otf_handle *handle; - struct s5p_mfc_ctx *ctx = NULL; + struct mfc_ctx *ctx = NULL; #ifdef CONFIG_VIDEO_EXYNOS_TSMUX struct packetizing_param packet_param; #endif @@ -689,7 +689,7 @@ int s5p_mfc_hwfc_encode(int buf_index, int job_id, struct encoding_param *param) return -HWFC_ERR_MFC_NOT_PREPARED; } - if (mfc_hwfc_check_run(ctx)) { + if (__mfc_hwfc_check_run(ctx)) { mfc_err_dev("[OTF] mfc is not prepared\n"); return -HWFC_ERR_MFC_NOT_PREPARED; } @@ -710,9 +710,9 @@ int s5p_mfc_hwfc_encode(int buf_index, int job_id, struct encoding_param *param) handle->otf_job_id = job_id; handle->otf_time_stamp = param->time_stamp; - if (s5p_mfc_otf_ctx_ready(ctx)) - s5p_mfc_set_bit(ctx->num, &dev->work_bits); - if (s5p_mfc_is_work_to_do(dev)) + if (mfc_otf_ctx_ready(ctx)) + mfc_set_bit(ctx->num, &dev->work_bits); + if (mfc_is_work_to_do(dev)) queue_work(dev->butler_wq, &dev->butler_work); mfc_debug_leave(); diff --git a/drivers/media/platform/exynos/mfc/mfc_otf.h b/drivers/media/platform/exynos/mfc/mfc_otf.h index d96e40353e9f..854cd6115a70 100644 --- a/drivers/media/platform/exynos/mfc/mfc_otf.h +++ b/drivers/media/platform/exynos/mfc/mfc_otf.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_otf.h + * drivers/media/platform/exynos/mfc/mfc_otf.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -15,17 +15,17 @@ #include "mfc_common.h" -extern struct s5p_mfc_dev *g_mfc_dev; +extern struct mfc_dev *g_mfc_dev; -int s5p_mfc_otf_create(struct s5p_mfc_ctx *ctx); -void s5p_mfc_otf_destroy(struct s5p_mfc_ctx *ctx); -int s5p_mfc_otf_init(struct s5p_mfc_ctx *ctx); -void s5p_mfc_otf_deinit(struct s5p_mfc_ctx *ctx); -int s5p_mfc_otf_ctx_ready(struct s5p_mfc_ctx *ctx); -int s5p_mfc_otf_run_enc_init(struct s5p_mfc_ctx *ctx); -int s5p_mfc_otf_run_enc_frame(struct s5p_mfc_ctx *ctx); -int s5p_mfc_otf_handle_seq(struct s5p_mfc_ctx *ctx); -int s5p_mfc_otf_handle_stream(struct s5p_mfc_ctx *ctx); -void s5p_mfc_otf_handle_error(struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err); +int mfc_otf_create(struct mfc_ctx *ctx); +void mfc_otf_destroy(struct mfc_ctx *ctx); +int mfc_otf_init(struct mfc_ctx *ctx); +void mfc_otf_deinit(struct mfc_ctx *ctx); +int mfc_otf_ctx_ready(struct mfc_ctx *ctx); +int mfc_otf_run_enc_init(struct mfc_ctx *ctx); +int mfc_otf_run_enc_frame(struct mfc_ctx *ctx); +int mfc_otf_handle_seq(struct mfc_ctx *ctx); +int mfc_otf_handle_stream(struct mfc_ctx *ctx); +void mfc_otf_handle_error(struct mfc_ctx *ctx, unsigned int reason, unsigned int err); #endif /* __MFC_OTF_H */ diff --git a/drivers/media/platform/exynos/mfc/mfc_perf_measure.c b/drivers/media/platform/exynos/mfc/mfc_perf_measure.c index a6d335eef593..b4db44195acd 100644 --- a/drivers/media/platform/exynos/mfc/mfc_perf_measure.c +++ b/drivers/media/platform/exynos/mfc/mfc_perf_measure.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_perf_measure.c + * drivers/media/platform/exynos/mfc/mfc_perf_measure.c * * Copyright (c) 2017 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -14,12 +14,12 @@ #ifndef PERF_MEASURE -void s5p_mfc_perf_register(struct s5p_mfc_dev *dev) {} -void mfc_measure_init(void) {} -void mfc_measure_on(struct s5p_mfc_dev *dev) {} -void mfc_measure_off(struct s5p_mfc_dev *dev) {} -void mfc_measure_store(struct s5p_mfc_dev *dev, int diff) {} -void s5p_mfc_perf_print(void) {} +void mfc_perf_register(struct mfc_dev *dev) {} +void __mfc_measure_init(void) {} +void __mfc_measure_on(struct mfc_dev *dev) {} +void __mfc_measure_off(struct mfc_dev *dev) {} +void __mfc_measure_store(struct mfc_dev *dev, int diff) {} +void mfc_perf_print(void) {} #else diff --git a/drivers/media/platform/exynos/mfc/mfc_perf_measure.h b/drivers/media/platform/exynos/mfc/mfc_perf_measure.h index ab7fe571d35c..9b74b773ce3e 100644 --- a/drivers/media/platform/exynos/mfc/mfc_perf_measure.h +++ b/drivers/media/platform/exynos/mfc/mfc_perf_measure.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_perf_measure.h + * drivers/media/platform/exynos/mfc/mfc_perf_measure.h * * Copyright (c) 2017 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -17,27 +17,27 @@ #include "mfc_reg.h" -void s5p_mfc_perf_register(struct s5p_mfc_dev *dev); -void mfc_measure_init(void); -void mfc_measure_on(struct s5p_mfc_dev *dev); -void mfc_measure_off(struct s5p_mfc_dev *dev); -void mfc_measure_store(struct s5p_mfc_dev *dev, int diff); -void s5p_mfc_perf_print(void); +void mfc_perf_register(struct mfc_dev *dev); +void __mfc_measure_init(void); +void __mfc_measure_on(struct mfc_dev *dev); +void __mfc_measure_off(struct mfc_dev *dev); +void __mfc_measure_store(struct mfc_dev *dev, int diff); +void mfc_perf_print(void); //#define PERF_MEASURE #ifndef PERF_MEASURE -static inline void s5p_mfc_perf_init(struct s5p_mfc_dev *dev) {} -static inline void s5p_mfc_perf_cancel_drv_margin(struct s5p_mfc_dev *dev) {} -static inline void s5p_mfc_perf_measure_on(struct s5p_mfc_dev *dev) {} -static inline void s5p_mfc_perf_measure_off(struct s5p_mfc_dev *dev) {} +static inline void mfc_perf_init(struct mfc_dev *dev) {} +static inline void mfc_perf_cancel_drv_margin(struct mfc_dev *dev) {} +static inline void mfc_perf_measure_on(struct mfc_dev *dev) {} +static inline void mfc_perf_measure_off(struct mfc_dev *dev) {} #else extern unsigned int perf_measure_option; -static inline void s5p_mfc_perf_init(struct s5p_mfc_dev *dev) +static inline void mfc_perf_init(struct mfc_dev *dev) { dev->perf.new_start = 0; dev->perf.count = 0; @@ -48,12 +48,12 @@ static inline void s5p_mfc_perf_init(struct s5p_mfc_dev *dev) mfc_info_dev("MFC frequency : %ld\n", clk_get_rate(dev->pm.clock)); } -static inline void s5p_mfc_perf_cancel_drv_margin(struct s5p_mfc_dev *dev) +static inline void mfc_perf_cancel_drv_margin(struct mfc_dev *dev) { dev->perf.drv_margin = 0; } -static inline void s5p_mfc_perf_measure_on(struct s5p_mfc_dev *dev) +static inline void mfc_perf_measure_on(struct mfc_dev *dev) { int diff; @@ -76,7 +76,7 @@ static inline void s5p_mfc_perf_measure_on(struct s5p_mfc_dev *dev) dev->perf.count++; } -static inline void s5p_mfc_perf_measure_off(struct s5p_mfc_dev *dev) +static inline void mfc_perf_measure_off(struct mfc_dev *dev) { unsigned int diff; @@ -91,7 +91,7 @@ static inline void s5p_mfc_perf_measure_off(struct s5p_mfc_dev *dev) mfc_measure_store(dev, diff); mfc_debug(3, "uDECtype :%d, uENCtype :%d, codectype :%d\n", - s5p_mfc_get_dec_frame_type(), s5p_mfc_get_enc_slice_type(), MFC_READL(S5P_FIMV_CODEC_TYPE)); + mfc_get_dec_frame_type(), mfc_get_enc_slice_type(), MFC_READL(MFC_REG_CODEC_TYPE)); dev->perf.drv_margin = 1; diff --git a/drivers/media/platform/exynos/mfc/mfc_pm.c b/drivers/media/platform/exynos/mfc/mfc_pm.c index b4db0562a3ad..0f7bfd26b312 100644 --- a/drivers/media/platform/exynos/mfc/mfc_pm.c +++ b/drivers/media/platform/exynos/mfc/mfc_pm.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_pm.c + * drivers/media/platform/exynos/mfc/mfc_pm.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -19,7 +19,7 @@ #include "mfc_cal.h" #include "mfc_reg.h" -void s5p_mfc_pm_init(struct s5p_mfc_dev *dev) +void mfc_pm_init(struct mfc_dev *dev) { spin_lock_init(&dev->pm.clklock); atomic_set(&dev->pm.pwr_ref, 0); @@ -31,12 +31,12 @@ void s5p_mfc_pm_init(struct s5p_mfc_dev *dev) pm_runtime_enable(dev->pm.device); } -void s5p_mfc_pm_final(struct s5p_mfc_dev *dev) +void mfc_pm_final(struct mfc_dev *dev) { pm_runtime_disable(dev->pm.device); } -int s5p_mfc_pm_clock_on(struct s5p_mfc_dev *dev) +int mfc_pm_clock_on(struct mfc_dev *dev) { int ret = 0; int state; @@ -54,7 +54,7 @@ int s5p_mfc_pm_clock_on(struct s5p_mfc_dev *dev) dev->pm.clock_on_steps |= 0x1 << 1; if (dev->pm.base_type != MFCBUF_INVALID) - s5p_mfc_set_risc_base_addr(dev, dev->pm.base_type); + mfc_set_risc_base_addr(dev, dev->pm.base_type); dev->pm.clock_on_steps |= 0x1 << 2; #ifdef CONFIG_EXYNOS_CONTENT_PATH_PROTECTION @@ -89,18 +89,18 @@ int s5p_mfc_pm_clock_on(struct s5p_mfc_dev *dev) } /* Use only in functions that first instance is guaranteed, like mfc_init_hw() */ -int s5p_mfc_pm_clock_on_with_base(struct s5p_mfc_dev *dev, +int mfc_pm_clock_on_with_base(struct mfc_dev *dev, enum mfc_buf_usage_type buf_type) { int ret; dev->pm.base_type = buf_type; - ret = s5p_mfc_pm_clock_on(dev); + ret = mfc_pm_clock_on(dev); dev->pm.base_type = MFCBUF_INVALID; return ret; } -void s5p_mfc_pm_clock_off(struct s5p_mfc_dev *dev) +void mfc_pm_clock_off(struct mfc_dev *dev) { int state; @@ -147,7 +147,7 @@ void s5p_mfc_pm_clock_off(struct s5p_mfc_dev *dev) MFC_TRACE_DEV("** clock_off end: ref state(%d)\n", state); } -int s5p_mfc_pm_power_on(struct s5p_mfc_dev *dev) +int mfc_pm_power_on(struct mfc_dev *dev) { int ret; @@ -188,7 +188,7 @@ err_power_on: return ret; } -int s5p_mfc_pm_power_off(struct s5p_mfc_dev *dev) +int mfc_pm_power_off(struct mfc_dev *dev) { int ret; diff --git a/drivers/media/platform/exynos/mfc/mfc_pm.h b/drivers/media/platform/exynos/mfc/mfc_pm.h index 8e3aa6707bd3..7f5f3e818c0c 100644 --- a/drivers/media/platform/exynos/mfc/mfc_pm.h +++ b/drivers/media/platform/exynos/mfc/mfc_pm.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_pm.h + * drivers/media/platform/exynos/mfc/mfc_pm.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -15,24 +15,24 @@ #include "mfc_common.h" -static inline int s5p_mfc_pm_get_pwr_ref_cnt(struct s5p_mfc_dev *dev) +static inline int mfc_pm_get_pwr_ref_cnt(struct mfc_dev *dev) { return atomic_read(&dev->pm.pwr_ref); } -static inline int s5p_mfc_pm_get_clk_ref_cnt(struct s5p_mfc_dev *dev) +static inline int mfc_pm_get_clk_ref_cnt(struct mfc_dev *dev) { return atomic_read(&dev->clk_ref); } -void s5p_mfc_pm_init(struct s5p_mfc_dev *dev); -void s5p_mfc_pm_final(struct s5p_mfc_dev *dev); +void mfc_pm_init(struct mfc_dev *dev); +void mfc_pm_final(struct mfc_dev *dev); -int s5p_mfc_pm_clock_on(struct s5p_mfc_dev *dev); -int s5p_mfc_pm_clock_on_with_base(struct s5p_mfc_dev *dev, +int mfc_pm_clock_on(struct mfc_dev *dev); +int mfc_pm_clock_on_with_base(struct mfc_dev *dev, enum mfc_buf_usage_type buf_type); -void s5p_mfc_pm_clock_off(struct s5p_mfc_dev *dev); -int s5p_mfc_pm_power_on(struct s5p_mfc_dev *dev); -int s5p_mfc_pm_power_off(struct s5p_mfc_dev *dev); +void mfc_pm_clock_off(struct mfc_dev *dev); +int mfc_pm_power_on(struct mfc_dev *dev); +int mfc_pm_power_off(struct mfc_dev *dev); #endif /* __MFC_PM_H */ diff --git a/drivers/media/platform/exynos/mfc/mfc_qos.c b/drivers/media/platform/exynos/mfc/mfc_qos.c index de6dd191b278..738cf783305e 100644 --- a/drivers/media/platform/exynos/mfc/mfc_qos.c +++ b/drivers/media/platform/exynos/mfc/mfc_qos.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_qos.c + * drivers/media/platform/exynos/mfc/mfc_qos.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -31,10 +31,10 @@ enum { MFC_PERF_BOOST_CPU = (1 << 2), }; -void s5p_mfc_perf_boost_enable(struct s5p_mfc_dev *dev) +void mfc_perf_boost_enable(struct mfc_dev *dev) { - struct s5p_mfc_platdata *pdata = dev->pdata; - struct s5p_mfc_qos_boost *qos_boost_table = pdata->qos_boost_table; + struct mfc_platdata *pdata = dev->pdata; + struct mfc_qos_boost *qos_boost_table = pdata->qos_boost_table; int i; if (perf_boost_mode & MFC_PERF_BOOST_DVFS) { @@ -69,9 +69,9 @@ void s5p_mfc_perf_boost_enable(struct s5p_mfc_dev *dev) } } -void s5p_mfc_perf_boost_disable(struct s5p_mfc_dev *dev) +void mfc_perf_boost_disable(struct mfc_dev *dev) { - struct s5p_mfc_platdata *pdata = dev->pdata; + struct mfc_platdata *pdata = dev->pdata; int i; if (perf_boost_mode & MFC_PERF_BOOST_DVFS) { @@ -99,11 +99,11 @@ void s5p_mfc_perf_boost_disable(struct s5p_mfc_dev *dev) } } -static void mfc_qos_operate(struct s5p_mfc_ctx *ctx, int opr_type, int idx) +static void __mfc_qos_operate(struct mfc_ctx *ctx, int opr_type, int idx) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_platdata *pdata = dev->pdata; - struct s5p_mfc_qos *qos_table = pdata->qos_table; + struct mfc_dev *dev = ctx->dev; + struct mfc_platdata *pdata = dev->pdata; + struct mfc_qos *qos_table = pdata->qos_table; switch (opr_type) { case MFC_QOS_ADD: @@ -214,14 +214,14 @@ static void mfc_qos_operate(struct s5p_mfc_ctx *ctx, int opr_type, int idx) } #ifdef CONFIG_EXYNOS_BTS -static void mfc_qos_set(struct s5p_mfc_ctx *ctx, struct bts_bw *mfc_bw, int i) +static void __mfc_qos_set(struct mfc_ctx *ctx, struct bts_bw *mfc_bw, int i) #else -static void mfc_qos_set(struct s5p_mfc_ctx *ctx, int i) +static void __mfc_qos_set(struct mfc_ctx *ctx, int i) #endif { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_platdata *pdata = dev->pdata; - struct s5p_mfc_qos *qos_table = pdata->qos_table; + struct mfc_dev *dev = ctx->dev; + struct mfc_platdata *pdata = dev->pdata; + struct mfc_qos *qos_table = pdata->qos_table; mfc_debug(2, "[QoS] table[%d] covered mb %d ~ %d (mfc: %d, int:%d, mif:%d)\n", i, qos_table[i].threshold_mb, @@ -235,43 +235,43 @@ static void mfc_qos_set(struct s5p_mfc_ctx *ctx, int i) dev->mfc_bw.peak = mfc_bw->peak; dev->mfc_bw.read = mfc_bw->read; dev->mfc_bw.write = mfc_bw->write; - mfc_qos_operate(ctx, MFC_QOS_BW, i); + __mfc_qos_operate(ctx, MFC_QOS_BW, i); } #endif if (atomic_read(&dev->qos_req_cur) == 0) - mfc_qos_operate(ctx, MFC_QOS_ADD, i); + __mfc_qos_operate(ctx, MFC_QOS_ADD, i); else if (atomic_read(&dev->qos_req_cur) != (i + 1)) - mfc_qos_operate(ctx, MFC_QOS_UPDATE, i); + __mfc_qos_operate(ctx, MFC_QOS_UPDATE, i); } -static inline unsigned long mfc_qos_get_weighted_mb(struct s5p_mfc_ctx *ctx, +static inline unsigned long __mfc_qos_get_weighted_mb(struct mfc_ctx *ctx, unsigned long mb) { - struct s5p_mfc_enc *enc = ctx->enc_priv; - struct s5p_mfc_dec *dec = ctx->dec_priv; - struct s5p_mfc_enc_params *p; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_enc_params *p; u32 num_planes = ctx->dst_fmt->num_planes; int weight = 1000; unsigned long weighted_mb; switch (ctx->codec_mode) { - case S5P_FIMV_CODEC_H264_DEC: - case S5P_FIMV_CODEC_H264_MVC_DEC: - case S5P_FIMV_CODEC_H264_ENC: - case S5P_FIMV_CODEC_H264_MVC_ENC: - case S5P_FIMV_CODEC_VP8_DEC: - case S5P_FIMV_CODEC_VP8_ENC: + case MFC_REG_CODEC_H264_DEC: + case MFC_REG_CODEC_H264_MVC_DEC: + case MFC_REG_CODEC_H264_ENC: + case MFC_REG_CODEC_H264_MVC_ENC: + case MFC_REG_CODEC_VP8_DEC: + case MFC_REG_CODEC_VP8_ENC: if (num_planes == 3) weight = (weight * 100) / MFC_QOS_WEIGHT_3PLANE; break; - case S5P_FIMV_CODEC_HEVC_DEC: - case S5P_FIMV_CODEC_HEVC_ENC: - case S5P_FIMV_CODEC_VP9_DEC: - case S5P_FIMV_CODEC_VP9_ENC: - case S5P_FIMV_CODEC_BPG_DEC: - case S5P_FIMV_CODEC_BPG_ENC: + case MFC_REG_CODEC_HEVC_DEC: + case MFC_REG_CODEC_HEVC_ENC: + case MFC_REG_CODEC_VP9_DEC: + case MFC_REG_CODEC_VP9_ENC: + case MFC_REG_CODEC_BPG_DEC: + case MFC_REG_CODEC_BPG_ENC: if (num_planes == 3) { weight = (weight * 100) / MFC_QOS_WEIGHT_3PLANE; } else { @@ -282,17 +282,17 @@ static inline unsigned long mfc_qos_get_weighted_mb(struct s5p_mfc_ctx *ctx, } break; - case S5P_FIMV_CODEC_MPEG4_DEC: - case S5P_FIMV_CODEC_FIMV1_DEC: - case S5P_FIMV_CODEC_FIMV2_DEC: - case S5P_FIMV_CODEC_FIMV3_DEC: - case S5P_FIMV_CODEC_FIMV4_DEC: - case S5P_FIMV_CODEC_H263_DEC: - case S5P_FIMV_CODEC_VC1_RCV_DEC: - case S5P_FIMV_CODEC_VC1_DEC: - case S5P_FIMV_CODEC_MPEG2_DEC: - case S5P_FIMV_CODEC_MPEG4_ENC: - case S5P_FIMV_CODEC_H263_ENC: + case MFC_REG_CODEC_MPEG4_DEC: + case MFC_REG_CODEC_FIMV1_DEC: + case MFC_REG_CODEC_FIMV2_DEC: + case MFC_REG_CODEC_FIMV3_DEC: + case MFC_REG_CODEC_FIMV4_DEC: + case MFC_REG_CODEC_H263_DEC: + case MFC_REG_CODEC_VC1_RCV_DEC: + case MFC_REG_CODEC_VC1_DEC: + case MFC_REG_CODEC_MPEG2_DEC: + case MFC_REG_CODEC_MPEG4_ENC: + case MFC_REG_CODEC_H263_ENC: weight = (weight * 100) / MFC_QOS_WEIGHT_OTHER_CODEC; break; @@ -330,7 +330,7 @@ static inline unsigned long mfc_qos_get_weighted_mb(struct s5p_mfc_ctx *ctx, return weighted_mb; } -static inline unsigned long mfc_qos_get_mb_per_second(struct s5p_mfc_ctx *ctx) +static inline unsigned long __mfc_qos_get_mb_per_second(struct mfc_ctx *ctx) { unsigned long mb_width, mb_height, fps, mb; @@ -343,11 +343,11 @@ static inline unsigned long mfc_qos_get_mb_per_second(struct s5p_mfc_ctx *ctx) ctx->num, ctx->type == MFCINST_ENCODER ? "ENC" : "DEC", ctx->crop_width, ctx->crop_height, fps, mb); - return mfc_qos_get_weighted_mb(ctx, mb); + return __mfc_qos_get_weighted_mb(ctx, mb); } #ifdef CONFIG_EXYNOS_BTS -static struct s5p_mfc_qos_bw mfc_bw_info = { +static struct mfc_qos_bw mfc_bw_info = { /* peak read write (KB/UHD frame) */ .h264_dec_uhd_bw = { 38131, 40206, 24870 }, .hevc_dec_uhd_bw = { 35055, 33741, 20511 }, @@ -363,7 +363,7 @@ static struct s5p_mfc_qos_bw mfc_bw_info = { .mpeg4_enc_uhd_bw = { 44633, 55310, 9599 }, }; -static void mfc_qos_get_bw_per_second(struct s5p_mfc_ctx *ctx, struct bts_bw *mfc_bw) +static void __mfc_qos_get_bw_per_second(struct mfc_ctx *ctx, struct bts_bw *mfc_bw) { struct mfc_qos_bw_data bw_data; unsigned long mb_width, mb_height, fps, mb; @@ -380,53 +380,53 @@ static void mfc_qos_get_bw_per_second(struct s5p_mfc_ctx *ctx, struct bts_bw *mf mb = mb_width * mb_height * fps; switch (ctx->codec_mode) { - case S5P_FIMV_CODEC_H264_DEC: - case S5P_FIMV_CODEC_H264_MVC_DEC: + case MFC_REG_CODEC_H264_DEC: + case MFC_REG_CODEC_H264_MVC_DEC: bw_data = mfc_bw_info.h264_dec_uhd_bw; break; - case S5P_FIMV_CODEC_H264_ENC: - case S5P_FIMV_CODEC_H264_MVC_ENC: + case MFC_REG_CODEC_H264_ENC: + case MFC_REG_CODEC_H264_MVC_ENC: bw_data = mfc_bw_info.h264_enc_uhd_bw; break; - case S5P_FIMV_CODEC_HEVC_DEC: - case S5P_FIMV_CODEC_BPG_DEC: + case MFC_REG_CODEC_HEVC_DEC: + case MFC_REG_CODEC_BPG_DEC: if (ctx->is_10bit) bw_data = mfc_bw_info.hevc_dec_uhd_10bit_bw; else bw_data = mfc_bw_info.hevc_dec_uhd_bw; break; - case S5P_FIMV_CODEC_HEVC_ENC: - case S5P_FIMV_CODEC_BPG_ENC: + case MFC_REG_CODEC_HEVC_ENC: + case MFC_REG_CODEC_BPG_ENC: if (ctx->is_10bit) bw_data = mfc_bw_info.hevc_enc_uhd_10bit_bw; else bw_data = mfc_bw_info.hevc_enc_uhd_bw; break; - case S5P_FIMV_CODEC_MPEG4_DEC: - case S5P_FIMV_CODEC_FIMV1_DEC: - case S5P_FIMV_CODEC_FIMV2_DEC: - case S5P_FIMV_CODEC_FIMV3_DEC: - case S5P_FIMV_CODEC_FIMV4_DEC: - case S5P_FIMV_CODEC_H263_DEC: - case S5P_FIMV_CODEC_VC1_RCV_DEC: - case S5P_FIMV_CODEC_VC1_DEC: - case S5P_FIMV_CODEC_MPEG2_DEC: + case MFC_REG_CODEC_MPEG4_DEC: + case MFC_REG_CODEC_FIMV1_DEC: + case MFC_REG_CODEC_FIMV2_DEC: + case MFC_REG_CODEC_FIMV3_DEC: + case MFC_REG_CODEC_FIMV4_DEC: + case MFC_REG_CODEC_H263_DEC: + case MFC_REG_CODEC_VC1_RCV_DEC: + case MFC_REG_CODEC_VC1_DEC: + case MFC_REG_CODEC_MPEG2_DEC: bw_data = mfc_bw_info.mpeg4_dec_uhd_bw; break; - case S5P_FIMV_CODEC_VP8_DEC: + case MFC_REG_CODEC_VP8_DEC: bw_data = mfc_bw_info.vp8_dec_uhd_bw; break; - case S5P_FIMV_CODEC_VP9_DEC: + case MFC_REG_CODEC_VP9_DEC: bw_data = mfc_bw_info.vp9_dec_uhd_bw; break; - case S5P_FIMV_CODEC_MPEG4_ENC: - case S5P_FIMV_CODEC_H263_ENC: + case MFC_REG_CODEC_MPEG4_ENC: + case MFC_REG_CODEC_H263_ENC: bw_data = mfc_bw_info.mpeg4_enc_uhd_bw; break; - case S5P_FIMV_CODEC_VP8_ENC: + case MFC_REG_CODEC_VP8_ENC: bw_data = mfc_bw_info.vp8_enc_uhd_bw; break; - case S5P_FIMV_CODEC_VP9_ENC: + case MFC_REG_CODEC_VP9_ENC: bw_data = mfc_bw_info.vp9_enc_uhd_bw; break; default: @@ -464,12 +464,12 @@ static void mfc_qos_get_bw_per_second(struct s5p_mfc_ctx *ctx, struct bts_bw *mf } #endif -void s5p_mfc_qos_on(struct s5p_mfc_ctx *ctx) +void mfc_qos_on(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_platdata *pdata = dev->pdata; - struct s5p_mfc_qos *qos_table = pdata->qos_table; - struct s5p_mfc_ctx *qos_ctx; + struct mfc_dev *dev = ctx->dev; + struct mfc_platdata *pdata = dev->pdata; + struct mfc_qos *qos_table = pdata->qos_table; + struct mfc_ctx *qos_ctx; unsigned long hw_mb = 0, total_mb = 0, total_fps = 0; unsigned int fw_time, sw_time; int i, found = 0, enc_found = 0; @@ -499,10 +499,10 @@ void s5p_mfc_qos_on(struct s5p_mfc_ctx *ctx) list_for_each_entry(qos_ctx, &dev->qos_queue, qos_list) { if (OVER_UHD_ENC60(qos_ctx)) enc_found = 1; - hw_mb += mfc_qos_get_mb_per_second(qos_ctx); + hw_mb += __mfc_qos_get_mb_per_second(qos_ctx); total_fps += (qos_ctx->framerate / 1000); #ifdef CONFIG_EXYNOS_BTS - mfc_qos_get_bw_per_second(qos_ctx, &mfc_bw_ctx); + __mfc_qos_get_bw_per_second(qos_ctx, &mfc_bw_ctx); mfc_bw.peak += mfc_bw_ctx.peak; mfc_bw.read += mfc_bw_ctx.read; mfc_bw.write += mfc_bw_ctx.write; @@ -535,18 +535,18 @@ void s5p_mfc_qos_on(struct s5p_mfc_ctx *ctx) mfc_debug(4, "[QoS] overspec mb %ld > %d\n", total_mb, pdata->max_mb); #ifdef CONFIG_EXYNOS_BTS - mfc_qos_set(ctx, &mfc_bw, i); + __mfc_qos_set(ctx, &mfc_bw, i); #else - mfc_qos_set(ctx, i); + __mfc_qos_set(ctx, i); #endif } -void s5p_mfc_qos_off(struct s5p_mfc_ctx *ctx) +void mfc_qos_off(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_platdata *pdata = dev->pdata; - struct s5p_mfc_qos *qos_table = pdata->qos_table; - struct s5p_mfc_ctx *qos_ctx; + struct mfc_dev *dev = ctx->dev; + struct mfc_platdata *pdata = dev->pdata; + struct mfc_qos *qos_table = pdata->qos_table; + struct mfc_ctx *qos_ctx; unsigned long hw_mb = 0, total_mb = 0, total_fps = 0; unsigned int fw_time, sw_time; int i, found = 0, enc_found = 0; @@ -563,7 +563,7 @@ void s5p_mfc_qos_off(struct s5p_mfc_ctx *ctx) if (list_empty(&dev->qos_queue)) { if (atomic_read(&dev->qos_req_cur) != 0) { mfc_err_ctx("[QoS] MFC request count is wrong!\n"); - mfc_qos_operate(ctx, MFC_QOS_REMOVE, 0); + __mfc_qos_operate(ctx, MFC_QOS_REMOVE, 0); } return; } @@ -582,10 +582,10 @@ void s5p_mfc_qos_off(struct s5p_mfc_ctx *ctx) if (OVER_UHD_ENC60(qos_ctx)) enc_found = 1; - hw_mb += mfc_qos_get_mb_per_second(qos_ctx); + hw_mb += __mfc_qos_get_mb_per_second(qos_ctx); total_fps += (qos_ctx->framerate / 1000); #ifdef CONFIG_EXYNOS_BTS - mfc_qos_get_bw_per_second(qos_ctx, &mfc_bw_ctx); + __mfc_qos_get_bw_per_second(qos_ctx, &mfc_bw_ctx); mfc_bw.peak += mfc_bw_ctx.peak; mfc_bw.read += mfc_bw_ctx.read; mfc_bw.write += mfc_bw_ctx.write; @@ -621,12 +621,12 @@ void s5p_mfc_qos_off(struct s5p_mfc_ctx *ctx) list_del(&ctx->qos_list); if (list_empty(&dev->qos_queue) || total_mb == 0) - mfc_qos_operate(ctx, MFC_QOS_REMOVE, 0); + __mfc_qos_operate(ctx, MFC_QOS_REMOVE, 0); else #ifdef CONFIG_EXYNOS_BTS - mfc_qos_set(ctx, &mfc_bw, i); + __mfc_qos_set(ctx, &mfc_bw, i); #else - mfc_qos_set(ctx, i); + __mfc_qos_set(ctx, i); #endif } #endif @@ -655,14 +655,14 @@ static unsigned long framerate_table[][2] = { { 480000, 0 }, }; -static inline unsigned long mfc_qos_timeval_diff(struct timeval *to, +static inline unsigned long __mfc_qos_timeval_diff(struct timeval *to, struct timeval *from) { return (to->tv_sec * USEC_PER_SEC + to->tv_usec) - (from->tv_sec * USEC_PER_SEC + from->tv_usec); } -static unsigned long mfc_qos_get_framerate_by_interval(int interval) +static unsigned long __mfc_qos_get_framerate_by_interval(int interval) { unsigned long i; @@ -679,7 +679,7 @@ static unsigned long mfc_qos_get_framerate_by_interval(int interval) } /* Return the minimum interval between previous and next entry */ -static int mfc_qos_get_interval(struct list_head *head, struct list_head *entry) +static int __mfc_qos_get_interval(struct list_head *head, struct list_head *entry) { int prev_interval = MFC_MAX_INTERVAL, next_interval = MFC_MAX_INTERVAL; struct mfc_timestamp *prev_ts, *next_ts, *curr_ts; @@ -688,18 +688,18 @@ static int mfc_qos_get_interval(struct list_head *head, struct list_head *entry) if (entry->prev != head) { prev_ts = list_entry(entry->prev, struct mfc_timestamp, list); - prev_interval = mfc_qos_timeval_diff(&curr_ts->timestamp, &prev_ts->timestamp); + prev_interval = __mfc_qos_timeval_diff(&curr_ts->timestamp, &prev_ts->timestamp); } if (entry->next != head) { next_ts = list_entry(entry->next, struct mfc_timestamp, list); - next_interval = mfc_qos_timeval_diff(&next_ts->timestamp, &curr_ts->timestamp); + next_interval = __mfc_qos_timeval_diff(&next_ts->timestamp, &curr_ts->timestamp); } return (prev_interval < next_interval ? prev_interval : next_interval); } -static int mfc_qos_add_timestamp(struct s5p_mfc_ctx *ctx, +static int __mfc_qos_add_timestamp(struct mfc_ctx *ctx, struct timeval *time, struct list_head *head) { int replace_entry = 0; @@ -717,7 +717,7 @@ static int mfc_qos_add_timestamp(struct s5p_mfc_ctx *ctx, if (!replace_entry) list_add(&curr_ts->list, head); curr_ts->interval = - mfc_qos_get_interval(&ctx->ts_list, &curr_ts->list); + __mfc_qos_get_interval(&ctx->ts_list, &curr_ts->list); curr_ts->index = ctx->ts_count; ctx->ts_count++; @@ -729,7 +729,7 @@ static int mfc_qos_add_timestamp(struct s5p_mfc_ctx *ctx, return 0; } -static unsigned long mfc_qos_get_fps_by_timestamp(struct s5p_mfc_ctx *ctx, struct timeval *time) +static unsigned long __mfc_qos_get_fps_by_timestamp(struct mfc_ctx *ctx, struct timeval *time) { struct mfc_timestamp *temp_ts; int found; @@ -753,8 +753,8 @@ static unsigned long mfc_qos_get_fps_by_timestamp(struct s5p_mfc_ctx *ctx, struc } if (list_empty(&ctx->ts_list)) { - mfc_qos_add_timestamp(ctx, time, &ctx->ts_list); - return mfc_qos_get_framerate_by_interval(0); + __mfc_qos_add_timestamp(ctx, time, &ctx->ts_list); + return __mfc_qos_get_framerate_by_interval(0); } else { found = 0; list_for_each_entry_reverse(temp_ts, &ctx->ts_list, list) { @@ -765,14 +765,14 @@ static unsigned long mfc_qos_get_fps_by_timestamp(struct s5p_mfc_ctx *ctx, struc break; } else if (time_diff > 0) { /* Add this after temp_ts */ - mfc_qos_add_timestamp(ctx, time, &temp_ts->list); + __mfc_qos_add_timestamp(ctx, time, &temp_ts->list); found = 1; break; } } if (!found) /* Add this at first entry */ - mfc_qos_add_timestamp(ctx, time, &ctx->ts_list); + __mfc_qos_add_timestamp(ctx, time, &ctx->ts_list); } list_for_each_entry(temp_ts, &ctx->ts_list, list) { @@ -780,7 +780,7 @@ static unsigned long mfc_qos_get_fps_by_timestamp(struct s5p_mfc_ctx *ctx, struc min_interval = temp_ts->interval; } - max_framerate = mfc_qos_get_framerate_by_interval(min_interval); + max_framerate = __mfc_qos_get_framerate_by_interval(min_interval); if (debug_ts == 1) { /* Debug info */ @@ -808,24 +808,24 @@ static unsigned long mfc_qos_get_fps_by_timestamp(struct s5p_mfc_ctx *ctx, struc return max_framerate; } -void s5p_mfc_qos_update_framerate(struct s5p_mfc_ctx *ctx) +void mfc_qos_update_framerate(struct mfc_ctx *ctx) { if (ctx->last_framerate != 0 && ctx->last_framerate != ctx->framerate) { mfc_debug(2, "[QoS] fps changed: %ld -> %ld, qos ratio: %d\n", ctx->framerate, ctx->last_framerate, ctx->qos_ratio); ctx->framerate = ctx->last_framerate; - s5p_mfc_qos_on(ctx); + mfc_qos_on(ctx); } } -void s5p_mfc_qos_update_last_framerate(struct s5p_mfc_ctx *ctx, u64 timestamp) +void mfc_qos_update_last_framerate(struct mfc_ctx *ctx, u64 timestamp) { struct timeval time; time.tv_sec = timestamp / NSEC_PER_SEC; time.tv_usec = (timestamp - (time.tv_sec * NSEC_PER_SEC)) / NSEC_PER_USEC; - ctx->last_framerate = mfc_qos_get_fps_by_timestamp(ctx, &time); + ctx->last_framerate = __mfc_qos_get_fps_by_timestamp(ctx, &time); if (ctx->last_framerate > MFC_MAX_FPS) ctx->last_framerate = MFC_MAX_FPS; ctx->last_framerate = (ctx->qos_ratio * ctx->last_framerate) / 100; diff --git a/drivers/media/platform/exynos/mfc/mfc_qos.h b/drivers/media/platform/exynos/mfc/mfc_qos.h index 783bda81b0f1..8e3ed4a83d56 100644 --- a/drivers/media/platform/exynos/mfc/mfc_qos.h +++ b/drivers/media/platform/exynos/mfc/mfc_qos.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_qos.h + * drivers/media/platform/exynos/mfc/mfc_qos.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -35,21 +35,21 @@ #define MFC_QOS_WEIGHT_NUM_OF_TILE 75 #ifdef CONFIG_MFC_USE_BUS_DEVFREQ -void s5p_mfc_perf_boost_enable(struct s5p_mfc_dev *dev); -void s5p_mfc_perf_boost_disable(struct s5p_mfc_dev *dev); -void s5p_mfc_qos_on(struct s5p_mfc_ctx *ctx); -void s5p_mfc_qos_off(struct s5p_mfc_ctx *ctx); +void mfc_perf_boost_enable(struct mfc_dev *dev); +void mfc_perf_boost_disable(struct mfc_dev *dev); +void mfc_qos_on(struct mfc_ctx *ctx); +void mfc_qos_off(struct mfc_ctx *ctx); #else -#define s5p_mfc_perf_boost_enable(dev) do {} while (0) -#define s5p_mfc_perf_boost_disable(dev) do {} while (0) -#define s5p_mfc_qos_on(ctx) do {} while (0) -#define s5p_mfc_qos_off(ctx) do {} while (0) +#define mfc_perf_boost_enable(dev) do {} while (0) +#define mfc_perf_boost_disable(dev) do {} while (0) +#define mfc_qos_on(ctx) do {} while (0) +#define mfc_qos_off(ctx) do {} while (0) #endif -void s5p_mfc_qos_update_framerate(struct s5p_mfc_ctx *ctx); -void s5p_mfc_qos_update_last_framerate(struct s5p_mfc_ctx *ctx, u64 timestamp); +void mfc_qos_update_framerate(struct mfc_ctx *ctx); +void mfc_qos_update_last_framerate(struct mfc_ctx *ctx, u64 timestamp); -static inline void s5p_mfc_qos_reset_framerate(struct s5p_mfc_ctx *ctx) +static inline void mfc_qos_reset_framerate(struct mfc_ctx *ctx) { if (ctx->type == MFCINST_DECODER) ctx->framerate = DEC_DEFAULT_FPS; @@ -57,17 +57,17 @@ static inline void s5p_mfc_qos_reset_framerate(struct s5p_mfc_ctx *ctx) ctx->framerate = ENC_DEFAULT_FPS; } -static inline void s5p_mfc_qos_reset_last_framerate(struct s5p_mfc_ctx *ctx) +static inline void mfc_qos_reset_last_framerate(struct mfc_ctx *ctx) { ctx->last_framerate = 0; } -static inline void s5p_mfc_qos_set_framerate(struct s5p_mfc_ctx *ctx, int rate) +static inline void mfc_qos_set_framerate(struct mfc_ctx *ctx, int rate) { ctx->framerate = rate; } -static inline int s5p_mfc_qos_get_framerate(struct s5p_mfc_ctx *ctx) +static inline int mfc_qos_get_framerate(struct mfc_ctx *ctx) { return ctx->framerate; } diff --git a/drivers/media/platform/exynos/mfc/mfc_queue.c b/drivers/media/platform/exynos/mfc/mfc_queue.c index 2dec6ab04f37..a6419de56d44 100644 --- a/drivers/media/platform/exynos/mfc/mfc_queue.c +++ b/drivers/media/platform/exynos/mfc/mfc_queue.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_queue.c + * drivers/media/platform/exynos/mfc/mfc_queue.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -15,8 +15,8 @@ #include "mfc_utils.h" #include "mfc_mem.h" -void s5p_mfc_add_tail_buf(spinlock_t *plock, struct s5p_mfc_buf_queue *queue, - struct s5p_mfc_buf *mfc_buf) +void mfc_add_tail_buf(spinlock_t *plock, struct mfc_buf_queue *queue, + struct mfc_buf *mfc_buf) { unsigned long flags; @@ -34,11 +34,11 @@ void s5p_mfc_add_tail_buf(spinlock_t *plock, struct s5p_mfc_buf_queue *queue, spin_unlock_irqrestore(plock, flags); } -int s5p_mfc_peek_buf_csd(spinlock_t *plock, struct s5p_mfc_buf_queue *queue) +int mfc_peek_buf_csd(spinlock_t *plock, struct mfc_buf_queue *queue) { unsigned long flags; int csd = -1; - struct s5p_mfc_buf *mfc_buf = NULL; + struct mfc_buf *mfc_buf = NULL; spin_lock_irqsave(plock, flags); @@ -48,7 +48,7 @@ int s5p_mfc_peek_buf_csd(spinlock_t *plock, struct s5p_mfc_buf_queue *queue) return csd; } - mfc_buf = list_entry(queue->head.next, struct s5p_mfc_buf, list); + mfc_buf = list_entry(queue->head.next, struct mfc_buf, list); csd = mfc_buf->vb.reserved2 & FLAG_CSD ? 1 : 0; @@ -58,11 +58,11 @@ int s5p_mfc_peek_buf_csd(spinlock_t *plock, struct s5p_mfc_buf_queue *queue) return csd; } -struct s5p_mfc_buf *s5p_mfc_get_buf(spinlock_t *plock, struct s5p_mfc_buf_queue *queue, - enum s5p_mfc_queue_used_type used) +struct mfc_buf *mfc_get_buf(spinlock_t *plock, struct mfc_buf_queue *queue, + enum mfc_queue_used_type used) { unsigned long flags; - struct s5p_mfc_buf *mfc_buf = NULL; + struct mfc_buf *mfc_buf = NULL; spin_lock_irqsave(plock, flags); @@ -72,7 +72,7 @@ struct s5p_mfc_buf *s5p_mfc_get_buf(spinlock_t *plock, struct s5p_mfc_buf_queue return NULL; } - mfc_buf = list_entry(queue->head.next, struct s5p_mfc_buf, list); + mfc_buf = list_entry(queue->head.next, struct mfc_buf, list); if ((used == MFC_BUF_RESET_USED) || (used == MFC_BUF_SET_USED)) mfc_buf->used = used; @@ -83,11 +83,11 @@ struct s5p_mfc_buf *s5p_mfc_get_buf(spinlock_t *plock, struct s5p_mfc_buf_queue return mfc_buf; } -struct s5p_mfc_buf *s5p_mfc_get_del_buf(spinlock_t *plock, struct s5p_mfc_buf_queue *queue, - enum s5p_mfc_queue_used_type used) +struct mfc_buf *mfc_get_del_buf(spinlock_t *plock, struct mfc_buf_queue *queue, + enum mfc_queue_used_type used) { unsigned long flags; - struct s5p_mfc_buf *mfc_buf = NULL; + struct mfc_buf *mfc_buf = NULL; spin_lock_irqsave(plock, flags); @@ -97,7 +97,7 @@ struct s5p_mfc_buf *s5p_mfc_get_del_buf(spinlock_t *plock, struct s5p_mfc_buf_qu return NULL; } - mfc_buf = list_entry(queue->head.next, struct s5p_mfc_buf, list); + mfc_buf = list_entry(queue->head.next, struct mfc_buf, list); if ((used == MFC_BUF_RESET_USED) || (used == MFC_BUF_SET_USED)) mfc_buf->used = used; @@ -111,12 +111,12 @@ struct s5p_mfc_buf *s5p_mfc_get_del_buf(spinlock_t *plock, struct s5p_mfc_buf_qu return mfc_buf; } -struct s5p_mfc_buf *s5p_mfc_get_del_if_consumed(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf_queue *queue, +struct mfc_buf *mfc_get_del_if_consumed(struct mfc_ctx *ctx, struct mfc_buf_queue *queue, unsigned long consumed, unsigned int min_bytes, int error, int *deleted) { unsigned long flags; - struct s5p_mfc_buf *mfc_buf = NULL; - struct s5p_mfc_dec *dec = ctx->dec_priv; + struct mfc_buf *mfc_buf = NULL; + struct mfc_dec *dec = ctx->dec_priv; unsigned long remained; spin_lock_irqsave(&ctx->buf_queue_lock, flags); @@ -127,7 +127,7 @@ struct s5p_mfc_buf *s5p_mfc_get_del_if_consumed(struct s5p_mfc_ctx *ctx, struct return NULL; } - mfc_buf = list_entry(queue->head.next, struct s5p_mfc_buf, list); + mfc_buf = list_entry(queue->head.next, struct mfc_buf, list); mfc_debug(2, "addr[0]: 0x%08llx\n", mfc_buf->addr[0][0]); @@ -154,12 +154,12 @@ struct s5p_mfc_buf *s5p_mfc_get_del_if_consumed(struct s5p_mfc_ctx *ctx, struct return mfc_buf; } -struct s5p_mfc_buf *s5p_mfc_get_move_buf(spinlock_t *plock, - struct s5p_mfc_buf_queue *to_queue, struct s5p_mfc_buf_queue *from_queue, - enum s5p_mfc_queue_used_type used, enum s5p_mfc_queue_top_type top) +struct mfc_buf *mfc_get_move_buf(spinlock_t *plock, + struct mfc_buf_queue *to_queue, struct mfc_buf_queue *from_queue, + enum mfc_queue_used_type used, enum mfc_queue_top_type top) { unsigned long flags; - struct s5p_mfc_buf *mfc_buf = NULL; + struct mfc_buf *mfc_buf = NULL; spin_lock_irqsave(plock, flags); @@ -169,7 +169,7 @@ struct s5p_mfc_buf *s5p_mfc_get_move_buf(spinlock_t *plock, return NULL; } - mfc_buf = list_entry(from_queue->head.next, struct s5p_mfc_buf, list); + mfc_buf = list_entry(from_queue->head.next, struct mfc_buf, list); if ((used == MFC_BUF_RESET_USED) || (used == MFC_BUF_SET_USED)) mfc_buf->used = used; @@ -190,11 +190,11 @@ struct s5p_mfc_buf *s5p_mfc_get_move_buf(spinlock_t *plock, return mfc_buf; } -struct s5p_mfc_buf *s5p_mfc_get_move_buf_used(spinlock_t *plock, - struct s5p_mfc_buf_queue *to_queue, struct s5p_mfc_buf_queue *from_queue) +struct mfc_buf *mfc_get_move_buf_used(spinlock_t *plock, + struct mfc_buf_queue *to_queue, struct mfc_buf_queue *from_queue) { unsigned long flags; - struct s5p_mfc_buf *mfc_buf = NULL; + struct mfc_buf *mfc_buf = NULL; spin_lock_irqsave(plock, flags); @@ -204,7 +204,7 @@ struct s5p_mfc_buf *s5p_mfc_get_move_buf_used(spinlock_t *plock, return NULL; } - mfc_buf = list_entry(from_queue->head.next, struct s5p_mfc_buf, list); + mfc_buf = list_entry(from_queue->head.next, struct mfc_buf, list); if (mfc_buf->used) { mfc_debug(2, "addr[0]: 0x%08llx\n", mfc_buf->addr[0][0]); @@ -223,12 +223,12 @@ struct s5p_mfc_buf *s5p_mfc_get_move_buf_used(spinlock_t *plock, } } -struct s5p_mfc_buf *s5p_mfc_get_move_buf_addr(spinlock_t *plock, - struct s5p_mfc_buf_queue *to_queue, struct s5p_mfc_buf_queue *from_queue, +struct mfc_buf *mfc_get_move_buf_addr(spinlock_t *plock, + struct mfc_buf_queue *to_queue, struct mfc_buf_queue *from_queue, dma_addr_t addr) { unsigned long flags; - struct s5p_mfc_buf *mfc_buf = NULL; + struct mfc_buf *mfc_buf = NULL; spin_lock_irqsave(plock, flags); @@ -238,7 +238,7 @@ struct s5p_mfc_buf *s5p_mfc_get_move_buf_addr(spinlock_t *plock, return NULL; } - mfc_buf = list_entry(from_queue->head.next, struct s5p_mfc_buf, list); + mfc_buf = list_entry(from_queue->head.next, struct mfc_buf, list); if (mfc_buf->addr[0][0] == addr) { mfc_debug(2, "[DPB] addr[0]: 0x%08llx\n", mfc_buf->addr[0][0]); @@ -257,11 +257,11 @@ struct s5p_mfc_buf *s5p_mfc_get_move_buf_addr(spinlock_t *plock, } } -struct s5p_mfc_buf *s5p_mfc_find_first_buf(spinlock_t *plock, struct s5p_mfc_buf_queue *queue, +struct mfc_buf *mfc_find_first_buf(spinlock_t *plock, struct mfc_buf_queue *queue, dma_addr_t addr) { unsigned long flags; - struct s5p_mfc_buf *mfc_buf = NULL; + struct mfc_buf *mfc_buf = NULL; dma_addr_t mb_addr; int i; @@ -274,7 +274,7 @@ struct s5p_mfc_buf *s5p_mfc_find_first_buf(spinlock_t *plock, struct s5p_mfc_buf } mfc_debug(4, "Looking for this address: 0x%08llx\n", addr); - mfc_buf = list_entry(queue->head.next, struct s5p_mfc_buf, list); + mfc_buf = list_entry(queue->head.next, struct mfc_buf, list); if (mfc_buf->num_valid_bufs > 0) { for (i = 0; i < mfc_buf->num_valid_bufs; i++) { mb_addr = mfc_buf->addr[i][0]; @@ -298,11 +298,11 @@ struct s5p_mfc_buf *s5p_mfc_find_first_buf(spinlock_t *plock, struct s5p_mfc_buf return NULL; } -struct s5p_mfc_buf *s5p_mfc_find_buf(spinlock_t *plock, struct s5p_mfc_buf_queue *queue, +struct mfc_buf *mfc_find_buf(spinlock_t *plock, struct mfc_buf_queue *queue, dma_addr_t addr) { unsigned long flags; - struct s5p_mfc_buf *mfc_buf = NULL; + struct mfc_buf *mfc_buf = NULL; dma_addr_t mb_addr; int i; @@ -334,11 +334,11 @@ struct s5p_mfc_buf *s5p_mfc_find_buf(spinlock_t *plock, struct s5p_mfc_buf_queue return NULL; } -struct s5p_mfc_buf *s5p_mfc_find_del_buf(spinlock_t *plock, struct s5p_mfc_buf_queue *queue, +struct mfc_buf *mfc_find_del_buf(spinlock_t *plock, struct mfc_buf_queue *queue, dma_addr_t addr) { unsigned long flags; - struct s5p_mfc_buf *mfc_buf = NULL; + struct mfc_buf *mfc_buf = NULL; dma_addr_t mb_addr; int found = 0, i; @@ -382,12 +382,12 @@ struct s5p_mfc_buf *s5p_mfc_find_del_buf(spinlock_t *plock, struct s5p_mfc_buf_q } } -struct s5p_mfc_buf *s5p_mfc_find_move_buf(spinlock_t *plock, - struct s5p_mfc_buf_queue *to_queue, struct s5p_mfc_buf_queue *from_queue, +struct mfc_buf *mfc_find_move_buf(spinlock_t *plock, + struct mfc_buf_queue *to_queue, struct mfc_buf_queue *from_queue, dma_addr_t addr, unsigned int released_flag) { unsigned long flags; - struct s5p_mfc_buf *mfc_buf = NULL; + struct mfc_buf *mfc_buf = NULL; dma_addr_t mb_addr; int found = 0; @@ -421,12 +421,12 @@ struct s5p_mfc_buf *s5p_mfc_find_move_buf(spinlock_t *plock, } } -struct s5p_mfc_buf *s5p_mfc_find_move_buf_used(spinlock_t *plock, - struct s5p_mfc_buf_queue *to_queue, struct s5p_mfc_buf_queue *from_queue, +struct mfc_buf *mfc_find_move_buf_used(spinlock_t *plock, + struct mfc_buf_queue *to_queue, struct mfc_buf_queue *from_queue, dma_addr_t addr) { unsigned long flags; - struct s5p_mfc_buf *mfc_buf = NULL; + struct mfc_buf *mfc_buf = NULL; dma_addr_t mb_addr; int found = 0; @@ -459,11 +459,11 @@ struct s5p_mfc_buf *s5p_mfc_find_move_buf_used(spinlock_t *plock, } } -void s5p_mfc_move_first_buf_used(spinlock_t *plock, struct s5p_mfc_buf_queue *to_queue, - struct s5p_mfc_buf_queue *from_queue, enum s5p_mfc_queue_top_type top) +void mfc_move_first_buf_used(spinlock_t *plock, struct mfc_buf_queue *to_queue, + struct mfc_buf_queue *from_queue, enum mfc_queue_top_type top) { unsigned long flags; - struct s5p_mfc_buf *mfc_buf = NULL; + struct mfc_buf *mfc_buf = NULL; spin_lock_irqsave(plock, flags); @@ -472,7 +472,7 @@ void s5p_mfc_move_first_buf_used(spinlock_t *plock, struct s5p_mfc_buf_queue *to spin_unlock_irqrestore(plock, flags); return; } - mfc_buf = list_entry(from_queue->head.next, struct s5p_mfc_buf, list); + mfc_buf = list_entry(from_queue->head.next, struct mfc_buf, list); if (mfc_buf->used) { list_del(&mfc_buf->list); @@ -489,17 +489,17 @@ void s5p_mfc_move_first_buf_used(spinlock_t *plock, struct s5p_mfc_buf_queue *to spin_unlock_irqrestore(plock, flags); } -void s5p_mfc_move_all_bufs(spinlock_t *plock, struct s5p_mfc_buf_queue *to_queue, - struct s5p_mfc_buf_queue *from_queue, enum s5p_mfc_queue_top_type top) +void mfc_move_all_bufs(spinlock_t *plock, struct mfc_buf_queue *to_queue, + struct mfc_buf_queue *from_queue, enum mfc_queue_top_type top) { unsigned long flags; - struct s5p_mfc_buf *mfc_buf = NULL; + struct mfc_buf *mfc_buf = NULL; spin_lock_irqsave(plock, flags); if (top == MFC_QUEUE_ADD_TOP) { while (!list_empty(&from_queue->head)) { - mfc_buf = list_entry(from_queue->head.prev, struct s5p_mfc_buf, list); + mfc_buf = list_entry(from_queue->head.prev, struct mfc_buf, list); list_del(&mfc_buf->list); from_queue->count--; @@ -509,7 +509,7 @@ void s5p_mfc_move_all_bufs(spinlock_t *plock, struct s5p_mfc_buf_queue *to_queue } } else { while (!list_empty(&from_queue->head)) { - mfc_buf = list_entry(from_queue->head.next, struct s5p_mfc_buf, list); + mfc_buf = list_entry(from_queue->head.next, struct mfc_buf, list); list_del(&mfc_buf->list); from_queue->count--; @@ -525,16 +525,16 @@ void s5p_mfc_move_all_bufs(spinlock_t *plock, struct s5p_mfc_buf_queue *to_queue spin_unlock_irqrestore(plock, flags); } -void s5p_mfc_cleanup_queue(spinlock_t *plock, struct s5p_mfc_buf_queue *queue) +void mfc_cleanup_queue(spinlock_t *plock, struct mfc_buf_queue *queue) { unsigned long flags; - struct s5p_mfc_buf *mfc_buf = NULL; + struct mfc_buf *mfc_buf = NULL; int i; spin_lock_irqsave(plock, flags); while (!list_empty(&queue->head)) { - mfc_buf = list_entry(queue->head.next, struct s5p_mfc_buf, list); + mfc_buf = list_entry(queue->head.next, struct mfc_buf, list); for (i = 0; i < mfc_buf->vb.vb2_buf.num_planes; i++) vb2_set_plane_payload(&mfc_buf->vb.vb2_buf, i, 0); @@ -549,19 +549,19 @@ void s5p_mfc_cleanup_queue(spinlock_t *plock, struct s5p_mfc_buf_queue *queue) spin_unlock_irqrestore(plock, flags); } -static void mfc_cleanup_batch_queue(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf_queue *queue) +static void __mfc_cleanup_batch_queue(struct mfc_ctx *ctx, struct mfc_buf_queue *queue) { unsigned long flags; - struct s5p_mfc_buf *mfc_buf = NULL; + struct mfc_buf *mfc_buf = NULL; int i; spin_lock_irqsave(&ctx->buf_queue_lock, flags); while (!list_empty(&queue->head)) { - mfc_buf = list_entry(queue->head.next, struct s5p_mfc_buf, list); + mfc_buf = list_entry(queue->head.next, struct mfc_buf, list); for (i = 0; i < mfc_buf->vb.vb2_buf.num_planes; i++) { - s5p_mfc_bufcon_put_daddr(ctx, mfc_buf, i); + mfc_bufcon_put_daddr(ctx, mfc_buf, i); vb2_set_plane_payload(&mfc_buf->vb.vb2_buf, i, 0); } vb2_buffer_done(&mfc_buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); @@ -576,11 +576,11 @@ static void mfc_cleanup_batch_queue(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf_ spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); } -struct s5p_mfc_buf *mfc_find_buf_index(spinlock_t *plock, struct s5p_mfc_buf_queue *queue, +struct mfc_buf *__mfc_find_buf_index(spinlock_t *plock, struct mfc_buf_queue *queue, int index) { unsigned long flags; - struct s5p_mfc_buf *mfc_buf = NULL; + struct mfc_buf *mfc_buf = NULL; int buf_index; spin_lock_irqsave(plock, flags); @@ -604,13 +604,13 @@ struct s5p_mfc_buf *mfc_find_buf_index(spinlock_t *plock, struct s5p_mfc_buf_que * Check released and enqueued buffers. (dst queue) * Check and move reuse buffers. (ref -> dst queue) */ -static void mfc_check_ref_frame(spinlock_t *plock, struct s5p_mfc_buf_queue *dst_queue, - struct s5p_mfc_buf_queue *ref_queue, - struct s5p_mfc_ctx *ctx, int ref_index) +static void __mfc_check_ref_frame(spinlock_t *plock, struct mfc_buf_queue *dst_queue, + struct mfc_buf_queue *ref_queue, + struct mfc_ctx *ctx, int ref_index) { unsigned long flags; - struct s5p_mfc_dec *dec = ctx->dec_priv; - struct s5p_mfc_buf *ref_mb, *tmp_mb; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_buf *ref_mb, *tmp_mb; int index; int found = 0; @@ -655,10 +655,10 @@ static void mfc_check_ref_frame(spinlock_t *plock, struct s5p_mfc_buf_queue *dst } /* Process the released reference information */ -void s5p_mfc_handle_released_info(struct s5p_mfc_ctx *ctx, +void mfc_handle_released_info(struct mfc_ctx *ctx, unsigned int released_flag, int index) { - struct s5p_mfc_dec *dec; + struct mfc_dec *dec; struct dec_dpb_ref_info *refBuf; int t, ncount = 0; @@ -690,7 +690,7 @@ void s5p_mfc_handle_released_info(struct s5p_mfc_ctx *ctx, t, dec->assigned_fd[t]); dec->err_reuse_flag &= ~(1 << t); } else if ((t != index) && - mfc_find_buf_index(&ctx->buf_queue_lock, &ctx->ref_buf_queue, t)) { + __mfc_find_buf_index(&ctx->buf_queue_lock, &ctx->ref_buf_queue, t)) { /* decoding only frame: do not update released info */ mfc_debug(2, "[DPB] Released, but reuse(decoding only). FD[%d] = %03d\n", t, dec->assigned_fd[t]); @@ -702,7 +702,7 @@ void s5p_mfc_handle_released_info(struct s5p_mfc_ctx *ctx, ncount++; } dec->assigned_fd[t] = MFC_INFO_INIT_FD; - mfc_check_ref_frame(&ctx->buf_queue_lock, &ctx->dst_buf_queue, + __mfc_check_ref_frame(&ctx->buf_queue_lock, &ctx->dst_buf_queue, &ctx->ref_buf_queue, ctx, t); } } @@ -712,12 +712,12 @@ void s5p_mfc_handle_released_info(struct s5p_mfc_ctx *ctx, refBuf->dpb[ncount].fd[0] = MFC_INFO_INIT_FD; } -struct s5p_mfc_buf *s5p_mfc_move_reuse_buffer(struct s5p_mfc_ctx *ctx, int release_index) +struct mfc_buf *mfc_move_reuse_buffer(struct mfc_ctx *ctx, int release_index) { - struct s5p_mfc_dec *dec = ctx->dec_priv; - struct s5p_mfc_buf_queue *dst_queue = &ctx->dst_buf_queue; - struct s5p_mfc_buf_queue *ref_queue = &ctx->ref_buf_queue; - struct s5p_mfc_buf *ref_mb, *tmp_mb; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_buf_queue *dst_queue = &ctx->dst_buf_queue; + struct mfc_buf_queue *ref_queue = &ctx->ref_buf_queue; + struct mfc_buf *ref_mb, *tmp_mb; spinlock_t *plock = &ctx->buf_queue_lock; unsigned long flags; int index; @@ -727,7 +727,7 @@ struct s5p_mfc_buf *s5p_mfc_move_reuse_buffer(struct s5p_mfc_ctx *ctx, int relea list_for_each_entry_safe(ref_mb, tmp_mb, &ref_queue->head, list) { index = ref_mb->vb.vb2_buf.index; if (index == release_index) { - s5p_mfc_raw_unprotect(ctx, ref_mb, index); + mfc_raw_unprotect(ctx, ref_mb, index); ref_mb->used = 0; @@ -749,10 +749,10 @@ struct s5p_mfc_buf *s5p_mfc_move_reuse_buffer(struct s5p_mfc_ctx *ctx, int relea return NULL; } -void s5p_mfc_cleanup_enc_src_queue(struct s5p_mfc_ctx *ctx) +void mfc_cleanup_enc_src_queue(struct mfc_ctx *ctx) { unsigned long flags; - struct s5p_mfc_buf *src_mb, *tmp_mb; + struct mfc_buf *src_mb, *tmp_mb; int i; if (ctx->is_drm && ctx->raw_protect_flag) { @@ -764,10 +764,10 @@ void s5p_mfc_cleanup_enc_src_queue(struct s5p_mfc_ctx *ctx) list_for_each_entry_safe(src_mb, tmp_mb, &ctx->src_buf_queue.head, list) { i = src_mb->vb.vb2_buf.index; - s5p_mfc_raw_unprotect(ctx, src_mb, i); + mfc_raw_unprotect(ctx, src_mb, i); for (i = 0; i < src_mb->vb.vb2_buf.num_planes; i++) { - s5p_mfc_bufcon_put_daddr(ctx, src_mb, i); + mfc_bufcon_put_daddr(ctx, src_mb, i); vb2_set_plane_payload(&src_mb->vb.vb2_buf, i, 0); } @@ -782,17 +782,17 @@ void s5p_mfc_cleanup_enc_src_queue(struct s5p_mfc_ctx *ctx) spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); } else { if (IS_BUFFER_BATCH_MODE(ctx)) - mfc_cleanup_batch_queue(ctx, &ctx->src_buf_queue); + __mfc_cleanup_batch_queue(ctx, &ctx->src_buf_queue); else - s5p_mfc_cleanup_queue(&ctx->buf_queue_lock, &ctx->src_buf_queue); + mfc_cleanup_queue(&ctx->buf_queue_lock, &ctx->src_buf_queue); } } -void s5p_mfc_cleanup_enc_dst_queue(struct s5p_mfc_ctx *ctx) +void mfc_cleanup_enc_dst_queue(struct mfc_ctx *ctx) { unsigned long flags; - struct s5p_mfc_buf *dst_mb, *tmp_mb; + struct mfc_buf *dst_mb, *tmp_mb; int i; if (ctx->is_drm && ctx->stream_protect_flag) { @@ -804,7 +804,7 @@ void s5p_mfc_cleanup_enc_dst_queue(struct s5p_mfc_ctx *ctx) list_for_each_entry_safe(dst_mb, tmp_mb, &ctx->dst_buf_queue.head, list) { i = dst_mb->vb.vb2_buf.index; - s5p_mfc_stream_unprotect(ctx, dst_mb, i); + mfc_stream_unprotect(ctx, dst_mb, i); for (i = 0; i < dst_mb->vb.vb2_buf.num_planes; i++) vb2_set_plane_payload(&dst_mb->vb.vb2_buf, i, 0); @@ -818,15 +818,15 @@ void s5p_mfc_cleanup_enc_dst_queue(struct s5p_mfc_ctx *ctx) spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); } else { - s5p_mfc_cleanup_queue(&ctx->buf_queue_lock, &ctx->dst_buf_queue); + mfc_cleanup_queue(&ctx->buf_queue_lock, &ctx->dst_buf_queue); } } /* Check all buffers are referenced or not */ -struct s5p_mfc_buf *mfc_check_full_refered_dpb(struct s5p_mfc_ctx *ctx) +struct mfc_buf *__mfc_check_full_refered_dpb(struct mfc_ctx *ctx) { - struct s5p_mfc_dec *dec = NULL; - struct s5p_mfc_buf *mfc_buf = NULL; + struct mfc_dec *dec = NULL; + struct mfc_buf *mfc_buf = NULL; int sum_dpb; dec = ctx->dec_priv; @@ -844,7 +844,7 @@ struct s5p_mfc_buf *mfc_check_full_refered_dpb(struct s5p_mfc_ctx *ctx) } mfc_debug(3, "[DPB] We should use this buffer\n"); mfc_buf = list_entry(ctx->dst_buf_queue.head.next, - struct s5p_mfc_buf, list); + struct mfc_buf, list); } else if ((ctx->dst_buf_queue.count == 0) && ((ctx->ref_buf_queue.count) == (ctx->dpb_count + 5))) { if (list_empty(&ctx->ref_buf_queue.head)) { @@ -853,7 +853,7 @@ struct s5p_mfc_buf *mfc_check_full_refered_dpb(struct s5p_mfc_ctx *ctx) } mfc_debug(3, "[DPB] All buffers are referenced\n"); mfc_buf = list_entry(ctx->ref_buf_queue.head.next, - struct s5p_mfc_buf, list); + struct mfc_buf, list); } else { mfc_debug(3, "[DPB] waiting for dst buffer, ref = %d, dst = %d\n", ctx->ref_buf_queue.count, ctx->dst_buf_queue.count); @@ -867,10 +867,10 @@ struct s5p_mfc_buf *mfc_check_full_refered_dpb(struct s5p_mfc_ctx *ctx) } /* Try to search non-referenced DPB on dst-queue */ -struct s5p_mfc_buf *s5p_mfc_search_for_dpb(struct s5p_mfc_ctx *ctx, unsigned int dynamic_used) +struct mfc_buf *mfc_search_for_dpb(struct mfc_ctx *ctx, unsigned int dynamic_used) { unsigned long flags; - struct s5p_mfc_buf *mfc_buf = NULL; + struct mfc_buf *mfc_buf = NULL; spin_lock_irqsave(&ctx->buf_queue_lock, flags); @@ -883,18 +883,18 @@ struct s5p_mfc_buf *s5p_mfc_search_for_dpb(struct s5p_mfc_ctx *ctx, unsigned int } } - mfc_buf = mfc_check_full_refered_dpb(ctx); + mfc_buf = __mfc_check_full_refered_dpb(ctx); spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); return mfc_buf; } -struct s5p_mfc_buf *s5p_mfc_search_move_dpb_nal_q(struct s5p_mfc_ctx *ctx, unsigned int dynamic_used) +struct mfc_buf *mfc_search_move_dpb_nal_q(struct mfc_ctx *ctx, unsigned int dynamic_used) { unsigned long flags; - struct s5p_mfc_buf *mfc_buf = NULL; - struct s5p_mfc_dec *dec = NULL; + struct mfc_buf *mfc_buf = NULL; + struct mfc_dec *dec = NULL; dec = ctx->dec_priv; if (!dec) { @@ -920,7 +920,7 @@ struct s5p_mfc_buf *s5p_mfc_search_move_dpb_nal_q(struct s5p_mfc_ctx *ctx, unsig } } - mfc_buf = mfc_check_full_refered_dpb(ctx); + mfc_buf = __mfc_check_full_refered_dpb(ctx); if (mfc_buf) { mfc_debug(2, "[NALQ][DPB] DPB is full. stop NAL-Q if started\n"); @@ -933,11 +933,11 @@ struct s5p_mfc_buf *s5p_mfc_search_move_dpb_nal_q(struct s5p_mfc_ctx *ctx, unsig } /* Add dst buffer in dst_buf_queue */ -void s5p_mfc_store_dpb(struct s5p_mfc_ctx *ctx, struct vb2_buffer *vb) +void mfc_store_dpb(struct mfc_ctx *ctx, struct vb2_buffer *vb) { unsigned long flags; - struct s5p_mfc_dec *dec; - struct s5p_mfc_buf *mfc_buf; + struct mfc_dec *dec; + struct mfc_buf *mfc_buf; int index; if (!ctx) { @@ -967,17 +967,17 @@ void s5p_mfc_store_dpb(struct s5p_mfc_ctx *ctx, struct vb2_buffer *vb) spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); } -void s5p_mfc_cleanup_nal_queue(struct s5p_mfc_ctx *ctx) +void mfc_cleanup_nal_queue(struct mfc_ctx *ctx) { - struct s5p_mfc_dec *dec = ctx->dec_priv; - struct s5p_mfc_buf *src_mb, *dst_mb; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_buf *src_mb, *dst_mb; unsigned long flags; unsigned int index; spin_lock_irqsave(&ctx->buf_queue_lock, flags); while (!list_empty(&ctx->src_buf_nal_queue.head)) { - src_mb = list_entry(ctx->src_buf_nal_queue.head.prev, struct s5p_mfc_buf, list); + src_mb = list_entry(ctx->src_buf_nal_queue.head.prev, struct mfc_buf, list); index = src_mb->vb.vb2_buf.index; call_cop(ctx, recover_buf_ctrls_nal_q, ctx, &ctx->src_ctrls[index]); @@ -1002,7 +1002,7 @@ void s5p_mfc_cleanup_nal_queue(struct s5p_mfc_ctx *ctx) } while (!list_empty(&ctx->dst_buf_nal_queue.head)) { - dst_mb = list_entry(ctx->dst_buf_nal_queue.head.prev, struct s5p_mfc_buf, list); + dst_mb = list_entry(ctx->dst_buf_nal_queue.head.prev, struct mfc_buf, list); dst_mb->used = 0; if (ctx->type == MFCINST_DECODER) @@ -1020,10 +1020,10 @@ void s5p_mfc_cleanup_nal_queue(struct s5p_mfc_ctx *ctx) spin_unlock_irqrestore(&ctx->buf_queue_lock, flags); } -int s5p_mfc_is_last_frame(struct s5p_mfc_ctx *ctx) +int mfc_is_last_frame(struct mfc_ctx *ctx) { - struct s5p_mfc_buf *src_mb; - struct s5p_mfc_dev *dev; + struct mfc_buf *src_mb; + struct mfc_dev *dev; unsigned long flags; mfc_debug_enter(); @@ -1047,7 +1047,7 @@ int s5p_mfc_is_last_frame(struct s5p_mfc_ctx *ctx) return -EINVAL; } - src_mb = list_entry(ctx->src_buf_queue.head.next, struct s5p_mfc_buf, list); + src_mb = list_entry(ctx->src_buf_queue.head.next, struct mfc_buf, list); mfc_debug(4, "addr[0]: 0x%08llx\n", src_mb->addr[0][0]); diff --git a/drivers/media/platform/exynos/mfc/mfc_queue.h b/drivers/media/platform/exynos/mfc/mfc_queue.h index 71dfc4245700..2c9345531392 100644 --- a/drivers/media/platform/exynos/mfc/mfc_queue.h +++ b/drivers/media/platform/exynos/mfc/mfc_queue.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_queue.h + * drivers/media/platform/exynos/mfc/mfc_queue.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -16,23 +16,23 @@ #include "mfc_common.h" /** - * enum s5p_mfc_queue_used_type + * enum mfc_queue_used_type */ -enum s5p_mfc_queue_used_type { +enum mfc_queue_used_type { MFC_BUF_NO_TOUCH_USED = -1, MFC_BUF_RESET_USED = 0, MFC_BUF_SET_USED = 1, }; /** - * enum s5p_mfc_queue_top_type + * enum mfc_queue_top_type */ -enum s5p_mfc_queue_top_type { +enum mfc_queue_top_type { MFC_QUEUE_ADD_BOTTOM = 0, MFC_QUEUE_ADD_TOP = 1, }; -static inline unsigned int s5p_mfc_get_queue_count(spinlock_t *plock, struct s5p_mfc_buf_queue *queue) +static inline unsigned int mfc_get_queue_count(spinlock_t *plock, struct mfc_buf_queue *queue) { unsigned long flags; unsigned int ret = 0; @@ -44,7 +44,7 @@ static inline unsigned int s5p_mfc_get_queue_count(spinlock_t *plock, struct s5p return ret; } -static inline int s5p_mfc_is_queue_count_same(spinlock_t *plock, struct s5p_mfc_buf_queue *queue, +static inline int mfc_is_queue_count_same(spinlock_t *plock, struct mfc_buf_queue *queue, unsigned int value) { unsigned long flags; @@ -58,7 +58,7 @@ static inline int s5p_mfc_is_queue_count_same(spinlock_t *plock, struct s5p_mfc_ return ret; } -static inline int s5p_mfc_is_queue_count_greater(spinlock_t *plock, struct s5p_mfc_buf_queue *queue, +static inline int mfc_is_queue_count_greater(spinlock_t *plock, struct mfc_buf_queue *queue, unsigned int value) { unsigned long flags; @@ -72,7 +72,7 @@ static inline int s5p_mfc_is_queue_count_greater(spinlock_t *plock, struct s5p_m return ret; } -static inline int s5p_mfc_is_queue_count_smaller(spinlock_t *plock, struct s5p_mfc_buf_queue *queue, +static inline int mfc_is_queue_count_smaller(spinlock_t *plock, struct mfc_buf_queue *queue, unsigned int value) { unsigned long flags; @@ -86,75 +86,75 @@ static inline int s5p_mfc_is_queue_count_smaller(spinlock_t *plock, struct s5p_m return ret; } -static inline void s5p_mfc_init_queue(struct s5p_mfc_buf_queue *queue) +static inline void mfc_init_queue(struct mfc_buf_queue *queue) { INIT_LIST_HEAD(&queue->head); queue->count = 0; } -static inline void s5p_mfc_create_queue(struct s5p_mfc_buf_queue *queue) +static inline void mfc_create_queue(struct mfc_buf_queue *queue) { - s5p_mfc_init_queue(queue); + mfc_init_queue(queue); } -static inline void s5p_mfc_delete_queue(struct s5p_mfc_buf_queue *queue) +static inline void mfc_delete_queue(struct mfc_buf_queue *queue) { - s5p_mfc_init_queue(queue); + mfc_init_queue(queue); } -void s5p_mfc_add_tail_buf(spinlock_t *plock, struct s5p_mfc_buf_queue *queue, - struct s5p_mfc_buf *mfc_buf); +void mfc_add_tail_buf(spinlock_t *plock, struct mfc_buf_queue *queue, + struct mfc_buf *mfc_buf); -int s5p_mfc_peek_buf_csd(spinlock_t *plock, struct s5p_mfc_buf_queue *queue); +int mfc_peek_buf_csd(spinlock_t *plock, struct mfc_buf_queue *queue); -struct s5p_mfc_buf *s5p_mfc_get_buf(spinlock_t *plock, struct s5p_mfc_buf_queue *queue, - enum s5p_mfc_queue_used_type used); -struct s5p_mfc_buf *s5p_mfc_get_del_buf(spinlock_t *plock, struct s5p_mfc_buf_queue *queue, - enum s5p_mfc_queue_used_type used); -struct s5p_mfc_buf *s5p_mfc_get_del_if_consumed(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf_queue *queue, +struct mfc_buf *mfc_get_buf(spinlock_t *plock, struct mfc_buf_queue *queue, + enum mfc_queue_used_type used); +struct mfc_buf *mfc_get_del_buf(spinlock_t *plock, struct mfc_buf_queue *queue, + enum mfc_queue_used_type used); +struct mfc_buf *mfc_get_del_if_consumed(struct mfc_ctx *ctx, struct mfc_buf_queue *queue, unsigned long consumed, unsigned int min_bytes, int err, int *deleted); -struct s5p_mfc_buf *s5p_mfc_get_move_buf(spinlock_t *plock, - struct s5p_mfc_buf_queue *to_queue, struct s5p_mfc_buf_queue *from_queue, - enum s5p_mfc_queue_used_type used, enum s5p_mfc_queue_top_type top); -struct s5p_mfc_buf *s5p_mfc_get_move_buf_used(spinlock_t *plock, - struct s5p_mfc_buf_queue *to_queue, struct s5p_mfc_buf_queue *from_queue); -struct s5p_mfc_buf *s5p_mfc_get_move_buf_addr(spinlock_t *plock, - struct s5p_mfc_buf_queue *to_queue, struct s5p_mfc_buf_queue *from_queue, +struct mfc_buf *mfc_get_move_buf(spinlock_t *plock, + struct mfc_buf_queue *to_queue, struct mfc_buf_queue *from_queue, + enum mfc_queue_used_type used, enum mfc_queue_top_type top); +struct mfc_buf *mfc_get_move_buf_used(spinlock_t *plock, + struct mfc_buf_queue *to_queue, struct mfc_buf_queue *from_queue); +struct mfc_buf *mfc_get_move_buf_addr(spinlock_t *plock, + struct mfc_buf_queue *to_queue, struct mfc_buf_queue *from_queue, dma_addr_t addr); -struct s5p_mfc_buf *s5p_mfc_find_first_buf(spinlock_t *plock, struct s5p_mfc_buf_queue *queue, +struct mfc_buf *mfc_find_first_buf(spinlock_t *plock, struct mfc_buf_queue *queue, dma_addr_t addr); -struct s5p_mfc_buf *s5p_mfc_find_buf(spinlock_t *plock, struct s5p_mfc_buf_queue *queue, +struct mfc_buf *mfc_find_buf(spinlock_t *plock, struct mfc_buf_queue *queue, dma_addr_t addr); -struct s5p_mfc_buf *s5p_mfc_find_del_buf(spinlock_t *plock, struct s5p_mfc_buf_queue *queue, +struct mfc_buf *mfc_find_del_buf(spinlock_t *plock, struct mfc_buf_queue *queue, dma_addr_t addr); -struct s5p_mfc_buf *s5p_mfc_find_move_buf(spinlock_t *plock, - struct s5p_mfc_buf_queue *to_queue, struct s5p_mfc_buf_queue *from_queue, +struct mfc_buf *mfc_find_move_buf(spinlock_t *plock, + struct mfc_buf_queue *to_queue, struct mfc_buf_queue *from_queue, dma_addr_t addr, unsigned int released_flag); -struct s5p_mfc_buf *s5p_mfc_find_move_buf_used(spinlock_t *plock, - struct s5p_mfc_buf_queue *to_queue, struct s5p_mfc_buf_queue *from_queue, +struct mfc_buf *mfc_find_move_buf_used(spinlock_t *plock, + struct mfc_buf_queue *to_queue, struct mfc_buf_queue *from_queue, dma_addr_t addr); -void s5p_mfc_move_first_buf_used(spinlock_t *plock, struct s5p_mfc_buf_queue *to_queue, - struct s5p_mfc_buf_queue *from_queue, enum s5p_mfc_queue_top_type top); -void s5p_mfc_move_all_bufs(spinlock_t *plock, struct s5p_mfc_buf_queue *to_queue, - struct s5p_mfc_buf_queue *from_queue, enum s5p_mfc_queue_top_type top); +void mfc_move_first_buf_used(spinlock_t *plock, struct mfc_buf_queue *to_queue, + struct mfc_buf_queue *from_queue, enum mfc_queue_top_type top); +void mfc_move_all_bufs(spinlock_t *plock, struct mfc_buf_queue *to_queue, + struct mfc_buf_queue *from_queue, enum mfc_queue_top_type top); -void s5p_mfc_cleanup_queue(spinlock_t *plock, struct s5p_mfc_buf_queue *queue); +void mfc_cleanup_queue(spinlock_t *plock, struct mfc_buf_queue *queue); -void s5p_mfc_handle_released_info(struct s5p_mfc_ctx *ctx, +void mfc_handle_released_info(struct mfc_ctx *ctx, unsigned int released_flag, int index); -struct s5p_mfc_buf *s5p_mfc_move_reuse_buffer(struct s5p_mfc_ctx *ctx, int release_index); +struct mfc_buf *mfc_move_reuse_buffer(struct mfc_ctx *ctx, int release_index); -void s5p_mfc_cleanup_enc_src_queue(struct s5p_mfc_ctx *ctx); -void s5p_mfc_cleanup_enc_dst_queue(struct s5p_mfc_ctx *ctx); +void mfc_cleanup_enc_src_queue(struct mfc_ctx *ctx); +void mfc_cleanup_enc_dst_queue(struct mfc_ctx *ctx); -struct s5p_mfc_buf *s5p_mfc_search_for_dpb(struct s5p_mfc_ctx *ctx, unsigned int dynamic_used); -struct s5p_mfc_buf *s5p_mfc_search_move_dpb_nal_q(struct s5p_mfc_ctx *ctx, unsigned int dynamic_used); -void s5p_mfc_store_dpb(struct s5p_mfc_ctx *ctx, struct vb2_buffer *vb); +struct mfc_buf *mfc_search_for_dpb(struct mfc_ctx *ctx, unsigned int dynamic_used); +struct mfc_buf *mfc_search_move_dpb_nal_q(struct mfc_ctx *ctx, unsigned int dynamic_used); +void mfc_store_dpb(struct mfc_ctx *ctx, struct vb2_buffer *vb); -void s5p_mfc_cleanup_nal_queue(struct s5p_mfc_ctx *ctx); -int s5p_mfc_is_last_frame(struct s5p_mfc_ctx *ctx); +void mfc_cleanup_nal_queue(struct mfc_ctx *ctx); +int mfc_is_last_frame(struct mfc_ctx *ctx); #endif /* __MFC_QUEUE_H */ diff --git a/drivers/media/platform/exynos/mfc/mfc_reg.c b/drivers/media/platform/exynos/mfc/mfc_reg.c index 1631025693eb..772af91d4ada 100644 --- a/drivers/media/platform/exynos/mfc/mfc_reg.c +++ b/drivers/media/platform/exynos/mfc/mfc_reg.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_reg.c + * drivers/media/platform/exynos/mfc/mfc_reg.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -14,31 +14,31 @@ #include "mfc_reg.h" -void s5p_mfc_dbg_enable(struct s5p_mfc_dev *dev) +void mfc_dbg_enable(struct mfc_dev *dev) { mfc_debug(2, "MFC debug info enable\n"); - MFC_WRITEL(0x1, S5P_FIMV_DBG_INFO_ENABLE); + MFC_WRITEL(0x1, MFC_REG_DBG_INFO_ENABLE); } -void s5p_mfc_dbg_disable(struct s5p_mfc_dev *dev) +void mfc_dbg_disable(struct mfc_dev *dev) { mfc_debug(2, "MFC debug info disable\n"); - MFC_WRITEL(0x0, S5P_FIMV_DBG_INFO_ENABLE); + MFC_WRITEL(0x0, MFC_REG_DBG_INFO_ENABLE); } -void s5p_mfc_dbg_set_addr(struct s5p_mfc_dev *dev) +void mfc_dbg_set_addr(struct mfc_dev *dev) { - struct s5p_mfc_ctx_buf_size *buf_size = dev->variant->buf_size->ctx_buf; + struct mfc_ctx_buf_size *buf_size = dev->variant->buf_size->ctx_buf; memset((void *)dev->dbg_info_buf.vaddr, 0, buf_size->dbg_info_buf); - MFC_WRITEL(dev->dbg_info_buf.daddr, S5P_FIMV_DBG_BUFFER_ADDR); - MFC_WRITEL(buf_size->dbg_info_buf, S5P_FIMV_DBG_BUFFER_SIZE); + MFC_WRITEL(dev->dbg_info_buf.daddr, MFC_REG_DBG_BUFFER_ADDR); + MFC_WRITEL(buf_size->dbg_info_buf, MFC_REG_DBG_BUFFER_SIZE); } -void s5p_mfc_otf_set_frame_addr(struct s5p_mfc_ctx *ctx, int num_planes) +void mfc_otf_set_frame_addr(struct mfc_ctx *ctx, int num_planes) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; struct _otf_handle *handle = ctx->otf_handle; struct _otf_buf_addr *buf_addr = &handle->otf_buf_addr; int index = handle->otf_buf_index; @@ -48,48 +48,48 @@ void s5p_mfc_otf_set_frame_addr(struct s5p_mfc_ctx *ctx, int num_planes) mfc_debug(2, "[OTF][FRAME] set frame buffer[%d], 0x%08llx)\n", i, buf_addr->otf_daddr[index][i]); MFC_WRITEL(buf_addr->otf_daddr[index][i], - S5P_FIMV_E_SOURCE_FIRST_ADDR + (i * 4)); + MFC_REG_E_SOURCE_FIRST_ADDR + (i * 4)); } } -void s5p_mfc_otf_set_stream_size(struct s5p_mfc_ctx *ctx, unsigned int size) +void mfc_otf_set_stream_size(struct mfc_ctx *ctx, unsigned int size) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; struct _otf_handle *handle = ctx->otf_handle; struct _otf_debug *debug = &handle->otf_debug; - struct s5p_mfc_special_buf *buf; + struct mfc_special_buf *buf; mfc_debug(2, "[OTF] set stream buffer full size, %u\n", size); - MFC_WRITEL(size, S5P_FIMV_E_STREAM_BUFFER_SIZE); + MFC_WRITEL(size, MFC_REG_E_STREAM_BUFFER_SIZE); if (otf_dump && !ctx->is_drm) { buf = &debug->stream_buf[debug->frame_cnt]; mfc_debug(2, "[OTF] set stream addr for debugging\n"); mfc_debug(2, "[OTF][STREAM] buf[%d] daddr: 0x%08llx\n", debug->frame_cnt, buf->daddr); - MFC_WRITEL(buf->daddr, S5P_FIMV_E_STREAM_BUFFER_ADDR); + MFC_WRITEL(buf->daddr, MFC_REG_E_STREAM_BUFFER_ADDR); } } -void s5p_mfc_otf_set_hwfc_index(struct s5p_mfc_ctx *ctx, int job_id) +void mfc_otf_set_hwfc_index(struct mfc_ctx *ctx, int job_id) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; mfc_debug(2, "[OTF] set hwfc index, %d\n", job_id); HWFC_WRITEL(job_id, HWFC_ENCODING_IDX); } /* Set decoding frame buffer */ -int s5p_mfc_set_dec_codec_buffers(struct s5p_mfc_ctx *ctx) +int mfc_set_dec_codec_buffers(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev; - struct s5p_mfc_dec *dec; + struct mfc_dev *dev; + struct mfc_dec *dec; unsigned int i; size_t frame_size_mv; dma_addr_t buf_addr; int buf_size; int align_gap; - struct s5p_mfc_raw_info *raw; + struct mfc_raw_info *raw; unsigned int reg = 0; if (!ctx) { @@ -118,33 +118,33 @@ int s5p_mfc_set_dec_codec_buffers(struct s5p_mfc_ctx *ctx) dec->total_dpb_count, dec->display_delay); /* set decoder DPB size, stride */ - MFC_WRITEL(dec->total_dpb_count, S5P_FIMV_D_NUM_DPB); + MFC_WRITEL(dec->total_dpb_count, MFC_REG_D_NUM_DPB); for (i = 0; i < raw->num_planes; i++) { mfc_debug(2, "[FRAME] buf[%d] size: %d, stride: %d\n", i, raw->plane_size[i], raw->stride[i]); - MFC_WRITEL(raw->plane_size[i], S5P_FIMV_D_FIRST_PLANE_DPB_SIZE + (i * 4)); + MFC_WRITEL(raw->plane_size[i], MFC_REG_D_FIRST_PLANE_DPB_SIZE + (i * 4)); MFC_WRITEL(ctx->raw_buf.stride[i], - S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE + (i * 4)); + MFC_REG_D_FIRST_PLANE_DPB_STRIDE_SIZE + (i * 4)); if (ctx->is_10bit) { - MFC_WRITEL(raw->stride_2bits[i], S5P_FIMV_D_FIRST_PLANE_2BIT_DPB_STRIDE_SIZE + (i * 4)); - MFC_WRITEL(raw->plane_size_2bits[i], S5P_FIMV_D_FIRST_PLANE_2BIT_DPB_SIZE + (i * 4)); + MFC_WRITEL(raw->stride_2bits[i], MFC_REG_D_FIRST_PLANE_2BIT_DPB_STRIDE_SIZE + (i * 4)); + MFC_WRITEL(raw->plane_size_2bits[i], MFC_REG_D_FIRST_PLANE_2BIT_DPB_SIZE + (i * 4)); mfc_debug(2, "[FRAME][10BIT] 2bits buf[%d] size: %d, stride: %d\n", i, raw->plane_size_2bits[i], raw->stride_2bits[i]); } } /* set codec buffers */ - MFC_WRITEL(buf_addr, S5P_FIMV_D_SCRATCH_BUFFER_ADDR); - MFC_WRITEL(ctx->scratch_buf_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE); + MFC_WRITEL(buf_addr, MFC_REG_D_SCRATCH_BUFFER_ADDR); + MFC_WRITEL(ctx->scratch_buf_size, MFC_REG_D_SCRATCH_BUFFER_SIZE); buf_addr += ctx->scratch_buf_size; buf_size -= ctx->scratch_buf_size; if (IS_H264_DEC(ctx) || IS_H264_MVC_DEC(ctx) || IS_HEVC_DEC(ctx) || IS_BPG_DEC(ctx)) - MFC_WRITEL(ctx->mv_size, S5P_FIMV_D_MV_BUFFER_SIZE); + MFC_WRITEL(ctx->mv_size, MFC_REG_D_MV_BUFFER_SIZE); if (IS_VP9_DEC(ctx)){ - MFC_WRITEL(buf_addr, S5P_FIMV_D_STATIC_BUFFER_ADDR); - MFC_WRITEL(DEC_STATIC_BUFFER_SIZE, S5P_FIMV_D_STATIC_BUFFER_SIZE); + MFC_WRITEL(buf_addr, MFC_REG_D_STATIC_BUFFER_ADDR); + MFC_WRITEL(DEC_STATIC_BUFFER_SIZE, MFC_REG_D_STATIC_BUFFER_SIZE); buf_addr += DEC_STATIC_BUFFER_SIZE; buf_size -= DEC_STATIC_BUFFER_SIZE; } @@ -152,38 +152,38 @@ int s5p_mfc_set_dec_codec_buffers(struct s5p_mfc_ctx *ctx) if (IS_MPEG4_DEC(ctx) && dec->loop_filter_mpeg4) { mfc_debug(2, "Add DPB for loop filter of MPEG4\n"); for (i = 0; i < NUM_MPEG4_LF_BUF; i++) { - MFC_WRITEL(buf_addr, S5P_FIMV_D_POST_FILTER_LUMA_DPB0 + (4 * i)); + MFC_WRITEL(buf_addr, MFC_REG_D_POST_FILTER_LUMA_DPB0 + (4 * i)); buf_addr += ctx->loopfilter_luma_size; buf_size -= ctx->loopfilter_luma_size; - MFC_WRITEL(buf_addr, S5P_FIMV_D_POST_FILTER_CHROMA_DPB0 + (4 * i)); + MFC_WRITEL(buf_addr, MFC_REG_D_POST_FILTER_CHROMA_DPB0 + (4 * i)); buf_addr += ctx->loopfilter_chroma_size; buf_size -= ctx->loopfilter_chroma_size; } - reg |= ((dec->loop_filter_mpeg4 & S5P_FIMV_D_INIT_BUF_OPT_LF_CTRL_MASK) - << S5P_FIMV_D_INIT_BUF_OPT_LF_CTRL_SHIFT); + reg |= ((dec->loop_filter_mpeg4 & MFC_REG_D_INIT_BUF_OPT_LF_CTRL_MASK) + << MFC_REG_D_INIT_BUF_OPT_LF_CTRL_SHIFT); } - reg |= (0x1 << S5P_FIMV_D_INIT_BUF_OPT_DYNAMIC_DPB_SET_SHIFT); + reg |= (0x1 << MFC_REG_D_INIT_BUF_OPT_DYNAMIC_DPB_SET_SHIFT); if (CODEC_NOT_CODED(ctx)) { - reg |= (0x1 << S5P_FIMV_D_INIT_BUF_OPT_COPY_NOT_CODED_SHIFT); + reg |= (0x1 << MFC_REG_D_INIT_BUF_OPT_COPY_NOT_CODED_SHIFT); mfc_debug(2, "Notcoded frame copy mode start\n"); } /* Enable 10bit Dithering */ if (ctx->is_10bit) { - reg |= (0x1 << S5P_FIMV_D_INIT_BUF_OPT_DITHERING_EN_SHIFT); + reg |= (0x1 << MFC_REG_D_INIT_BUF_OPT_DITHERING_EN_SHIFT); /* 64byte align, It is vaid only for VP9 */ - reg |= (0x1 << S5P_FIMV_D_INIT_BUF_OPT_STRIDE_SIZE_ALIGN); + reg |= (0x1 << MFC_REG_D_INIT_BUF_OPT_STRIDE_SIZE_ALIGN); } else { /* 16byte align, It is vaid only for VP9 */ - reg &= ~(0x1 << S5P_FIMV_D_INIT_BUF_OPT_STRIDE_SIZE_ALIGN); + reg &= ~(0x1 << MFC_REG_D_INIT_BUF_OPT_STRIDE_SIZE_ALIGN); } - MFC_WRITEL(reg, S5P_FIMV_D_INIT_BUFFER_OPTIONS); + MFC_WRITEL(reg, MFC_REG_D_INIT_BUFFER_OPTIONS); frame_size_mv = ctx->mv_size; - MFC_WRITEL(dec->mv_count, S5P_FIMV_D_NUM_MV); + MFC_WRITEL(dec->mv_count, MFC_REG_D_NUM_MV); if (IS_H264_DEC(ctx) || IS_H264_MVC_DEC(ctx) || IS_HEVC_DEC(ctx) || IS_BPG_DEC(ctx)) { for (i = 0; i < dec->mv_count; i++) { /* To test alignment */ @@ -192,7 +192,7 @@ int s5p_mfc_set_dec_codec_buffers(struct s5p_mfc_ctx *ctx) align_gap = buf_addr - align_gap; buf_size -= align_gap; - MFC_WRITEL(buf_addr, S5P_FIMV_D_MV_BUFFER0 + i * 4); + MFC_WRITEL(buf_addr, MFC_REG_D_MV_BUFFER0 + i * 4); buf_addr += frame_size_mv; buf_size -= frame_size_mv; } @@ -208,10 +208,10 @@ int s5p_mfc_set_dec_codec_buffers(struct s5p_mfc_ctx *ctx) } /* Set encoding ref & codec buffer */ -int s5p_mfc_set_enc_codec_buffers(struct s5p_mfc_ctx *ctx) +int mfc_set_enc_codec_buffers(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_enc *enc = ctx->enc_priv; + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; dma_addr_t buf_addr; int buf_size; int i; @@ -224,31 +224,31 @@ int s5p_mfc_set_enc_codec_buffers(struct s5p_mfc_ctx *ctx) mfc_debug(2, "[MEMINFO] codec buf 0x%llx, size: %d\n", buf_addr, buf_size); mfc_debug(2, "DPB COUNT: %d\n", ctx->dpb_count); - MFC_WRITEL(buf_addr, S5P_FIMV_E_SCRATCH_BUFFER_ADDR); - MFC_WRITEL(ctx->scratch_buf_size, S5P_FIMV_E_SCRATCH_BUFFER_SIZE); + MFC_WRITEL(buf_addr, MFC_REG_E_SCRATCH_BUFFER_ADDR); + MFC_WRITEL(ctx->scratch_buf_size, MFC_REG_E_SCRATCH_BUFFER_SIZE); buf_addr += ctx->scratch_buf_size; buf_size -= ctx->scratch_buf_size; /* start address of per buffer is aligned */ for (i = 0; i < ctx->dpb_count; i++) { - MFC_WRITEL(buf_addr, S5P_FIMV_E_LUMA_DPB + (4 * i)); + MFC_WRITEL(buf_addr, MFC_REG_E_LUMA_DPB + (4 * i)); buf_addr += enc->luma_dpb_size; buf_size -= enc->luma_dpb_size; } for (i = 0; i < ctx->dpb_count; i++) { - MFC_WRITEL(buf_addr, S5P_FIMV_E_CHROMA_DPB + (4 * i)); + MFC_WRITEL(buf_addr, MFC_REG_E_CHROMA_DPB + (4 * i)); buf_addr += enc->chroma_dpb_size; buf_size -= enc->chroma_dpb_size; } for (i = 0; i < ctx->dpb_count; i++) { - MFC_WRITEL(buf_addr, S5P_FIMV_E_ME_BUFFER + (4 * i)); + MFC_WRITEL(buf_addr, MFC_REG_E_ME_BUFFER + (4 * i)); buf_addr += enc->me_buffer_size; buf_size -= enc->me_buffer_size; } - MFC_WRITEL(buf_addr, S5P_FIMV_E_TMV_BUFFER0); + MFC_WRITEL(buf_addr, MFC_REG_E_TMV_BUFFER0); buf_addr += enc->tmv_buffer_size >> 1; - MFC_WRITEL(buf_addr, S5P_FIMV_E_TMV_BUFFER1); + MFC_WRITEL(buf_addr, MFC_REG_E_TMV_BUFFER1); buf_addr += enc->tmv_buffer_size >> 1; buf_size -= enc->tmv_buffer_size; @@ -264,11 +264,11 @@ int s5p_mfc_set_enc_codec_buffers(struct s5p_mfc_ctx *ctx) } /* Set registers for decoding stream buffer */ -int s5p_mfc_set_dec_stream_buffer(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *mfc_buf, +int mfc_set_dec_stream_buffer(struct mfc_ctx *ctx, struct mfc_buf *mfc_buf, unsigned int start_num_byte, unsigned int strm_size) { - struct s5p_mfc_dev *dev; - struct s5p_mfc_dec *dec; + struct mfc_dev *dev; + struct mfc_dec *dec; unsigned int cpb_buf_size; dma_addr_t addr; int index = -1; @@ -312,10 +312,10 @@ int s5p_mfc_set_dec_stream_buffer(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *m if (strm_size == 0) mfc_info_ctx("stream size is 0\n"); - MFC_WRITEL(strm_size, S5P_FIMV_D_STREAM_DATA_SIZE); - MFC_WRITEL(addr, S5P_FIMV_D_CPB_BUFFER_ADDR); - MFC_WRITEL(cpb_buf_size, S5P_FIMV_D_CPB_BUFFER_SIZE); - MFC_WRITEL(start_num_byte, S5P_FIMV_D_CPB_BUFFER_OFFSET); + MFC_WRITEL(strm_size, MFC_REG_D_STREAM_DATA_SIZE); + MFC_WRITEL(addr, MFC_REG_D_CPB_BUFFER_ADDR); + MFC_WRITEL(cpb_buf_size, MFC_REG_D_CPB_BUFFER_SIZE); + MFC_WRITEL(start_num_byte, MFC_REG_D_CPB_BUFFER_OFFSET); if (mfc_buf) MFC_TRACE_CTX("Set src[%d] fd: %d, %#llx\n", @@ -325,10 +325,10 @@ int s5p_mfc_set_dec_stream_buffer(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *m return 0; } -void s5p_mfc_set_enc_frame_buffer(struct s5p_mfc_ctx *ctx, - struct s5p_mfc_buf *mfc_buf, int num_planes) +void mfc_set_enc_frame_buffer(struct mfc_ctx *ctx, + struct mfc_buf *mfc_buf, int num_planes) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; dma_addr_t addr[3] = { 0, 0, 0 }; dma_addr_t addr_2bit[2] = { 0, 0 }; int index, i; @@ -356,7 +356,7 @@ void s5p_mfc_set_enc_frame_buffer(struct s5p_mfc_ctx *ctx, buffer_set: for (i = 0; i < num_planes; i++) - MFC_WRITEL(addr[i], S5P_FIMV_E_SOURCE_FIRST_ADDR + (i * 4)); + MFC_WRITEL(addr[i], MFC_REG_E_SOURCE_FIRST_ADDR + (i * 4)); if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M_S10B || ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV21M_S10B) { @@ -364,7 +364,7 @@ buffer_set: addr_2bit[1] = addr[1] + NV12N_10B_CBCR_8B_SIZE(ctx->img_width, ctx->img_height); for (i = 0; i < num_planes; i++) { - MFC_WRITEL(addr_2bit[i], S5P_FIMV_E_SOURCE_FIRST_2BIT_ADDR + (i * 4)); + MFC_WRITEL(addr_2bit[i], MFC_REG_E_SOURCE_FIRST_2BIT_ADDR + (i * 4)); mfc_debug(2, "[BUFINFO][10BIT] ctx[%d] set src 2bit addr[%d]: 0x%08llx\n", ctx->num, i, addr_2bit[i]); } @@ -374,7 +374,7 @@ buffer_set: addr_2bit[1] = addr[1] + NV16M_CBCR_SIZE(ctx->img_width, ctx->img_height); for (i = 0; i < num_planes; i++) { - MFC_WRITEL(addr_2bit[i], S5P_FIMV_E_SOURCE_FIRST_2BIT_ADDR + (i * 4)); + MFC_WRITEL(addr_2bit[i], MFC_REG_E_SOURCE_FIRST_2BIT_ADDR + (i * 4)); mfc_debug(2, "[BUFINFO][10BIT] ctx[%d] set src 2bit addr[%d]: 0x%08llx\n", ctx->num, i, addr_2bit[i]); } @@ -382,10 +382,10 @@ buffer_set: } /* Set registers for encoding stream buffer */ -int s5p_mfc_set_enc_stream_buffer(struct s5p_mfc_ctx *ctx, - struct s5p_mfc_buf *mfc_buf) +int mfc_set_enc_stream_buffer(struct mfc_ctx *ctx, + struct mfc_buf *mfc_buf) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; dma_addr_t addr; unsigned int size, offset, index; @@ -395,9 +395,9 @@ int s5p_mfc_set_enc_stream_buffer(struct s5p_mfc_ctx *ctx, size = (unsigned int)vb2_plane_size(&mfc_buf->vb.vb2_buf, 0); size = ALIGN(size, 512); - MFC_WRITEL(addr, S5P_FIMV_E_STREAM_BUFFER_ADDR); /* 16B align */ - MFC_WRITEL(size, S5P_FIMV_E_STREAM_BUFFER_SIZE); - MFC_WRITEL(offset, S5P_FIMV_E_STREAM_BUFFER_OFFSET); + MFC_WRITEL(addr, MFC_REG_E_STREAM_BUFFER_ADDR); /* 16B align */ + MFC_WRITEL(size, MFC_REG_E_STREAM_BUFFER_SIZE); + MFC_WRITEL(offset, MFC_REG_E_STREAM_BUFFER_OFFSET); mfc_debug(2, "[BUFINFO] ctx[%d] set dst index: %d, addr: 0x%08llx\n", ctx->num, index, addr); @@ -406,43 +406,43 @@ int s5p_mfc_set_enc_stream_buffer(struct s5p_mfc_ctx *ctx, return 0; } -void s5p_mfc_get_enc_frame_buffer(struct s5p_mfc_ctx *ctx, +void mfc_get_enc_frame_buffer(struct mfc_ctx *ctx, dma_addr_t addr[], int num_planes) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; unsigned long enc_recon_y_addr, enc_recon_c_addr; int i, addr_offset; - addr_offset = S5P_FIMV_E_ENCODED_SOURCE_FIRST_ADDR; + addr_offset = MFC_REG_E_ENCODED_SOURCE_FIRST_ADDR; for (i = 0; i < num_planes; i++) addr[i] = MFC_READL(addr_offset + (i * 4)); - enc_recon_y_addr = MFC_READL(S5P_FIMV_E_RECON_LUMA_DPB_ADDR); - enc_recon_c_addr = MFC_READL(S5P_FIMV_E_RECON_CHROMA_DPB_ADDR); + enc_recon_y_addr = MFC_READL(MFC_REG_E_RECON_LUMA_DPB_ADDR); + enc_recon_c_addr = MFC_READL(MFC_REG_E_RECON_CHROMA_DPB_ADDR); mfc_debug(2, "[MEMINFO] recon y: 0x%08lx c: 0x%08lx\n", enc_recon_y_addr, enc_recon_c_addr); } -void s5p_mfc_set_enc_stride(struct s5p_mfc_ctx *ctx) +void mfc_set_enc_stride(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; int i; for (i = 0; i < ctx->raw_buf.num_planes; i++) { MFC_WRITEL(ctx->raw_buf.stride[i], - S5P_FIMV_E_SOURCE_FIRST_STRIDE + (i * 4)); + MFC_REG_E_SOURCE_FIRST_STRIDE + (i * 4)); mfc_debug(2, "[FRAME] enc src plane[%d] stride: %d\n", i, ctx->raw_buf.stride[i]); } } -int s5p_mfc_set_dynamic_dpb(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *dst_mb) +int mfc_set_dynamic_dpb(struct mfc_ctx *ctx, struct mfc_buf *dst_mb) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_dec *dec = ctx->dec_priv; - struct s5p_mfc_raw_info *raw = &ctx->raw_buf; + struct mfc_dev *dev = ctx->dev; + struct mfc_dec *dec = ctx->dec_priv; + struct mfc_raw_info *raw = &ctx->raw_buf; int dst_index; int i; @@ -466,16 +466,16 @@ int s5p_mfc_set_dynamic_dpb(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *dst_mb) } /* decoder dst buffer CFW PROT */ - s5p_mfc_protect_dpb(ctx, dst_mb); + mfc_protect_dpb(ctx, dst_mb); for (i = 0; i < raw->num_planes; i++) { MFC_WRITEL(raw->plane_size[i], - S5P_FIMV_D_FIRST_PLANE_DPB_SIZE + i * 4); + MFC_REG_D_FIRST_PLANE_DPB_SIZE + i * 4); MFC_WRITEL(dst_mb->addr[0][i], - S5P_FIMV_D_FIRST_PLANE_DPB0 + (i * 0x100 + dst_index * 4)); + MFC_REG_D_FIRST_PLANE_DPB0 + (i * 0x100 + dst_index * 4)); if (ctx->is_10bit) MFC_WRITEL(raw->plane_size_2bits[i], - S5P_FIMV_D_FIRST_PLANE_2BIT_DPB_SIZE + (i * 4)); + MFC_REG_D_FIRST_PLANE_2BIT_DPB_SIZE + (i * 4)); mfc_debug(2, "[BUFINFO][DPB] ctx[%d] set dst index: %d, addr[%d]: 0x%08llx\n", ctx->num, dst_index, i, dst_mb->addr[0][i]); } @@ -487,7 +487,7 @@ int s5p_mfc_set_dynamic_dpb(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *dst_mb) return 0; } -void s5p_mfc_set_pixel_format(struct s5p_mfc_dev *dev, unsigned int format) +void mfc_set_pixel_format(struct mfc_dev *dev, unsigned int format) { unsigned int reg = 0; unsigned int pix_val, mem_type_10bit = 0; @@ -541,7 +541,7 @@ void s5p_mfc_set_pixel_format(struct s5p_mfc_dev *dev, unsigned int format) } reg |= pix_val; reg |= (mem_type_10bit << 4); - MFC_WRITEL(reg, S5P_FIMV_PIXEL_FORMAT); + MFC_WRITEL(reg, MFC_REG_PIXEL_FORMAT); mfc_debug(2, "[FRAME] pixel format: %d, mem_type_10bit for 10bit: %d (reg: %#x)\n", pix_val, mem_type_10bit, reg); } diff --git a/drivers/media/platform/exynos/mfc/mfc_reg.h b/drivers/media/platform/exynos/mfc/mfc_reg.h index 3e8be853f7d7..757b3d11e00e 100644 --- a/drivers/media/platform/exynos/mfc/mfc_reg.h +++ b/drivers/media/platform/exynos/mfc/mfc_reg.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_reg.h + * drivers/media/platform/exynos/mfc/mfc_reg.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -29,191 +29,191 @@ #define MMCACHE_WRITEL(data, offset) writel((data), dev->mmcache.base + (offset)) /* version */ -#define s5p_mfc_get_fimv_info() ((MFC_READL(S5P_FIMV_FW_VERSION) \ - >> S5P_FIMV_FW_VER_INFO_SHFT) \ - & S5P_FIMV_FW_VER_INFO_MASK) -#define s5p_mfc_get_fw_ver_year() ((MFC_READL(S5P_FIMV_FW_VERSION) \ - >> S5P_FIMV_FW_VER_YEAR_SHFT) \ - & S5P_FIMV_FW_VER_YEAR_MASK) -#define s5p_mfc_get_fw_ver_month() ((MFC_READL(S5P_FIMV_FW_VERSION) \ - >> S5P_FIMV_FW_VER_MONTH_SHFT) \ - & S5P_FIMV_FW_VER_MONTH_MASK) -#define s5p_mfc_get_fw_ver_date() ((MFC_READL(S5P_FIMV_FW_VERSION) \ - >> S5P_FIMV_FW_VER_DATE_SHFT) \ - & S5P_FIMV_FW_VER_DATE_MASK) -#define s5p_mfc_get_fw_ver_all() ((MFC_READL(S5P_FIMV_FW_VERSION) \ - >> S5P_FIMV_FW_VER_ALL_SHFT) \ - & S5P_FIMV_FW_VER_ALL_MASK) -#define s5p_mfc_get_mfc_version() ((MFC_READL(S5P_FIMV_MFC_VERSION) \ - >> S5P_FIMV_MFC_VER_SHFT) \ - & S5P_FIMV_MFC_VER_MASK) +#define mfc_get_fimv_info() ((MFC_READL(MFC_REG_FW_VERSION) \ + >> MFC_REG_FW_VER_INFO_SHFT) \ + & MFC_REG_FW_VER_INFO_MASK) +#define mfc_get_fw_ver_year() ((MFC_READL(MFC_REG_FW_VERSION) \ + >> MFC_REG_FW_VER_YEAR_SHFT) \ + & MFC_REG_FW_VER_YEAR_MASK) +#define mfc_get_fw_ver_month() ((MFC_READL(MFC_REG_FW_VERSION) \ + >> MFC_REG_FW_VER_MONTH_SHFT) \ + & MFC_REG_FW_VER_MONTH_MASK) +#define mfc_get_fw_ver_date() ((MFC_READL(MFC_REG_FW_VERSION) \ + >> MFC_REG_FW_VER_DATE_SHFT) \ + & MFC_REG_FW_VER_DATE_MASK) +#define mfc_get_fw_ver_all() ((MFC_READL(MFC_REG_FW_VERSION) \ + >> MFC_REG_FW_VER_ALL_SHFT) \ + & MFC_REG_FW_VER_ALL_MASK) +#define mfc_get_mfc_version() ((MFC_READL(MFC_REG_MFC_VERSION) \ + >> MFC_REG_MFC_VER_SHFT) \ + & MFC_REG_MFC_VER_MASK) /* decoding & display information */ -#define s5p_mfc_get_dec_status() (MFC_READL(S5P_FIMV_D_DECODED_STATUS) \ - & S5P_FIMV_DEC_STATUS_DECODED_STATUS_MASK) -#define s5p_mfc_get_disp_status() (MFC_READL(S5P_FIMV_D_DISPLAY_STATUS) \ - & S5P_FIMV_DISP_STATUS_DISPLAY_STATUS_MASK) -#define s5p_mfc_get_res_change() ((MFC_READL(S5P_FIMV_D_DISPLAY_STATUS) \ - >> S5P_FIMV_DISP_STATUS_RES_CHANGE_SHIFT) \ - & S5P_FIMV_DISP_STATUS_RES_CHANGE_MASK) -#define s5p_mfc_get_black_bar_detection() ((MFC_READL(S5P_FIMV_D_DISPLAY_STATUS) \ - >> S5P_FIMV_DISP_STATUS_BLACK_BAR_DETECT_SHIFT) \ - & S5P_FIMV_DISP_STATUS_BLACK_BAR_DETECT_MASK) -#define s5p_mfc_get_dpb_change() ((MFC_READL(S5P_FIMV_D_DISPLAY_STATUS) \ - >> S5P_FIMV_DISP_STATUS_NEED_DPB_CHANGE_SHIFT) \ - & S5P_FIMV_DISP_STATUS_NEED_DPB_CHANGE_MASK) -#define s5p_mfc_get_scratch_change() ((MFC_READL(S5P_FIMV_D_DISPLAY_STATUS) \ - >> S5P_FIMV_DISP_STATUS_NEED_SCRATCH_CHANGE_SHIFT) \ - & S5P_FIMV_DISP_STATUS_NEED_SCRATCH_CHANGE_MASK) -#define s5p_mfc_get_disp_frame_type() (MFC_READL(S5P_FIMV_D_DISPLAY_FRAME_TYPE) \ - & S5P_FIMV_DISPLAY_FRAME_MASK) -#define s5p_mfc_get_dec_frame_type() (MFC_READL(S5P_FIMV_D_DECODED_FRAME_TYPE) \ - & S5P_FIMV_DECODED_FRAME_MASK) -#define s5p_mfc_get_interlace_type() ((MFC_READL(S5P_FIMV_D_DISPLAY_FRAME_TYPE) \ - >> S5P_FIMV_DISPLAY_TEMP_INFO_SHIFT) \ - & S5P_FIMV_DISPLAY_TEMP_INFO_MASK) -#define s5p_mfc_is_interlace_picture() ((MFC_READL(S5P_FIMV_D_DISPLAY_STATUS) \ - >> S5P_FIMV_DISP_STATUS_INTERLACE_SHIFT)\ - & S5P_FIMV_DISP_STATUS_INTERLACE_MASK) -#define s5p_mfc_is_mbaff_picture() ((MFC_READL(S5P_FIMV_D_H264_INFO) \ - >> S5P_FIMV_D_H264_INFO_MBAFF_FRAME_FLAG_SHIFT)\ - & S5P_FIMV_D_H264_INFO_MBAFF_FRAME_FLAG_MASK) -#define s5p_mfc_get_img_width() MFC_READL(S5P_FIMV_D_DISPLAY_FRAME_WIDTH) -#define s5p_mfc_get_img_height() MFC_READL(S5P_FIMV_D_DISPLAY_FRAME_HEIGHT) -#define s5p_mfc_get_disp_y_addr() MFC_READL(S5P_FIMV_D_DISPLAY_LUMA_ADDR) -#define s5p_mfc_get_dec_y_addr() MFC_READL(S5P_FIMV_D_DECODED_LUMA_ADDR) +#define mfc_get_dec_status() (MFC_READL(MFC_REG_D_DECODED_STATUS) \ + & MFC_REG_DEC_STATUS_DECODED_STATUS_MASK) +#define mfc_get_disp_status() (MFC_READL(MFC_REG_D_DISPLAY_STATUS) \ + & MFC_REG_DISP_STATUS_DISPLAY_STATUS_MASK) +#define mfc_get_res_change() ((MFC_READL(MFC_REG_D_DISPLAY_STATUS) \ + >> MFC_REG_DISP_STATUS_RES_CHANGE_SHIFT) \ + & MFC_REG_DISP_STATUS_RES_CHANGE_MASK) +#define mfc_get_black_bar_detection() ((MFC_READL(MFC_REG_D_DISPLAY_STATUS) \ + >> MFC_REG_DISP_STATUS_BLACK_BAR_DETECT_SHIFT) \ + & MFC_REG_DISP_STATUS_BLACK_BAR_DETECT_MASK) +#define mfc_get_dpb_change() ((MFC_READL(MFC_REG_D_DISPLAY_STATUS) \ + >> MFC_REG_DISP_STATUS_NEED_DPB_CHANGE_SHIFT) \ + & MFC_REG_DISP_STATUS_NEED_DPB_CHANGE_MASK) +#define mfc_get_scratch_change() ((MFC_READL(MFC_REG_D_DISPLAY_STATUS) \ + >> MFC_REG_DISP_STATUS_NEED_SCRATCH_CHANGE_SHIFT) \ + & MFC_REG_DISP_STATUS_NEED_SCRATCH_CHANGE_MASK) +#define mfc_get_disp_frame_type() (MFC_READL(MFC_REG_D_DISPLAY_FRAME_TYPE) \ + & MFC_REG_DISPLAY_FRAME_MASK) +#define mfc_get_dec_frame_type() (MFC_READL(MFC_REG_D_DECODED_FRAME_TYPE) \ + & MFC_REG_DECODED_FRAME_MASK) +#define mfc_get_interlace_type() ((MFC_READL(MFC_REG_D_DISPLAY_FRAME_TYPE) \ + >> MFC_REG_DISPLAY_TEMP_INFO_SHIFT) \ + & MFC_REG_DISPLAY_TEMP_INFO_MASK) +#define mfc_is_interlace_picture() ((MFC_READL(MFC_REG_D_DISPLAY_STATUS) \ + >> MFC_REG_DISP_STATUS_INTERLACE_SHIFT)\ + & MFC_REG_DISP_STATUS_INTERLACE_MASK) +#define mfc_is_mbaff_picture() ((MFC_READL(MFC_REG_D_H264_INFO) \ + >> MFC_REG_D_H264_INFO_MBAFF_FRAME_FLAG_SHIFT)\ + & MFC_REG_D_H264_INFO_MBAFF_FRAME_FLAG_MASK) +#define mfc_get_img_width() MFC_READL(MFC_REG_D_DISPLAY_FRAME_WIDTH) +#define mfc_get_img_height() MFC_READL(MFC_REG_D_DISPLAY_FRAME_HEIGHT) +#define mfc_get_disp_y_addr() MFC_READL(MFC_REG_D_DISPLAY_LUMA_ADDR) +#define mfc_get_dec_y_addr() MFC_READL(MFC_REG_D_DECODED_LUMA_ADDR) /* kind of interrupt */ -#define s5p_mfc_get_int_err() MFC_READL(S5P_FIMV_ERROR_CODE) -#define s5p_mfc_get_err(x) (((x) >> S5P_FIMV_ERR_STATUS_SHIFT) \ - & S5P_FIMV_ERR_STATUS_MASK) -#define s5p_mfc_get_warn(x) (((x) >> S5P_FIMV_WARN_STATUS_SHIFT) \ - & S5P_FIMV_WARN_STATUS_MASK) +#define mfc_get_int_err() MFC_READL(MFC_REG_ERROR_CODE) +#define mfc_get_err(x) (((x) >> MFC_REG_ERR_STATUS_SHIFT) \ + & MFC_REG_ERR_STATUS_MASK) +#define mfc_get_warn(x) (((x) >> MFC_REG_WARN_STATUS_SHIFT) \ + & MFC_REG_WARN_STATUS_MASK) /* additional information */ -#define s5p_mfc_get_consumed_stream() MFC_READL(S5P_FIMV_D_DECODED_NAL_SIZE) -#define s5p_mfc_get_dpb_count() MFC_READL(S5P_FIMV_D_MIN_NUM_DPB) -#define s5p_mfc_get_min_dpb_size(x) MFC_READL(S5P_FIMV_D_MIN_FIRST_PLANE_DPB_SIZE + (x * 4)) -#define s5p_mfc_get_scratch_size() MFC_READL(S5P_FIMV_D_MIN_SCRATCH_BUFFER_SIZE) -#define s5p_mfc_get_mv_count() MFC_READL(S5P_FIMV_D_MIN_NUM_MV) -#define s5p_mfc_get_inst_no() MFC_READL(S5P_FIMV_RET_INSTANCE_ID) -#define s5p_mfc_get_enc_dpb_count() MFC_READL(S5P_FIMV_E_NUM_DPB) -#define s5p_mfc_get_enc_scratch_size() MFC_READL(S5P_FIMV_E_MIN_SCRATCH_BUFFER_SIZE) -#define s5p_mfc_get_enc_strm_size() MFC_READL(S5P_FIMV_E_STREAM_SIZE) -#define s5p_mfc_get_enc_slice_type() MFC_READL(S5P_FIMV_E_SLICE_TYPE) -#define s5p_mfc_get_enc_pic_count() MFC_READL(S5P_FIMV_E_PICTURE_COUNT) -#define s5p_mfc_get_sei_avail() MFC_READL(S5P_FIMV_D_SEI_AVAIL) -#define s5p_mfc_get_sei_content_light() MFC_READL(S5P_FIMV_D_CONTENT_LIGHT_LEVEL_INFO_SEI) -#define s5p_mfc_get_sei_mastering0() MFC_READL(S5P_FIMV_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_0) -#define s5p_mfc_get_sei_mastering1() MFC_READL(S5P_FIMV_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_1) -#define s5p_mfc_get_sei_mastering2() MFC_READL(S5P_FIMV_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_2) -#define s5p_mfc_get_sei_mastering3() MFC_READL(S5P_FIMV_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_3) -#define s5p_mfc_get_sei_mastering4() MFC_READL(S5P_FIMV_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_4) -#define s5p_mfc_get_sei_mastering5() MFC_READL(S5P_FIMV_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_5) -#define s5p_mfc_get_sei_avail_frame_pack() (MFC_READL(S5P_FIMV_D_SEI_AVAIL) \ - & S5P_FIMV_D_SEI_AVAIL_FRAME_PACK_MASK) -#define s5p_mfc_get_sei_avail_content_light() ((MFC_READL(S5P_FIMV_D_SEI_AVAIL) \ - >> S5P_FIMV_D_SEI_AVAIL_CONTENT_LIGHT_SHIFT) \ - & S5P_FIMV_D_SEI_AVAIL_CONTENT_LIGHT_MASK) -#define s5p_mfc_get_sei_avail_mastering_display() ((MFC_READL(S5P_FIMV_D_SEI_AVAIL) \ - >> S5P_FIMV_D_SEI_AVAIL_MASTERING_DISPLAY_SHIFT) \ - & S5P_FIMV_D_SEI_AVAIL_MASTERING_DISPLAY_MASK) -#define s5p_mfc_get_video_signal_type() ((MFC_READL(S5P_FIMV_D_VIDEO_SIGNAL_TYPE) \ - >> S5P_FIMV_D_VIDEO_SIGNAL_TYPE_FLAG_SHIFT) \ - & S5P_FIMV_D_VIDEO_SIGNAL_TYPE_FLAG_MASK) -#define s5p_mfc_get_colour_description() ((MFC_READL(S5P_FIMV_D_VIDEO_SIGNAL_TYPE) \ - >> S5P_FIMV_D_COLOUR_DESCRIPTION_FLAG_SHIFT) \ - & S5P_FIMV_D_COLOUR_DESCRIPTION_FLAG_MASK) -#define s5p_mfc_get_black_bar_pos_x() ((MFC_READL(S5P_FIMV_D_BLACK_BAR_START_POS) \ - >> S5P_FIMV_D_BLACK_BAR_START_X_SHIFT) \ - & S5P_FIMV_D_BLACK_BAR_START_X_MASK) -#define s5p_mfc_get_black_bar_pos_y() ((MFC_READL(S5P_FIMV_D_BLACK_BAR_START_POS) \ - >> S5P_FIMV_D_BLACK_BAR_START_Y_SHIFT) \ - & S5P_FIMV_D_BLACK_BAR_START_Y_MASK) -#define s5p_mfc_get_black_bar_image_w() ((MFC_READL(S5P_FIMV_D_BLACK_BAR_IMAGE_SIZE) \ - >> S5P_FIMV_D_BLACK_BAR_IMAGE_W_SHIFT) \ - & S5P_FIMV_D_BLACK_BAR_IMAGE_W_MASK) -#define s5p_mfc_get_black_bar_image_h() ((MFC_READL(S5P_FIMV_D_BLACK_BAR_IMAGE_SIZE) \ - >> S5P_FIMV_D_BLACK_BAR_IMAGE_H_SHIFT) \ - & S5P_FIMV_D_BLACK_BAR_IMAGE_H_MASK) -#define s5p_mfc_get_mvc_disp_view_id() (MFC_READL(S5P_FIMV_D_MVC_VIEW_ID) \ - & S5P_FIMV_D_MVC_VIEW_ID_DISP_MASK) -#define s5p_mfc_get_profile() (MFC_READL(S5P_FIMV_D_DECODED_PICTURE_PROFILE) \ - & S5P_FIMV_D_DECODED_PIC_PROFILE_MASK) -#define s5p_mfc_get_luma_bit_depth_minus8() ((MFC_READL(S5P_FIMV_D_DECODED_PICTURE_PROFILE) \ - >> S5P_FIMV_D_BIT_DEPTH_LUMA_MINUS8_SHIFT) \ - & S5P_FIMV_D_BIT_DEPTH_LUMA_MINUS8_MASK) -#define s5p_mfc_get_chroma_bit_depth_minus8() ((MFC_READL(S5P_FIMV_D_DECODED_PICTURE_PROFILE) \ - >> S5P_FIMV_D_BIT_DEPTH_CHROMA_MINUS8_SHIFT) \ - & S5P_FIMV_D_BIT_DEPTH_CHROMA_MINUS8_MASK) -#define s5p_mfc_get_dec_used_flag() MFC_READL(S5P_FIMV_D_USED_DPB_FLAG_LOWER) -#define s5p_mfc_get_enc_nal_done_info() ((MFC_READL(S5P_FIMV_E_NAL_DONE_INFO) & (0x3 << 4)) >> 4) -#define s5p_mfc_get_chroma_format() (MFC_READL(S5P_FIMV_D_CHROMA_FORMAT) \ - & S5P_FIMV_D_CHROMA_FORMAT_MASK) -#define s5p_mfc_get_color_range() ((MFC_READL(S5P_FIMV_D_CHROMA_FORMAT) \ - >> S5P_FIMV_D_COLOR_RANGE_SHIFT) \ - & S5P_FIMV_D_COLOR_RANGE_MASK) -#define s5p_mfc_get_color_space() ((MFC_READL(S5P_FIMV_D_CHROMA_FORMAT) \ - >> S5P_FIMV_D_COLOR_SPACE_SHIFT) \ - & S5P_FIMV_D_COLOR_SPACE_MASK) -#define s5p_mfc_get_num_of_tile() ((MFC_READL(S5P_FIMV_D_DECODED_STATUS) \ - >> S5P_FIMV_DEC_STATUS_NUM_OF_TILE_SHIFT) \ - & S5P_FIMV_DEC_STATUS_NUM_OF_TILE_MASK) +#define mfc_get_consumed_stream() MFC_READL(MFC_REG_D_DECODED_NAL_SIZE) +#define mfc_get_dpb_count() MFC_READL(MFC_REG_D_MIN_NUM_DPB) +#define mfc_get_min_dpb_size(x) MFC_READL(MFC_REG_D_MIN_FIRST_PLANE_DPB_SIZE + (x * 4)) +#define mfc_get_scratch_size() MFC_READL(MFC_REG_D_MIN_SCRATCH_BUFFER_SIZE) +#define mfc_get_mv_count() MFC_READL(MFC_REG_D_MIN_NUM_MV) +#define mfc_get_inst_no() MFC_READL(MFC_REG_RET_INSTANCE_ID) +#define mfc_get_enc_dpb_count() MFC_READL(MFC_REG_E_NUM_DPB) +#define mfc_get_enc_scratch_size() MFC_READL(MFC_REG_E_MIN_SCRATCH_BUFFER_SIZE) +#define mfc_get_enc_strm_size() MFC_READL(MFC_REG_E_STREAM_SIZE) +#define mfc_get_enc_slice_type() MFC_READL(MFC_REG_E_SLICE_TYPE) +#define mfc_get_enc_pic_count() MFC_READL(MFC_REG_E_PICTURE_COUNT) +#define mfc_get_sei_avail() MFC_READL(MFC_REG_D_SEI_AVAIL) +#define mfc_get_sei_content_light() MFC_READL(MFC_REG_D_CONTENT_LIGHT_LEVEL_INFO_SEI) +#define mfc_get_sei_mastering0() MFC_READL(MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_0) +#define mfc_get_sei_mastering1() MFC_READL(MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_1) +#define mfc_get_sei_mastering2() MFC_READL(MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_2) +#define mfc_get_sei_mastering3() MFC_READL(MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_3) +#define mfc_get_sei_mastering4() MFC_READL(MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_4) +#define mfc_get_sei_mastering5() MFC_READL(MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_5) +#define mfc_get_sei_avail_frame_pack() (MFC_READL(MFC_REG_D_SEI_AVAIL) \ + & MFC_REG_D_SEI_AVAIL_FRAME_PACK_MASK) +#define mfc_get_sei_avail_content_light() ((MFC_READL(MFC_REG_D_SEI_AVAIL) \ + >> MFC_REG_D_SEI_AVAIL_CONTENT_LIGHT_SHIFT) \ + & MFC_REG_D_SEI_AVAIL_CONTENT_LIGHT_MASK) +#define mfc_get_sei_avail_mastering_display() ((MFC_READL(MFC_REG_D_SEI_AVAIL) \ + >> MFC_REG_D_SEI_AVAIL_MASTERING_DISPLAY_SHIFT) \ + & MFC_REG_D_SEI_AVAIL_MASTERING_DISPLAY_MASK) +#define mfc_get_video_signal_type() ((MFC_READL(MFC_REG_D_VIDEO_SIGNAL_TYPE) \ + >> MFC_REG_D_VIDEO_SIGNAL_TYPE_FLAG_SHIFT) \ + & MFC_REG_D_VIDEO_SIGNAL_TYPE_FLAG_MASK) +#define mfc_get_colour_description() ((MFC_READL(MFC_REG_D_VIDEO_SIGNAL_TYPE) \ + >> MFC_REG_D_COLOUR_DESCRIPTION_FLAG_SHIFT) \ + & MFC_REG_D_COLOUR_DESCRIPTION_FLAG_MASK) +#define mfc_get_black_bar_pos_x() ((MFC_READL(MFC_REG_D_BLACK_BAR_START_POS) \ + >> MFC_REG_D_BLACK_BAR_START_X_SHIFT) \ + & MFC_REG_D_BLACK_BAR_START_X_MASK) +#define mfc_get_black_bar_pos_y() ((MFC_READL(MFC_REG_D_BLACK_BAR_START_POS) \ + >> MFC_REG_D_BLACK_BAR_START_Y_SHIFT) \ + & MFC_REG_D_BLACK_BAR_START_Y_MASK) +#define mfc_get_black_bar_image_w() ((MFC_READL(MFC_REG_D_BLACK_BAR_IMAGE_SIZE) \ + >> MFC_REG_D_BLACK_BAR_IMAGE_W_SHIFT) \ + & MFC_REG_D_BLACK_BAR_IMAGE_W_MASK) +#define mfc_get_black_bar_image_h() ((MFC_READL(MFC_REG_D_BLACK_BAR_IMAGE_SIZE) \ + >> MFC_REG_D_BLACK_BAR_IMAGE_H_SHIFT) \ + & MFC_REG_D_BLACK_BAR_IMAGE_H_MASK) +#define mfc_get_mvc_disp_view_id() (MFC_READL(MFC_REG_D_MVC_VIEW_ID) \ + & MFC_REG_D_MVC_VIEW_ID_DISP_MASK) +#define mfc_get_profile() (MFC_READL(MFC_REG_D_DECODED_PICTURE_PROFILE) \ + & MFC_REG_D_DECODED_PIC_PROFILE_MASK) +#define mfc_get_luma_bit_depth_minus8() ((MFC_READL(MFC_REG_D_DECODED_PICTURE_PROFILE) \ + >> MFC_REG_D_BIT_DEPTH_LUMA_MINUS8_SHIFT) \ + & MFC_REG_D_BIT_DEPTH_LUMA_MINUS8_MASK) +#define mfc_get_chroma_bit_depth_minus8() ((MFC_READL(MFC_REG_D_DECODED_PICTURE_PROFILE) \ + >> MFC_REG_D_BIT_DEPTH_CHROMA_MINUS8_SHIFT) \ + & MFC_REG_D_BIT_DEPTH_CHROMA_MINUS8_MASK) +#define mfc_get_dec_used_flag() MFC_READL(MFC_REG_D_USED_DPB_FLAG_LOWER) +#define mfc_get_enc_nal_done_info() ((MFC_READL(MFC_REG_E_NAL_DONE_INFO) & (0x3 << 4)) >> 4) +#define mfc_get_chroma_format() (MFC_READL(MFC_REG_D_CHROMA_FORMAT) \ + & MFC_REG_D_CHROMA_FORMAT_MASK) +#define mfc_get_color_range() ((MFC_READL(MFC_REG_D_CHROMA_FORMAT) \ + >> MFC_REG_D_COLOR_RANGE_SHIFT) \ + & MFC_REG_D_COLOR_RANGE_MASK) +#define mfc_get_color_space() ((MFC_READL(MFC_REG_D_CHROMA_FORMAT) \ + >> MFC_REG_D_COLOR_SPACE_SHIFT) \ + & MFC_REG_D_COLOR_SPACE_MASK) +#define mfc_get_num_of_tile() ((MFC_READL(MFC_REG_D_DECODED_STATUS) \ + >> MFC_REG_DEC_STATUS_NUM_OF_TILE_SHIFT) \ + & MFC_REG_DEC_STATUS_NUM_OF_TILE_MASK) /* nal queue information */ -#define s5p_mfc_get_nal_q_input_count() MFC_READL(S5P_FIMV_NAL_QUEUE_INPUT_COUNT) -#define s5p_mfc_get_nal_q_output_count() MFC_READL(S5P_FIMV_NAL_QUEUE_OUTPUT_COUNT) -#define s5p_mfc_get_nal_q_input_exe_count() MFC_READL(S5P_FIMV_NAL_QUEUE_INPUT_EXE_COUNT) -#define s5p_mfc_get_nal_q_info() MFC_READL(S5P_FIMV_NAL_QUEUE_INFO) -#define s5p_mfc_get_nal_q_input_addr() MFC_READL(S5P_FIMV_NAL_QUEUE_INPUT_ADDR) -#define s5p_mfc_get_nal_q_input_size() MFC_READL(S5P_FIMV_NAL_QUEUE_INPUT_SIZE) -#define s5p_mfc_get_nal_q_output_addr() MFC_READL(S5P_FIMV_NAL_QUEUE_OUTPUT_ADDR) -#define s5p_mfc_get_nal_q_output_ize() MFC_READL(S5P_FIMV_NAL_QUEUE_OUTPUT_SIZE) - -static inline void s5p_mfc_reset_nal_queue_registers(struct s5p_mfc_dev *dev) +#define mfc_get_nal_q_input_count() MFC_READL(MFC_REG_NAL_QUEUE_INPUT_COUNT) +#define mfc_get_nal_q_output_count() MFC_READL(MFC_REG_NAL_QUEUE_OUTPUT_COUNT) +#define mfc_get_nal_q_input_exe_count() MFC_READL(MFC_REG_NAL_QUEUE_INPUT_EXE_COUNT) +#define mfc_get_nal_q_info() MFC_READL(MFC_REG_NAL_QUEUE_INFO) +#define mfc_get_nal_q_input_addr() MFC_READL(MFC_REG_NAL_QUEUE_INPUT_ADDR) +#define mfc_get_nal_q_input_size() MFC_READL(MFC_REG_NAL_QUEUE_INPUT_SIZE) +#define mfc_get_nal_q_output_addr() MFC_READL(MFC_REG_NAL_QUEUE_OUTPUT_ADDR) +#define mfc_get_nal_q_output_ize() MFC_READL(MFC_REG_NAL_QUEUE_OUTPUT_SIZE) + +static inline void mfc_reset_nal_queue_registers(struct mfc_dev *dev) { - MFC_WRITEL(0x0, S5P_FIMV_NAL_QUEUE_INPUT_COUNT); - MFC_WRITEL(0x0, S5P_FIMV_NAL_QUEUE_OUTPUT_COUNT); - MFC_WRITEL(0x0, S5P_FIMV_NAL_QUEUE_INPUT_EXE_COUNT); - MFC_WRITEL(0x0, S5P_FIMV_NAL_QUEUE_INFO); + MFC_WRITEL(0x0, MFC_REG_NAL_QUEUE_INPUT_COUNT); + MFC_WRITEL(0x0, MFC_REG_NAL_QUEUE_OUTPUT_COUNT); + MFC_WRITEL(0x0, MFC_REG_NAL_QUEUE_INPUT_EXE_COUNT); + MFC_WRITEL(0x0, MFC_REG_NAL_QUEUE_INFO); } -static inline void s5p_mfc_update_nal_queue_input(struct s5p_mfc_dev *dev, +static inline void mfc_update_nal_queue_input(struct mfc_dev *dev, dma_addr_t addr, unsigned int size) { - MFC_WRITEL(addr, S5P_FIMV_NAL_QUEUE_INPUT_ADDR); - MFC_WRITEL(size, S5P_FIMV_NAL_QUEUE_INPUT_SIZE); + MFC_WRITEL(addr, MFC_REG_NAL_QUEUE_INPUT_ADDR); + MFC_WRITEL(size, MFC_REG_NAL_QUEUE_INPUT_SIZE); } -static inline void s5p_mfc_update_nal_queue_output(struct s5p_mfc_dev *dev, +static inline void mfc_update_nal_queue_output(struct mfc_dev *dev, dma_addr_t addr, unsigned int size) { - MFC_WRITEL(addr, S5P_FIMV_NAL_QUEUE_OUTPUT_ADDR); - MFC_WRITEL(size, S5P_FIMV_NAL_QUEUE_OUTPUT_SIZE); + MFC_WRITEL(addr, MFC_REG_NAL_QUEUE_OUTPUT_ADDR); + MFC_WRITEL(size, MFC_REG_NAL_QUEUE_OUTPUT_SIZE); } -static inline void s5p_mfc_update_nal_queue_input_count(struct s5p_mfc_dev *dev, +static inline void mfc_update_nal_queue_input_count(struct mfc_dev *dev, unsigned int input_count) { - MFC_WRITEL(input_count, S5P_FIMV_NAL_QUEUE_INPUT_COUNT); + MFC_WRITEL(input_count, MFC_REG_NAL_QUEUE_INPUT_COUNT); } -static inline void s5p_mfc_dec_store_crop_info(struct s5p_mfc_ctx *ctx) +static inline void mfc_dec_store_crop_info(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_dec *dec = ctx->dec_priv; + struct mfc_dev *dev = ctx->dev; + struct mfc_dec *dec = ctx->dec_priv; u32 left, right, top, bottom; - left = MFC_READL(S5P_FIMV_D_DISPLAY_CROP_INFO1); - right = left >> S5P_FIMV_D_SHARED_CROP_RIGHT_SHIFT; - left = left & S5P_FIMV_D_SHARED_CROP_LEFT_MASK; - top = MFC_READL(S5P_FIMV_D_DISPLAY_CROP_INFO2); - bottom = top >> S5P_FIMV_D_SHARED_CROP_BOTTOM_SHIFT; - top = top & S5P_FIMV_D_SHARED_CROP_TOP_MASK; + left = MFC_READL(MFC_REG_D_DISPLAY_CROP_INFO1); + right = left >> MFC_REG_D_SHARED_CROP_RIGHT_SHIFT; + left = left & MFC_REG_D_SHARED_CROP_LEFT_MASK; + top = MFC_READL(MFC_REG_D_DISPLAY_CROP_INFO2); + bottom = top >> MFC_REG_D_SHARED_CROP_BOTTOM_SHIFT; + top = top & MFC_REG_D_SHARED_CROP_TOP_MASK; dec->cr_left = left; dec->cr_right = right; @@ -221,51 +221,51 @@ static inline void s5p_mfc_dec_store_crop_info(struct s5p_mfc_ctx *ctx) dec->cr_bot = bottom; } -static inline void s5p_mfc_clear_enc_res_change(struct s5p_mfc_dev *dev) +static inline void mfc_clear_enc_res_change(struct mfc_dev *dev) { unsigned int reg = 0; - reg = MFC_READL(S5P_FIMV_E_PARAM_CHANGE); + reg = MFC_READL(MFC_REG_E_PARAM_CHANGE); reg &= ~(0x7 << 6); - MFC_WRITEL(reg, S5P_FIMV_E_PARAM_CHANGE); + MFC_WRITEL(reg, MFC_REG_E_PARAM_CHANGE); } -static inline void s5p_mfc_clear_roi_enable(struct s5p_mfc_dev *dev) +static inline void mfc_clear_roi_enable(struct mfc_dev *dev) { unsigned int reg = 0; - reg = MFC_READL(S5P_FIMV_E_RC_ROI_CTRL); + reg = MFC_READL(MFC_REG_E_RC_ROI_CTRL); reg &= ~(0x1); - MFC_WRITEL(reg, S5P_FIMV_E_RC_ROI_CTRL); + MFC_WRITEL(reg, MFC_REG_E_RC_ROI_CTRL); } -void s5p_mfc_dbg_enable(struct s5p_mfc_dev *dev); -void s5p_mfc_dbg_disable(struct s5p_mfc_dev *dev); -void s5p_mfc_dbg_set_addr(struct s5p_mfc_dev *dev); +void mfc_dbg_enable(struct mfc_dev *dev); +void mfc_dbg_disable(struct mfc_dev *dev); +void mfc_dbg_set_addr(struct mfc_dev *dev); -void s5p_mfc_otf_set_frame_addr(struct s5p_mfc_ctx *ctx, int num_planes); -void s5p_mfc_otf_set_stream_size(struct s5p_mfc_ctx *ctx, unsigned int size); -void s5p_mfc_otf_set_hwfc_index(struct s5p_mfc_ctx *ctx, int job_id); +void mfc_otf_set_frame_addr(struct mfc_ctx *ctx, int num_planes); +void mfc_otf_set_stream_size(struct mfc_ctx *ctx, unsigned int size); +void mfc_otf_set_hwfc_index(struct mfc_ctx *ctx, int job_id); -int s5p_mfc_set_dec_codec_buffers(struct s5p_mfc_ctx *ctx); -int s5p_mfc_set_enc_codec_buffers(struct s5p_mfc_ctx *mfc_ctx); +int mfc_set_dec_codec_buffers(struct mfc_ctx *ctx); +int mfc_set_enc_codec_buffers(struct mfc_ctx *mfc_ctx); -int s5p_mfc_set_dec_stream_buffer(struct s5p_mfc_ctx *ctx, - struct s5p_mfc_buf *mfc_buf, +int mfc_set_dec_stream_buffer(struct mfc_ctx *ctx, + struct mfc_buf *mfc_buf, unsigned int start_num_byte, unsigned int buf_size); -void s5p_mfc_set_enc_frame_buffer(struct s5p_mfc_ctx *ctx, - struct s5p_mfc_buf *mfc_buf, int num_planes); -int s5p_mfc_set_enc_stream_buffer(struct s5p_mfc_ctx *ctx, - struct s5p_mfc_buf *mfc_buf); +void mfc_set_enc_frame_buffer(struct mfc_ctx *ctx, + struct mfc_buf *mfc_buf, int num_planes); +int mfc_set_enc_stream_buffer(struct mfc_ctx *ctx, + struct mfc_buf *mfc_buf); -void s5p_mfc_get_enc_frame_buffer(struct s5p_mfc_ctx *ctx, +void mfc_get_enc_frame_buffer(struct mfc_ctx *ctx, dma_addr_t addr[], int num_planes); -void s5p_mfc_set_enc_stride(struct s5p_mfc_ctx *ctx); +void mfc_set_enc_stride(struct mfc_ctx *ctx); -int s5p_mfc_set_dynamic_dpb(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *dst_vb); +int mfc_set_dynamic_dpb(struct mfc_ctx *ctx, struct mfc_buf *dst_vb); -void s5p_mfc_set_pixel_format(struct s5p_mfc_dev *dev, unsigned int format); +void mfc_set_pixel_format(struct mfc_dev *dev, unsigned int format); #endif /* __MFC_REG_H */ diff --git a/drivers/media/platform/exynos/mfc/mfc_regs_v10.h b/drivers/media/platform/exynos/mfc/mfc_regs_v10.h index 94d818eeefcc..e50d495ad0b6 100644 --- a/drivers/media/platform/exynos/mfc/mfc_regs_v10.h +++ b/drivers/media/platform/exynos/mfc/mfc_regs_v10.h @@ -21,723 +21,723 @@ #define HWFC_ENCODING_IDX 0x4 /* Codec Common Registers */ -#define S5P_FIMV_RISC_ON 0x0000 -#define S5P_FIMV_RISC2HOST_INT 0x003C -#define S5P_FIMV_HOST2RISC_INT 0x0044 -#define S5P_FIMV_RISC_BASE_ADDRESS 0x0054 - -#define S5P_FIMV_MFC_FW_CLOCK 0x1060 -#define S5P_FIMV_MFC_RESET 0x1070 - -#define S5P_FIMV_HOST2RISC_CMD 0x1100 -#define S5P_FIMV_RISC2HOST_CMD 0x1104 - -#define S5P_FIMV_MFC_BUS_STATUS 0x7018 -#define S5P_FIMV_MFC_RPEND 0x7028 -#define S5P_FIMV_MFC_WPEND 0x702C -#define S5P_FIMV_MFC_BUS_RESET_CTRL 0x7110 -#define S5P_FIMV_MFC_OFF 0x7120 -#define S5P_FIMV_MFC_STATE 0x7124 - -#define S5P_FIMV_FW_VERSION 0xF000 -#define S5P_FIMV_INSTANCE_ID 0xF008 -#define S5P_FIMV_CODEC_TYPE 0xF00C -#define S5P_FIMV_CONTEXT_MEM_ADDR 0xF014 -#define S5P_FIMV_CONTEXT_MEM_SIZE 0xF018 -#define S5P_FIMV_SHARED_MEM_ADDR 0xF01C -#define S5P_FIMV_PIXEL_FORMAT 0xF020 - -#define S5P_FIMV_METADATA_ENABLE 0xF024 -#define S5P_FIMV_MFC_VERSION 0xF028 -#define S5P_FIMV_DBG_INFO_ENABLE 0xF02C -#define S5P_FIMV_DBG_BUFFER_ADDR 0xF030 -#define S5P_FIMV_DBG_BUFFER_SIZE 0xF034 - -#define S5P_FIMV_CODEC_CONTROL 0xF038 -#define S5P_FIMV_DEC_TIMEOUT_VALUE 0xF03C -#define S5P_FIMV_HED_SHARED_MEM_ADDR 0xF040 +#define MFC_REG_RISC_ON 0x0000 +#define MFC_REG_RISC2HOST_INT 0x003C +#define MFC_REG_HOST2RISC_INT 0x0044 +#define MFC_REG_RISC_BASE_ADDRESS 0x0054 + +#define MFC_REG_MFC_FW_CLOCK 0x1060 +#define MFC_REG_MFC_RESET 0x1070 + +#define MFC_REG_HOST2RISC_CMD 0x1100 +#define MFC_REG_RISC2HOST_CMD 0x1104 + +#define MFC_REG_MFC_BUS_STATUS 0x7018 +#define MFC_REG_MFC_RPEND 0x7028 +#define MFC_REG_MFC_WPEND 0x702C +#define MFC_REG_MFC_BUS_RESET_CTRL 0x7110 +#define MFC_REG_MFC_OFF 0x7120 +#define MFC_REG_MFC_STATE 0x7124 + +#define MFC_REG_FW_VERSION 0xF000 +#define MFC_REG_INSTANCE_ID 0xF008 +#define MFC_REG_CODEC_TYPE 0xF00C +#define MFC_REG_CONTEXT_MEM_ADDR 0xF014 +#define MFC_REG_CONTEXT_MEM_SIZE 0xF018 +#define MFC_REG_SHARED_MEM_ADDR 0xF01C +#define MFC_REG_PIXEL_FORMAT 0xF020 + +#define MFC_REG_METADATA_ENABLE 0xF024 +#define MFC_REG_MFC_VERSION 0xF028 +#define MFC_REG_DBG_INFO_ENABLE 0xF02C +#define MFC_REG_DBG_BUFFER_ADDR 0xF030 +#define MFC_REG_DBG_BUFFER_SIZE 0xF034 + +#define MFC_REG_CODEC_CONTROL 0xF038 +#define MFC_REG_DEC_TIMEOUT_VALUE 0xF03C +#define MFC_REG_HED_SHARED_MEM_ADDR 0xF040 /* NAL QUEUE */ -#define S5P_FIMV_NAL_QUEUE_INPUT_ADDR 0xF044 -#define S5P_FIMV_NAL_QUEUE_INPUT_SIZE 0xF048 -#define S5P_FIMV_NAL_QUEUE_OUTPUT_ADDR 0xF04C -#define S5P_FIMV_NAL_QUEUE_OUTPUT_SIZE 0xF050 -#define S5P_FIMV_NAL_QUEUE_INPUT_COUNT 0xF054 +#define MFC_REG_NAL_QUEUE_INPUT_ADDR 0xF044 +#define MFC_REG_NAL_QUEUE_INPUT_SIZE 0xF048 +#define MFC_REG_NAL_QUEUE_OUTPUT_ADDR 0xF04C +#define MFC_REG_NAL_QUEUE_OUTPUT_SIZE 0xF050 +#define MFC_REG_NAL_QUEUE_INPUT_COUNT 0xF054 -#define S5P_FIMV_RET_INSTANCE_ID 0xF070 -#define S5P_FIMV_ERROR_CODE 0xF074 -#define S5P_FIMV_DBG_BUFFER_OUTPUT_SIZE 0xF078 -#define S5P_FIMV_METADATA_STATUS 0xF07C +#define MFC_REG_RET_INSTANCE_ID 0xF070 +#define MFC_REG_ERROR_CODE 0xF074 +#define MFC_REG_DBG_BUFFER_OUTPUT_SIZE 0xF078 +#define MFC_REG_METADATA_STATUS 0xF07C -#define S5P_FIMV_DBG_INFO_STAGE_COUNTER 0xF088 +#define MFC_REG_DBG_INFO_STAGE_COUNTER 0xF088 /* NAL QUEUE */ -#define S5P_FIMV_NAL_QUEUE_OUTPUT_COUNT 0xF08C -#define S5P_FIMV_NAL_QUEUE_INPUT_EXE_COUNT 0xF090 -#define S5P_FIMV_NAL_QUEUE_INFO 0xF094 +#define MFC_REG_NAL_QUEUE_OUTPUT_COUNT 0xF08C +#define MFC_REG_NAL_QUEUE_INPUT_EXE_COUNT 0xF090 +#define MFC_REG_NAL_QUEUE_INFO 0xF094 /* Decoder Registers */ -#define S5P_FIMV_D_CRC_CTRL 0xF0B0 -#define S5P_FIMV_D_DEC_OPTIONS 0xF0B4 +#define MFC_REG_D_CRC_CTRL 0xF0B0 +#define MFC_REG_D_DEC_OPTIONS 0xF0B4 -#define S5P_FIMV_D_DISPLAY_DELAY 0xF0B8 +#define MFC_REG_D_DISPLAY_DELAY 0xF0B8 -#define S5P_FIMV_D_SET_FRAME_WIDTH 0xF0BC -#define S5P_FIMV_D_SET_FRAME_HEIGHT 0xF0C0 +#define MFC_REG_D_SET_FRAME_WIDTH 0xF0BC +#define MFC_REG_D_SET_FRAME_HEIGHT 0xF0C0 -#define S5P_FIMV_D_SEI_ENABLE 0xF0C4 +#define MFC_REG_D_SEI_ENABLE 0xF0C4 -#define S5P_FIMV_D_FORCE_PIXEL_VAL 0xF0C8 +#define MFC_REG_D_FORCE_PIXEL_VAL 0xF0C8 /* Buffer setting registers */ /* Session return */ -#define S5P_FIMV_D_MIN_NUM_DPB 0xF0F0 -#define S5P_FIMV_D_MIN_FIRST_PLANE_DPB_SIZE 0xF0F4 -#define S5P_FIMV_D_MIN_SECOND_PLANE_DPB_SIZE 0xF0F8 -#define S5P_FIMV_D_MIN_THIRD_PLANE_DPB_SIZE 0xF0FC -#define S5P_FIMV_D_MIN_NUM_MV 0xF100 -#define S5P_FIMV_D_MVC_NUM_VIEWS 0xF104 -#define S5P_FIMV_D_MIN_SCRATCH_BUFFER_SIZE 0xF108 -#define S5P_FIMV_D_MIN_FIRST_PLANE_2BIT_DPB_SIZE 0xF10C -#define S5P_FIMV_D_MIN_SECOND_PLANE_2BIT_DPB_SIZE 0xF110 -#define S5P_FIMV_D_POST_FILTER_LUMA_DPB0 0xF120 -#define S5P_FIMV_D_POST_FILTER_LUMA_DPB1 0xF124 -#define S5P_FIMV_D_POST_FILTER_CHROMA_DPB0 0xF128 -#define S5P_FIMV_D_POST_FILTER_CHROMA_DPB1 0xF12C +#define MFC_REG_D_MIN_NUM_DPB 0xF0F0 +#define MFC_REG_D_MIN_FIRST_PLANE_DPB_SIZE 0xF0F4 +#define MFC_REG_D_MIN_SECOND_PLANE_DPB_SIZE 0xF0F8 +#define MFC_REG_D_MIN_THIRD_PLANE_DPB_SIZE 0xF0FC +#define MFC_REG_D_MIN_NUM_MV 0xF100 +#define MFC_REG_D_MVC_NUM_VIEWS 0xF104 +#define MFC_REG_D_MIN_SCRATCH_BUFFER_SIZE 0xF108 +#define MFC_REG_D_MIN_FIRST_PLANE_2BIT_DPB_SIZE 0xF10C +#define MFC_REG_D_MIN_SECOND_PLANE_2BIT_DPB_SIZE 0xF110 +#define MFC_REG_D_POST_FILTER_LUMA_DPB0 0xF120 +#define MFC_REG_D_POST_FILTER_LUMA_DPB1 0xF124 +#define MFC_REG_D_POST_FILTER_CHROMA_DPB0 0xF128 +#define MFC_REG_D_POST_FILTER_CHROMA_DPB1 0xF12C /* Buffers */ -#define S5P_FIMV_D_NUM_DPB 0xF130 -#define S5P_FIMV_D_NUM_MV 0xF134 -#define S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE 0xF138 -#define S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE 0xF13C -#define S5P_FIMV_D_THIRD_PLANE_DPB_STRIDE_SIZE 0xF140 -#define S5P_FIMV_D_FIRST_PLANE_DPB_SIZE 0xF144 -#define S5P_FIMV_D_SECOND_PLANE_DPB_SIZE 0xF148 -#define S5P_FIMV_D_THIRD_PLANE_DPB_SIZE 0xF14C -#define S5P_FIMV_D_MV_BUFFER_SIZE 0xF150 -#define S5P_FIMV_D_INIT_BUFFER_OPTIONS 0xF154 -#define S5P_FIMV_D_FIRST_PLANE_DPB0 0xF160 -#define S5P_FIMV_D_SECOND_PLANE_DPB0 0xF260 -#define S5P_FIMV_D_THIRD_PLANE_DPB0 0xF360 -#define S5P_FIMV_D_MV_BUFFER0 0xF460 -#define S5P_FIMV_D_SCRATCH_BUFFER_ADDR 0xF560 -#define S5P_FIMV_D_SCRATCH_BUFFER_SIZE 0xF564 -#define S5P_FIMV_D_METADATA_BUFFER_ADDR 0xF568 -#define S5P_FIMV_D_METADATA_BUFFER_SIZE 0xF56C - -#define S5P_FIMV_D_STATIC_BUFFER_ADDR 0xF570 -#define S5P_FIMV_D_STATIC_BUFFER_SIZE 0xF574 -#define S5P_FIMV_D_FIRST_PLANE_2BIT_DPB_SIZE 0xF578 -#define S5P_FIMV_D_SECOND_PLANE_2BIT_DPB_SIZE 0xF57C -#define S5P_FIMV_D_FIRST_PLANE_2BIT_DPB_STRIDE_SIZE 0xF580 -#define S5P_FIMV_D_SECOND_PLANE_2BIT_DPB_STRIDE_SIZE 0xF584 - -#define S5P_FIMV_D_NAL_START_OPTIONS 0xF5AC +#define MFC_REG_D_NUM_DPB 0xF130 +#define MFC_REG_D_NUM_MV 0xF134 +#define MFC_REG_D_FIRST_PLANE_DPB_STRIDE_SIZE 0xF138 +#define MFC_REG_D_SECOND_PLANE_DPB_STRIDE_SIZE 0xF13C +#define MFC_REG_D_THIRD_PLANE_DPB_STRIDE_SIZE 0xF140 +#define MFC_REG_D_FIRST_PLANE_DPB_SIZE 0xF144 +#define MFC_REG_D_SECOND_PLANE_DPB_SIZE 0xF148 +#define MFC_REG_D_THIRD_PLANE_DPB_SIZE 0xF14C +#define MFC_REG_D_MV_BUFFER_SIZE 0xF150 +#define MFC_REG_D_INIT_BUFFER_OPTIONS 0xF154 +#define MFC_REG_D_FIRST_PLANE_DPB0 0xF160 +#define MFC_REG_D_SECOND_PLANE_DPB0 0xF260 +#define MFC_REG_D_THIRD_PLANE_DPB0 0xF360 +#define MFC_REG_D_MV_BUFFER0 0xF460 +#define MFC_REG_D_SCRATCH_BUFFER_ADDR 0xF560 +#define MFC_REG_D_SCRATCH_BUFFER_SIZE 0xF564 +#define MFC_REG_D_METADATA_BUFFER_ADDR 0xF568 +#define MFC_REG_D_METADATA_BUFFER_SIZE 0xF56C + +#define MFC_REG_D_STATIC_BUFFER_ADDR 0xF570 +#define MFC_REG_D_STATIC_BUFFER_SIZE 0xF574 +#define MFC_REG_D_FIRST_PLANE_2BIT_DPB_SIZE 0xF578 +#define MFC_REG_D_SECOND_PLANE_2BIT_DPB_SIZE 0xF57C +#define MFC_REG_D_FIRST_PLANE_2BIT_DPB_STRIDE_SIZE 0xF580 +#define MFC_REG_D_SECOND_PLANE_2BIT_DPB_STRIDE_SIZE 0xF584 + +#define MFC_REG_D_NAL_START_OPTIONS 0xF5AC /* Nal cmd */ -#define S5P_FIMV_D_CPB_BUFFER_ADDR 0xF5B0 -#define S5P_FIMV_D_CPB_BUFFER_SIZE 0xF5B4 -#define S5P_FIMV_D_AVAILABLE_DPB_FLAG_UPPER 0xF5B8 -#define S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER 0xF5BC -#define S5P_FIMV_D_CPB_BUFFER_OFFSET 0xF5C0 -#define S5P_FIMV_D_SLICE_IF_ENABLE 0xF5C4 -#define S5P_FIMV_D_PICTURE_TAG 0xF5C8 -#define S5P_FIMV_D_STREAM_DATA_SIZE 0xF5D0 -#define S5P_FIMV_D_DYNAMIC_DPB_FLAG_UPPER 0xF5D4 -#define S5P_FIMV_D_DYNAMIC_DPB_FLAG_LOWER 0xF5D8 +#define MFC_REG_D_CPB_BUFFER_ADDR 0xF5B0 +#define MFC_REG_D_CPB_BUFFER_SIZE 0xF5B4 +#define MFC_REG_D_AVAILABLE_DPB_FLAG_UPPER 0xF5B8 +#define MFC_REG_D_AVAILABLE_DPB_FLAG_LOWER 0xF5BC +#define MFC_REG_D_CPB_BUFFER_OFFSET 0xF5C0 +#define MFC_REG_D_SLICE_IF_ENABLE 0xF5C4 +#define MFC_REG_D_PICTURE_TAG 0xF5C8 +#define MFC_REG_D_STREAM_DATA_SIZE 0xF5D0 +#define MFC_REG_D_DYNAMIC_DPB_FLAG_UPPER 0xF5D4 +#define MFC_REG_D_DYNAMIC_DPB_FLAG_LOWER 0xF5D8 /* Nal return */ -#define S5P_FIMV_D_DISPLAY_FRAME_WIDTH 0xF600 -#define S5P_FIMV_D_DISPLAY_FRAME_HEIGHT 0xF604 -#define S5P_FIMV_D_DISPLAY_STATUS 0xF608 -#define S5P_FIMV_D_DISPLAY_FIRST_PLANE_ADDR 0xF60C -#define S5P_FIMV_D_DISPLAY_SECOND_PLANE_ADDR 0xF610 -#define S5P_FIMV_D_DISPLAY_THIRD_PLANE_ADDR 0xF614 -#define S5P_FIMV_D_DISPLAY_FRAME_TYPE 0xF618 -#define S5P_FIMV_D_DISPLAY_CROP_INFO1 0xF61C -#define S5P_FIMV_D_DISPLAY_CROP_INFO2 0xF620 -#define S5P_FIMV_D_DISPLAY_PICTURE_PROFILE 0xF624 -#define S5P_FIMV_D_DISPLAY_FIRST_PLANE_CRC 0xF628 -#define S5P_FIMV_D_DISPLAY_SECOND_PLANE_CRC 0xF62C -#define S5P_FIMV_D_DISPLAY_THIRD_PLANE_CRC 0xF630 -#define S5P_FIMV_D_DISPLAY_ASPECT_RATIO 0xF634 -#define S5P_FIMV_D_DISPLAY_EXTENDED_AR 0xF638 -#define S5P_FIMV_D_DECODED_FRAME_WIDTH 0xF63C -#define S5P_FIMV_D_DECODED_FRAME_HEIGHT 0xF640 -#define S5P_FIMV_D_DECODED_STATUS 0xF644 -#define S5P_FIMV_D_DECODED_FIRST_PLANE_ADDR 0xF648 -#define S5P_FIMV_D_DECODED_SECOND_PLANE_ADDR 0xF64C -#define S5P_FIMV_D_DECODED_THIRD_PLANE_ADDR 0xF650 -#define S5P_FIMV_D_DECODED_FRAME_TYPE 0xF654 -#define S5P_FIMV_D_DECODED_CROP_INFO1 0xF658 -#define S5P_FIMV_D_DECODED_CROP_INFO2 0xF65C -#define S5P_FIMV_D_DECODED_PICTURE_PROFILE 0xF660 -#define S5P_FIMV_D_DECODED_NAL_SIZE 0xF664 -#define S5P_FIMV_D_DECODED_FIRST_PLANE_CRC 0xF668 -#define S5P_FIMV_D_DECODED_SECOND_PLANE_CRC 0xF66C -#define S5P_FIMV_D_DECODED_THIRD_PLANE_CRC 0xF670 -#define S5P_FIMV_D_RET_PICTURE_TAG_TOP 0xF674 -#define S5P_FIMV_D_RET_PICTURE_TAG_BOT 0xF678 -#define S5P_FIMV_D_RET_PICTURE_TIME_TOP 0xF67C -#define S5P_FIMV_D_RET_PICTURE_TIME_BOT 0xF680 -#define S5P_FIMV_D_CHROMA_FORMAT 0xF684 - -#define S5P_FIMV_D_VC1_INFO 0xF688 -#define S5P_FIMV_D_MPEG4_INFO 0xF68C -#define S5P_FIMV_D_H264_INFO 0xF690 -#define S5P_FIMV_D_HEVC_INFO 0xF6A0 -#define S5P_FIMV_D_BPG_INFO 0xF6A8 - -#define S5P_FIMV_D_METADATA_ADDR_CONCEALED_MB 0xF6B0 -#define S5P_FIMV_D_METADATA_SIZE_CONCEALED_MB 0xF6B4 -#define S5P_FIMV_D_METADATA_ADDR_VC1_PARAM 0xF6B8 -#define S5P_FIMV_D_METADATA_SIZE_VC1_PARAM 0xF6BC -#define S5P_FIMV_D_METADATA_ADDR_SEI_NAL 0xF6C0 -#define S5P_FIMV_D_METADATA_SIZE_SEI_NAL 0xF6C4 -#define S5P_FIMV_D_METADATA_ADDR_VUI 0xF6C8 -#define S5P_FIMV_D_METADATA_SIZE_VUI 0xF6CC -#define S5P_FIMV_D_METADATA_ADDR_MVCVUI 0xF6D0 -#define S5P_FIMV_D_METADATA_SIZE_MVCVUI 0xF6D4 - -#define S5P_FIMV_D_MVC_VIEW_ID 0xF6D8 - -#define S5P_FIMV_D_SEI_AVAIL 0xF6DC -#define S5P_FIMV_D_FRAME_PACK_ARRGMENT_ID 0xF6E0 -#define S5P_FIMV_D_FRAME_PACK_SEI_INFO 0xF6E4 -#define S5P_FIMV_D_FRAME_PACK_GRID_POS 0xF6E8 - -#define S5P_FIMV_D_DISPLAY_RECOVERY_SEI_INFO 0xF6EC -#define S5P_FIMV_D_DECODED_RECOVERY_SEI_INFO 0xF6F0 - -#define S5P_FIMV_D_DISPLAY_FIRST_PLANE_2BIT_CRC 0xF6FC -#define S5P_FIMV_D_DISPLAY_SECOND_PLANE_2BIT_CRC 0xF700 -#define S5P_FIMV_D_DECODED_FIRST_PLANE_2BIT_CRC 0xF704 -#define S5P_FIMV_D_DECODED_SECOND_PLANE_2BIT_CRC 0xF708 - -#define S5P_FIMV_D_VIDEO_SIGNAL_TYPE 0xF70C -#define S5P_FIMV_D_CONTENT_LIGHT_LEVEL_INFO_SEI 0xF710 -#define S5P_FIMV_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_0 0xF714 -#define S5P_FIMV_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_1 0xF718 - -#define S5P_FIMV_D_USED_DPB_FLAG_UPPER 0xF720 -#define S5P_FIMV_D_USED_DPB_FLAG_LOWER 0xF724 - -#define S5P_FIMV_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_2 0xF728 -#define S5P_FIMV_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_3 0xF72C -#define S5P_FIMV_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_4 0xF730 -#define S5P_FIMV_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_5 0xF734 - -#define S5P_FIMV_D_BLACK_BAR_START_POS 0xF738 -#define S5P_FIMV_D_BLACK_BAR_IMAGE_SIZE 0xF73C - -#define S5P_FIMV_D_DISPLAY_LUMA_ADDR 0xF60C -#define S5P_FIMV_D_DISPLAY_CHROMA_ADDR 0xF610 - -#define S5P_FIMV_D_DECODED_LUMA_ADDR 0xF648 -#define S5P_FIMV_D_DECODED_CHROMA_ADDR 0xF64C +#define MFC_REG_D_DISPLAY_FRAME_WIDTH 0xF600 +#define MFC_REG_D_DISPLAY_FRAME_HEIGHT 0xF604 +#define MFC_REG_D_DISPLAY_STATUS 0xF608 +#define MFC_REG_D_DISPLAY_FIRST_PLANE_ADDR 0xF60C +#define MFC_REG_D_DISPLAY_SECOND_PLANE_ADDR 0xF610 +#define MFC_REG_D_DISPLAY_THIRD_PLANE_ADDR 0xF614 +#define MFC_REG_D_DISPLAY_FRAME_TYPE 0xF618 +#define MFC_REG_D_DISPLAY_CROP_INFO1 0xF61C +#define MFC_REG_D_DISPLAY_CROP_INFO2 0xF620 +#define MFC_REG_D_DISPLAY_PICTURE_PROFILE 0xF624 +#define MFC_REG_D_DISPLAY_FIRST_PLANE_CRC 0xF628 +#define MFC_REG_D_DISPLAY_SECOND_PLANE_CRC 0xF62C +#define MFC_REG_D_DISPLAY_THIRD_PLANE_CRC 0xF630 +#define MFC_REG_D_DISPLAY_ASPECT_RATIO 0xF634 +#define MFC_REG_D_DISPLAY_EXTENDED_AR 0xF638 +#define MFC_REG_D_DECODED_FRAME_WIDTH 0xF63C +#define MFC_REG_D_DECODED_FRAME_HEIGHT 0xF640 +#define MFC_REG_D_DECODED_STATUS 0xF644 +#define MFC_REG_D_DECODED_FIRST_PLANE_ADDR 0xF648 +#define MFC_REG_D_DECODED_SECOND_PLANE_ADDR 0xF64C +#define MFC_REG_D_DECODED_THIRD_PLANE_ADDR 0xF650 +#define MFC_REG_D_DECODED_FRAME_TYPE 0xF654 +#define MFC_REG_D_DECODED_CROP_INFO1 0xF658 +#define MFC_REG_D_DECODED_CROP_INFO2 0xF65C +#define MFC_REG_D_DECODED_PICTURE_PROFILE 0xF660 +#define MFC_REG_D_DECODED_NAL_SIZE 0xF664 +#define MFC_REG_D_DECODED_FIRST_PLANE_CRC 0xF668 +#define MFC_REG_D_DECODED_SECOND_PLANE_CRC 0xF66C +#define MFC_REG_D_DECODED_THIRD_PLANE_CRC 0xF670 +#define MFC_REG_D_RET_PICTURE_TAG_TOP 0xF674 +#define MFC_REG_D_RET_PICTURE_TAG_BOT 0xF678 +#define MFC_REG_D_RET_PICTURE_TIME_TOP 0xF67C +#define MFC_REG_D_RET_PICTURE_TIME_BOT 0xF680 +#define MFC_REG_D_CHROMA_FORMAT 0xF684 + +#define MFC_REG_D_VC1_INFO 0xF688 +#define MFC_REG_D_MPEG4_INFO 0xF68C +#define MFC_REG_D_H264_INFO 0xF690 +#define MFC_REG_D_HEVC_INFO 0xF6A0 +#define MFC_REG_D_BPG_INFO 0xF6A8 + +#define MFC_REG_D_METADATA_ADDR_CONCEALED_MB 0xF6B0 +#define MFC_REG_D_METADATA_SIZE_CONCEALED_MB 0xF6B4 +#define MFC_REG_D_METADATA_ADDR_VC1_PARAM 0xF6B8 +#define MFC_REG_D_METADATA_SIZE_VC1_PARAM 0xF6BC +#define MFC_REG_D_METADATA_ADDR_SEI_NAL 0xF6C0 +#define MFC_REG_D_METADATA_SIZE_SEI_NAL 0xF6C4 +#define MFC_REG_D_METADATA_ADDR_VUI 0xF6C8 +#define MFC_REG_D_METADATA_SIZE_VUI 0xF6CC +#define MFC_REG_D_METADATA_ADDR_MVCVUI 0xF6D0 +#define MFC_REG_D_METADATA_SIZE_MVCVUI 0xF6D4 + +#define MFC_REG_D_MVC_VIEW_ID 0xF6D8 + +#define MFC_REG_D_SEI_AVAIL 0xF6DC +#define MFC_REG_D_FRAME_PACK_ARRGMENT_ID 0xF6E0 +#define MFC_REG_D_FRAME_PACK_SEI_INFO 0xF6E4 +#define MFC_REG_D_FRAME_PACK_GRID_POS 0xF6E8 + +#define MFC_REG_D_DISPLAY_RECOVERY_SEI_INFO 0xF6EC +#define MFC_REG_D_DECODED_RECOVERY_SEI_INFO 0xF6F0 + +#define MFC_REG_D_DISPLAY_FIRST_PLANE_2BIT_CRC 0xF6FC +#define MFC_REG_D_DISPLAY_SECOND_PLANE_2BIT_CRC 0xF700 +#define MFC_REG_D_DECODED_FIRST_PLANE_2BIT_CRC 0xF704 +#define MFC_REG_D_DECODED_SECOND_PLANE_2BIT_CRC 0xF708 + +#define MFC_REG_D_VIDEO_SIGNAL_TYPE 0xF70C +#define MFC_REG_D_CONTENT_LIGHT_LEVEL_INFO_SEI 0xF710 +#define MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_0 0xF714 +#define MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_1 0xF718 + +#define MFC_REG_D_USED_DPB_FLAG_UPPER 0xF720 +#define MFC_REG_D_USED_DPB_FLAG_LOWER 0xF724 + +#define MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_2 0xF728 +#define MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_3 0xF72C +#define MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_4 0xF730 +#define MFC_REG_D_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_5 0xF734 + +#define MFC_REG_D_BLACK_BAR_START_POS 0xF738 +#define MFC_REG_D_BLACK_BAR_IMAGE_SIZE 0xF73C + +#define MFC_REG_D_DISPLAY_LUMA_ADDR 0xF60C +#define MFC_REG_D_DISPLAY_CHROMA_ADDR 0xF610 + +#define MFC_REG_D_DECODED_LUMA_ADDR 0xF648 +#define MFC_REG_D_DECODED_CHROMA_ADDR 0xF64C /* Encoder Registers */ -#define S5P_FIMV_E_CROPPED_FRAME_WIDTH 0xF778 -#define S5P_FIMV_E_CROPPED_FRAME_HEIGHT 0xF77C -#define S5P_FIMV_E_FRAME_CROP_OFFSET 0xF780 -#define S5P_FIMV_E_ENC_OPTIONS 0xF784 -#define S5P_FIMV_E_PICTURE_PROFILE 0xF788 -#define S5P_FIMV_E_VBV_BUFFER_SIZE 0xF78C -#define S5P_FIMV_E_VBV_INIT_DELAY 0xF790 -#define S5P_FIMV_E_FIXED_PICTURE_QP 0xF794 -#define S5P_FIMV_E_RC_CONFIG 0xF798 -#define S5P_FIMV_E_RC_QP_BOUND 0xF79C -#define S5P_FIMV_E_RC_QP_BOUND_PB 0xF7A0 -#define S5P_FIMV_E_RC_MODE 0xF7A4 - -#define S5P_FIMV_E_MB_RC_CONFIG 0xF7A8 -#define S5P_FIMV_E_PADDING_CTRL 0xF7AC -#define S5P_FIMV_E_AIR_THRESHOLD 0xF7B0 - -#define S5P_FIMV_E_MV_HOR_RANGE 0xF7B4 -#define S5P_FIMV_E_MV_VER_RANGE 0xF7B8 - -#define S5P_FIMV_E_HIGH_QUALITY_MODE 0xF7C0 -#define S5P_FIMV_E_VIDEO_SIGNAL_TYPE 0xF7C4 - -#define S5P_FIMV_E_SAO_WEIGHT0 0xF7C8 -#define S5P_FIMV_E_SAO_WEIGHT1 0xF7CC - -#define S5P_FIMV_E_NUM_DPB 0xF890 -#define S5P_FIMV_E_MIN_SCRATCH_BUFFER_SIZE 0xF894 - -#define S5P_FIMV_E_LUMA_DPB 0xF8C0 -#define S5P_FIMV_E_CHROMA_DPB 0xF904 -#define S5P_FIMV_E_ME_BUFFER 0xF948 - -#define S5P_FIMV_E_SCRATCH_BUFFER_ADDR 0xF98C -#define S5P_FIMV_E_SCRATCH_BUFFER_SIZE 0xF990 -#define S5P_FIMV_E_TMV_BUFFER0 0xF994 -#define S5P_FIMV_E_TMV_BUFFER1 0xF998 -#define S5P_FIMV_E_IR_BUFFER_ADDR 0xF99C -#define S5P_FIMV_E_SOURCE_FIRST_2BIT_ADDR 0xF9D0 -#define S5P_FIMV_E_SOURCE_SECOND_2BIT_ADDR 0xF9D4 -#define S5P_FIMV_E_SOURCE_FIRST_2BIT_STRIDE 0xF9D8 -#define S5P_FIMV_E_SOURCE_SECOND_2BIT_STRIDE 0xF9DC -#define S5P_FIMV_E_SOURCE_FIRST_ADDR 0xF9E0 -#define S5P_FIMV_E_SOURCE_SECOND_ADDR 0xF9E4 -#define S5P_FIMV_E_SOURCE_THIRD_ADDR 0xF9E8 -#define S5P_FIMV_E_SOURCE_FIRST_STRIDE 0xF9EC -#define S5P_FIMV_E_SOURCE_SECOND_STRIDE 0xF9F0 -#define S5P_FIMV_E_SOURCE_THIRD_STRIDE 0xF9F4 -#define S5P_FIMV_E_STREAM_BUFFER_ADDR 0xF9F8 -#define S5P_FIMV_E_STREAM_BUFFER_SIZE 0xF9FC -#define S5P_FIMV_E_ROI_BUFFER_ADDR 0xFA00 - -#define S5P_FIMV_E_PARAM_CHANGE 0xFA04 -#define S5P_FIMV_E_IR_SIZE 0xFA08 -#define S5P_FIMV_E_GOP_CONFIG 0xFA0C -#define S5P_FIMV_E_MSLICE_MODE 0xFA10 -#define S5P_FIMV_E_MSLICE_SIZE_MB 0xFA14 -#define S5P_FIMV_E_MSLICE_SIZE_BITS 0xFA18 -#define S5P_FIMV_E_FRAME_INSERTION 0xFA1C - -#define S5P_FIMV_E_RC_FRAME_RATE 0xFA20 -#define S5P_FIMV_E_RC_BIT_RATE 0xFA24 -#define S5P_FIMV_E_RC_ROI_CTRL 0xFA2C -#define S5P_FIMV_E_PICTURE_TAG 0xFA30 -#define S5P_FIMV_E_BIT_COUNT_ENABLE 0xFA34 -#define S5P_FIMV_E_MAX_BIT_COUNT 0xFA38 -#define S5P_FIMV_E_MIN_BIT_COUNT 0xFA3C - -#define S5P_FIMV_E_METADATA_BUFFER_ADDR 0xFA40 -#define S5P_FIMV_E_METADATA_BUFFER_SIZE 0xFA44 - -#define S5P_FIMV_E_ENCODING_ORDER_TIME_INFO 0xFA50 -#define S5P_FIMV_E_ENCODING_ORDER_INFO 0xFA54 -#define S5P_FIMV_E_STREAM_BUFFER_OFFSET 0xFA58 -#define S5P_FIMV_E_GOP_CONFIG2 0xFA5C -#define S5P_FIMV_E_WEIGHT_FOR_WEIGHTED_PREDICTION 0xFA60 - -#define S5P_FIMV_E_ENCODED_SOURCE_FIRST_ADDR 0xFA70 -#define S5P_FIMV_E_ENCODED_SOURCE_SECOND_ADDR 0xFA74 -#define S5P_FIMV_E_ENCODED_SOURCE_THIRD_ADDR 0xFA78 - -#define S5P_FIMV_E_STREAM_SIZE 0xFA80 -#define S5P_FIMV_E_SLICE_TYPE 0xFA84 -#define S5P_FIMV_E_PICTURE_COUNT 0xFA88 -#define S5P_FIMV_E_RET_PICTURE_TAG 0xFA8C - -#define S5P_FIMV_E_RECON_LUMA_DPB_ADDR 0xFA9C -#define S5P_FIMV_E_RECON_CHROMA_DPB_ADDR 0xFAA0 -#define S5P_FIMV_E_METADATA_ADDR_ENC_SLICE 0xFAA4 -#define S5P_FIMV_E_METADATA_SIZE_ENC_SLICE 0xFAA8 - -#define S5P_FIMV_E_NAL_DONE_INFO 0xFAEC - -#define S5P_FIMV_E_MPEG4_OPTIONS 0xFB10 -#define S5P_FIMV_E_MPEG4_HEC_PERIOD 0xFB14 - -#define S5P_FIMV_E_BPG_OPTIONS 0xFB1C -#define S5P_FIMV_E_BPG_EXT_CTB_QP_CTRL 0xFB20 -#define S5P_FIMV_E_BPG_CHROMA_QP_OFFSET 0xFB24 -#define S5P_FIMV_E_BPG_EXTENSION_DATA_SIZE 0xFB28 - -#define S5P_FIMV_E_H264_HD_SVC_EXTENSION_0 0xFB44 -#define S5P_FIMV_E_H264_HD_SVC_EXTENSION_1 0xFB48 -#define S5P_FIMV_E_ASPECT_RATIO 0xFB4C -#define S5P_FIMV_E_EXTENDED_SAR 0xFB50 - -#define S5P_FIMV_E_H264_OPTIONS 0xFB54 -#define S5P_FIMV_E_H264_OPTIONS_2 0xFB58 -#define S5P_FIMV_E_H264_LF_ALPHA_OFFSET 0xFB5C -#define S5P_FIMV_E_H264_LF_BETA_OFFSET 0xFB60 -#define S5P_FIMV_E_H264_REFRESH_PERIOD 0xFB64 - -#define S5P_FIMV_E_H264_FMO_SLICE_GRP_MAP_TYPE 0xFB68 -#define S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1 0xFB6C -#define S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_DIR 0xFB70 -#define S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_RATE_MINUS1 0xFB74 -#define S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_0 0xFB78 -#define S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_1 0xFB7C -#define S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_2 0xFB80 -#define S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_3 0xFB84 - -#define S5P_FIMV_E_H264_ASO_SLICE_ORDER_0 0xFB88 -#define S5P_FIMV_E_H264_ASO_SLICE_ORDER_1 0xFB8C -#define S5P_FIMV_E_H264_ASO_SLICE_ORDER_2 0xFB90 -#define S5P_FIMV_E_H264_ASO_SLICE_ORDER_3 0xFB94 -#define S5P_FIMV_E_H264_ASO_SLICE_ORDER_4 0xFB98 -#define S5P_FIMV_E_H264_ASO_SLICE_ORDER_5 0xFB9C -#define S5P_FIMV_E_H264_ASO_SLICE_ORDER_6 0xFBA0 -#define S5P_FIMV_E_H264_ASO_SLICE_ORDER_7 0xFBA4 -#define S5P_FIMV_E_H264_CHROMA_QP_OFFSET 0xFBA8 - -#define S5P_FIMV_E_NUM_T_LAYER 0xFBAC -#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER0 0xFBB0 -#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER1 0xFBB4 -#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER2 0xFBB8 -#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER3 0xFBBC -#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER4 0xFBC0 -#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER5 0xFBC4 -#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER6 0xFBC8 +#define MFC_REG_E_CROPPED_FRAME_WIDTH 0xF778 +#define MFC_REG_E_CROPPED_FRAME_HEIGHT 0xF77C +#define MFC_REG_E_FRAME_CROP_OFFSET 0xF780 +#define MFC_REG_E_ENC_OPTIONS 0xF784 +#define MFC_REG_E_PICTURE_PROFILE 0xF788 +#define MFC_REG_E_VBV_BUFFER_SIZE 0xF78C +#define MFC_REG_E_VBV_INIT_DELAY 0xF790 +#define MFC_REG_E_FIXED_PICTURE_QP 0xF794 +#define MFC_REG_E_RC_CONFIG 0xF798 +#define MFC_REG_E_RC_QP_BOUND 0xF79C +#define MFC_REG_E_RC_QP_BOUND_PB 0xF7A0 +#define MFC_REG_E_RC_MODE 0xF7A4 + +#define MFC_REG_E_MB_RC_CONFIG 0xF7A8 +#define MFC_REG_E_PADDING_CTRL 0xF7AC +#define MFC_REG_E_AIR_THRESHOLD 0xF7B0 + +#define MFC_REG_E_MV_HOR_RANGE 0xF7B4 +#define MFC_REG_E_MV_VER_RANGE 0xF7B8 + +#define MFC_REG_E_HIGH_QUALITY_MODE 0xF7C0 +#define MFC_REG_E_VIDEO_SIGNAL_TYPE 0xF7C4 + +#define MFC_REG_E_SAO_WEIGHT0 0xF7C8 +#define MFC_REG_E_SAO_WEIGHT1 0xF7CC + +#define MFC_REG_E_NUM_DPB 0xF890 +#define MFC_REG_E_MIN_SCRATCH_BUFFER_SIZE 0xF894 + +#define MFC_REG_E_LUMA_DPB 0xF8C0 +#define MFC_REG_E_CHROMA_DPB 0xF904 +#define MFC_REG_E_ME_BUFFER 0xF948 + +#define MFC_REG_E_SCRATCH_BUFFER_ADDR 0xF98C +#define MFC_REG_E_SCRATCH_BUFFER_SIZE 0xF990 +#define MFC_REG_E_TMV_BUFFER0 0xF994 +#define MFC_REG_E_TMV_BUFFER1 0xF998 +#define MFC_REG_E_IR_BUFFER_ADDR 0xF99C +#define MFC_REG_E_SOURCE_FIRST_2BIT_ADDR 0xF9D0 +#define MFC_REG_E_SOURCE_SECOND_2BIT_ADDR 0xF9D4 +#define MFC_REG_E_SOURCE_FIRST_2BIT_STRIDE 0xF9D8 +#define MFC_REG_E_SOURCE_SECOND_2BIT_STRIDE 0xF9DC +#define MFC_REG_E_SOURCE_FIRST_ADDR 0xF9E0 +#define MFC_REG_E_SOURCE_SECOND_ADDR 0xF9E4 +#define MFC_REG_E_SOURCE_THIRD_ADDR 0xF9E8 +#define MFC_REG_E_SOURCE_FIRST_STRIDE 0xF9EC +#define MFC_REG_E_SOURCE_SECOND_STRIDE 0xF9F0 +#define MFC_REG_E_SOURCE_THIRD_STRIDE 0xF9F4 +#define MFC_REG_E_STREAM_BUFFER_ADDR 0xF9F8 +#define MFC_REG_E_STREAM_BUFFER_SIZE 0xF9FC +#define MFC_REG_E_ROI_BUFFER_ADDR 0xFA00 + +#define MFC_REG_E_PARAM_CHANGE 0xFA04 +#define MFC_REG_E_IR_SIZE 0xFA08 +#define MFC_REG_E_GOP_CONFIG 0xFA0C +#define MFC_REG_E_MSLICE_MODE 0xFA10 +#define MFC_REG_E_MSLICE_SIZE_MB 0xFA14 +#define MFC_REG_E_MSLICE_SIZE_BITS 0xFA18 +#define MFC_REG_E_FRAME_INSERTION 0xFA1C + +#define MFC_REG_E_RC_FRAME_RATE 0xFA20 +#define MFC_REG_E_RC_BIT_RATE 0xFA24 +#define MFC_REG_E_RC_ROI_CTRL 0xFA2C +#define MFC_REG_E_PICTURE_TAG 0xFA30 +#define MFC_REG_E_BIT_COUNT_ENABLE 0xFA34 +#define MFC_REG_E_MAX_BIT_COUNT 0xFA38 +#define MFC_REG_E_MIN_BIT_COUNT 0xFA3C + +#define MFC_REG_E_METADATA_BUFFER_ADDR 0xFA40 +#define MFC_REG_E_METADATA_BUFFER_SIZE 0xFA44 + +#define MFC_REG_E_ENCODING_ORDER_TIME_INFO 0xFA50 +#define MFC_REG_E_ENCODING_ORDER_INFO 0xFA54 +#define MFC_REG_E_STREAM_BUFFER_OFFSET 0xFA58 +#define MFC_REG_E_GOP_CONFIG2 0xFA5C +#define MFC_REG_E_WEIGHT_FOR_WEIGHTED_PREDICTION 0xFA60 + +#define MFC_REG_E_ENCODED_SOURCE_FIRST_ADDR 0xFA70 +#define MFC_REG_E_ENCODED_SOURCE_SECOND_ADDR 0xFA74 +#define MFC_REG_E_ENCODED_SOURCE_THIRD_ADDR 0xFA78 + +#define MFC_REG_E_STREAM_SIZE 0xFA80 +#define MFC_REG_E_SLICE_TYPE 0xFA84 +#define MFC_REG_E_PICTURE_COUNT 0xFA88 +#define MFC_REG_E_RET_PICTURE_TAG 0xFA8C + +#define MFC_REG_E_RECON_LUMA_DPB_ADDR 0xFA9C +#define MFC_REG_E_RECON_CHROMA_DPB_ADDR 0xFAA0 +#define MFC_REG_E_METADATA_ADDR_ENC_SLICE 0xFAA4 +#define MFC_REG_E_METADATA_SIZE_ENC_SLICE 0xFAA8 + +#define MFC_REG_E_NAL_DONE_INFO 0xFAEC + +#define MFC_REG_E_MPEG4_OPTIONS 0xFB10 +#define MFC_REG_E_MPEG4_HEC_PERIOD 0xFB14 + +#define MFC_REG_E_BPG_OPTIONS 0xFB1C +#define MFC_REG_E_BPG_EXT_CTB_QP_CTRL 0xFB20 +#define MFC_REG_E_BPG_CHROMA_QP_OFFSET 0xFB24 +#define MFC_REG_E_BPG_EXTENSION_DATA_SIZE 0xFB28 + +#define MFC_REG_E_H264_HD_SVC_EXTENSION_0 0xFB44 +#define MFC_REG_E_H264_HD_SVC_EXTENSION_1 0xFB48 +#define MFC_REG_E_ASPECT_RATIO 0xFB4C +#define MFC_REG_E_EXTENDED_SAR 0xFB50 + +#define MFC_REG_E_H264_OPTIONS 0xFB54 +#define MFC_REG_E_H264_OPTIONS_2 0xFB58 +#define MFC_REG_E_H264_LF_ALPHA_OFFSET 0xFB5C +#define MFC_REG_E_H264_LF_BETA_OFFSET 0xFB60 +#define MFC_REG_E_H264_REFRESH_PERIOD 0xFB64 + +#define MFC_REG_E_H264_FMO_SLICE_GRP_MAP_TYPE 0xFB68 +#define MFC_REG_E_H264_FMO_NUM_SLICE_GRP_MINUS1 0xFB6C +#define MFC_REG_E_H264_FMO_SLICE_GRP_CHANGE_DIR 0xFB70 +#define MFC_REG_E_H264_FMO_SLICE_GRP_CHANGE_RATE_MINUS1 0xFB74 +#define MFC_REG_E_H264_FMO_RUN_LENGTH_MINUS1_0 0xFB78 +#define MFC_REG_E_H264_FMO_RUN_LENGTH_MINUS1_1 0xFB7C +#define MFC_REG_E_H264_FMO_RUN_LENGTH_MINUS1_2 0xFB80 +#define MFC_REG_E_H264_FMO_RUN_LENGTH_MINUS1_3 0xFB84 + +#define MFC_REG_E_H264_ASO_SLICE_ORDER_0 0xFB88 +#define MFC_REG_E_H264_ASO_SLICE_ORDER_1 0xFB8C +#define MFC_REG_E_H264_ASO_SLICE_ORDER_2 0xFB90 +#define MFC_REG_E_H264_ASO_SLICE_ORDER_3 0xFB94 +#define MFC_REG_E_H264_ASO_SLICE_ORDER_4 0xFB98 +#define MFC_REG_E_H264_ASO_SLICE_ORDER_5 0xFB9C +#define MFC_REG_E_H264_ASO_SLICE_ORDER_6 0xFBA0 +#define MFC_REG_E_H264_ASO_SLICE_ORDER_7 0xFBA4 +#define MFC_REG_E_H264_CHROMA_QP_OFFSET 0xFBA8 + +#define MFC_REG_E_NUM_T_LAYER 0xFBAC +#define MFC_REG_E_HIERARCHICAL_QP_LAYER0 0xFBB0 +#define MFC_REG_E_HIERARCHICAL_QP_LAYER1 0xFBB4 +#define MFC_REG_E_HIERARCHICAL_QP_LAYER2 0xFBB8 +#define MFC_REG_E_HIERARCHICAL_QP_LAYER3 0xFBBC +#define MFC_REG_E_HIERARCHICAL_QP_LAYER4 0xFBC0 +#define MFC_REG_E_HIERARCHICAL_QP_LAYER5 0xFBC4 +#define MFC_REG_E_HIERARCHICAL_QP_LAYER6 0xFBC8 /* For backward compatibility */ -#define S5P_FIMV_E_H264_FRAME_PACKING_SEI_INFO 0xFC4C - -#define S5P_FIMV_E_H264_NAL_CONTROL 0xFD14 -#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0 0xFD18 -#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER1 0xFD1C -#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER2 0xFD20 -#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER3 0xFD24 -#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER4 0xFD28 -#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER5 0xFD2C -#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER6 0xFD30 - -#define S5P_FIMV_E_MVC_FRAME_QP_VIEW1 0xFD40 -#define S5P_FIMV_E_MVC_RC_FRAME_RATE_VIEW1 0xFD44 -#define S5P_FIMV_E_MVC_RC_BIT_RATE_VIEW1 0xFD48 -#define S5P_FIMV_E_MVC_RC_QBOUND_VIEW1 0xFD4C -#define S5P_FIMV_E_MVC_RC_MODE_VIEW1 0xFD50 -#define S5P_FIMV_E_MVC_INTER_VIEW_PREDICTION_ON 0xFD80 - -#define S5P_FIMV_E_VP9_OPTION 0xFD90 -#define S5P_FIMV_E_VP9_FILTER_OPTION 0xFD94 -#define S5P_FIMV_E_VP9_GOLDEN_FRAME_OPTION 0xFD98 -#define S5P_FIMV_E_VP8_OPTION 0xFDB0 -#define S5P_FIMV_E_VP8_FILTER_OPTION 0xFDB4 -#define S5P_FIMV_E_VP8_GOLDEN_FRAME_OPTION 0xFDB8 - -#define S5P_FIMV_E_HEVC_OPTIONS_2 0xFDC4 - -#define S5P_FIMV_E_HEVC_OPTIONS 0xFDD4 -#define S5P_FIMV_E_HEVC_REFRESH_PERIOD 0xFDD8 -#define S5P_FIMV_E_HEVC_CHROMA_QP_OFFSET 0xFDDC -#define S5P_FIMV_E_HEVC_LF_BETA_OFFSET_DIV2 0xFDE0 -#define S5P_FIMV_E_HEVC_LF_TC_OFFSET_DIV2 0xFDE4 -#define S5P_FIMV_E_HEVC_NAL_CONTROL 0xFDE8 - -#define S5P_FIMV_E_VP8_NAL_CONTROL 0xFDF0 -#define S5P_FIMV_E_VP9_NAL_CONTROL 0xFDF4 -#define S5P_FIMV_E_CONTENT_LIGHT_LEVEL_INFO_SEI 0xFDF8 -#define S5P_FIMV_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_0 0xFDFC -#define S5P_FIMV_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_1 0xFE00 -#define S5P_FIMV_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_2 0xFE04 -#define S5P_FIMV_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_3 0xFE08 -#define S5P_FIMV_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_4 0xFE0C -#define S5P_FIMV_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_5 0xFE10 - - -#define S5P_FIMV_REG_CLEAR_BEGIN 0xf000 -#define S5P_FIMV_REG_CLEAR_COUNT 1024 +#define MFC_REG_E_H264_FRAME_PACKING_SEI_INFO 0xFC4C + +#define MFC_REG_E_H264_NAL_CONTROL 0xFD14 +#define MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER0 0xFD18 +#define MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER1 0xFD1C +#define MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER2 0xFD20 +#define MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER3 0xFD24 +#define MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER4 0xFD28 +#define MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER5 0xFD2C +#define MFC_REG_E_HIERARCHICAL_BIT_RATE_LAYER6 0xFD30 + +#define MFC_REG_E_MVC_FRAME_QP_VIEW1 0xFD40 +#define MFC_REG_E_MVC_RC_FRAME_RATE_VIEW1 0xFD44 +#define MFC_REG_E_MVC_RC_BIT_RATE_VIEW1 0xFD48 +#define MFC_REG_E_MVC_RC_QBOUND_VIEW1 0xFD4C +#define MFC_REG_E_MVC_RC_MODE_VIEW1 0xFD50 +#define MFC_REG_E_MVC_INTER_VIEW_PREDICTION_ON 0xFD80 + +#define MFC_REG_E_VP9_OPTION 0xFD90 +#define MFC_REG_E_VP9_FILTER_OPTION 0xFD94 +#define MFC_REG_E_VP9_GOLDEN_FRAME_OPTION 0xFD98 +#define MFC_REG_E_VP8_OPTION 0xFDB0 +#define MFC_REG_E_VP8_FILTER_OPTION 0xFDB4 +#define MFC_REG_E_VP8_GOLDEN_FRAME_OPTION 0xFDB8 + +#define MFC_REG_E_HEVC_OPTIONS_2 0xFDC4 + +#define MFC_REG_E_HEVC_OPTIONS 0xFDD4 +#define MFC_REG_E_HEVC_REFRESH_PERIOD 0xFDD8 +#define MFC_REG_E_HEVC_CHROMA_QP_OFFSET 0xFDDC +#define MFC_REG_E_HEVC_LF_BETA_OFFSET_DIV2 0xFDE0 +#define MFC_REG_E_HEVC_LF_TC_OFFSET_DIV2 0xFDE4 +#define MFC_REG_E_HEVC_NAL_CONTROL 0xFDE8 + +#define MFC_REG_E_VP8_NAL_CONTROL 0xFDF0 +#define MFC_REG_E_VP9_NAL_CONTROL 0xFDF4 +#define MFC_REG_E_CONTENT_LIGHT_LEVEL_INFO_SEI 0xFDF8 +#define MFC_REG_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_0 0xFDFC +#define MFC_REG_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_1 0xFE00 +#define MFC_REG_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_2 0xFE04 +#define MFC_REG_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_3 0xFE08 +#define MFC_REG_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_4 0xFE0C +#define MFC_REG_E_MASTERING_DISPLAY_COLOUR_VOLUME_SEI_5 0xFE10 + + +#define MFC_REG_REG_CLEAR_BEGIN 0xf000 +#define MFC_REG_REG_CLEAR_COUNT 1024 /* Bit Definitions */ -/* 0x1100: S5P_FIMV_HOST2RISC_CMD */ -#define S5P_FIMV_H2R_CMD_EMPTY 0 -#define S5P_FIMV_H2R_CMD_SYS_INIT 1 -#define S5P_FIMV_H2R_CMD_OPEN_INSTANCE 2 -#define S5P_FIMV_H2R_CMD_SEQ_HEADER 3 -#define S5P_FIMV_H2R_CMD_INIT_BUFFERS 4 -#define S5P_FIMV_H2R_CMD_NAL_START 5 -#define S5P_FIMV_H2R_CMD_CLOSE_INSTANCE 6 -#define S5P_FIMV_H2R_CMD_SLEEP 7 -#define S5P_FIMV_H2R_CMD_WAKEUP 8 -#define S5P_FIMV_H2R_CMD_LAST_FRAME 9 -#define S5P_FIMV_H2R_CMD_DPB_FLUSH 10 -#define S5P_FIMV_H2R_CMD_NAL_ABORT 11 -#define S5P_FIMV_H2R_CMD_CACHE_FLUSH 12 -#define S5P_FIMV_H2R_CMD_NAL_QUEUE 13 -#define S5P_FIMV_H2R_CMD_STOP_QUEUE 14 - - -/* 0x1104: S5P_FIMV_RISC2HOST_CMD */ -#define S5P_FIMV_RISC2HOST_CMD_MASK 0x1FFFF -#define S5P_FIMV_R2H_CMD_EMPTY 0 -#define S5P_FIMV_R2H_CMD_SYS_INIT_RET 1 -#define S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET 2 -#define S5P_FIMV_R2H_CMD_SEQ_DONE_RET 3 -#define S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET 4 -#define S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET 6 -#define S5P_FIMV_R2H_CMD_SLEEP_RET 7 -#define S5P_FIMV_R2H_CMD_WAKEUP_RET 8 -#define S5P_FIMV_R2H_CMD_COMPLETE_SEQ_RET 9 -#define S5P_FIMV_R2H_CMD_DPB_FLUSH_RET 10 -#define S5P_FIMV_R2H_CMD_NAL_ABORT_RET 11 -#define S5P_FIMV_R2H_CMD_FW_STATUS_RET 12 -#define S5P_FIMV_R2H_CMD_FRAME_DONE_RET 13 -#define S5P_FIMV_R2H_CMD_FIELD_DONE_RET 14 -#define S5P_FIMV_R2H_CMD_SLICE_DONE_RET 15 -#define S5P_FIMV_R2H_CMD_ENC_BUFFER_FULL_RET 16 -#define S5P_FIMV_R2H_CMD_QUEUE_DONE_RET 17 -#define S5P_FIMV_R2H_CMD_COMPLETE_QUEUE_RET 18 -#define S5P_FIMV_R2H_CMD_CACHE_FLUSH_RET 20 -#define S5P_FIMV_R2H_CMD_ERR_RET 32 - - -/* 0xF000: S5P_FIMV_FW_VERSION */ -#define S5P_FIMV_FW_VER_INFO_MASK 0xFF -#define S5P_FIMV_FW_VER_INFO_SHFT 24 -#define S5P_FIMV_FW_VER_YEAR_MASK 0xFF -#define S5P_FIMV_FW_VER_YEAR_SHFT 16 -#define S5P_FIMV_FW_VER_MONTH_MASK 0xFF -#define S5P_FIMV_FW_VER_MONTH_SHFT 8 -#define S5P_FIMV_FW_VER_DATE_MASK 0xFF -#define S5P_FIMV_FW_VER_DATE_SHFT 0 -#define S5P_FIMV_FW_VER_ALL_MASK 0xFFFFFF -#define S5P_FIMV_FW_VER_ALL_SHFT 0 - - -/* 0xF00C: S5P_FIMV_CODEC_TYPE */ +/* 0x1100: MFC_REG_HOST2RISC_CMD */ +#define MFC_REG_H2R_CMD_EMPTY 0 +#define MFC_REG_H2R_CMD_SYS_INIT 1 +#define MFC_REG_H2R_CMD_OPEN_INSTANCE 2 +#define MFC_REG_H2R_CMD_SEQ_HEADER 3 +#define MFC_REG_H2R_CMD_INIT_BUFFERS 4 +#define MFC_REG_H2R_CMD_NAL_START 5 +#define MFC_REG_H2R_CMD_CLOSE_INSTANCE 6 +#define MFC_REG_H2R_CMD_SLEEP 7 +#define MFC_REG_H2R_CMD_WAKEUP 8 +#define MFC_REG_H2R_CMD_LAST_FRAME 9 +#define MFC_REG_H2R_CMD_DPB_FLUSH 10 +#define MFC_REG_H2R_CMD_NAL_ABORT 11 +#define MFC_REG_H2R_CMD_CACHE_FLUSH 12 +#define MFC_REG_H2R_CMD_NAL_QUEUE 13 +#define MFC_REG_H2R_CMD_STOP_QUEUE 14 + + +/* 0x1104: MFC_REG_RISC2HOST_CMD */ +#define MFC_REG_RISC2HOST_CMD_MASK 0x1FFFF +#define MFC_REG_R2H_CMD_EMPTY 0 +#define MFC_REG_R2H_CMD_SYS_INIT_RET 1 +#define MFC_REG_R2H_CMD_OPEN_INSTANCE_RET 2 +#define MFC_REG_R2H_CMD_SEQ_DONE_RET 3 +#define MFC_REG_R2H_CMD_INIT_BUFFERS_RET 4 +#define MFC_REG_R2H_CMD_CLOSE_INSTANCE_RET 6 +#define MFC_REG_R2H_CMD_SLEEP_RET 7 +#define MFC_REG_R2H_CMD_WAKEUP_RET 8 +#define MFC_REG_R2H_CMD_COMPLETE_SEQ_RET 9 +#define MFC_REG_R2H_CMD_DPB_FLUSH_RET 10 +#define MFC_REG_R2H_CMD_NAL_ABORT_RET 11 +#define MFC_REG_R2H_CMD_FW_STATUS_RET 12 +#define MFC_REG_R2H_CMD_FRAME_DONE_RET 13 +#define MFC_REG_R2H_CMD_FIELD_DONE_RET 14 +#define MFC_REG_R2H_CMD_SLICE_DONE_RET 15 +#define MFC_REG_R2H_CMD_ENC_BUFFER_FULL_RET 16 +#define MFC_REG_R2H_CMD_QUEUE_DONE_RET 17 +#define MFC_REG_R2H_CMD_COMPLETE_QUEUE_RET 18 +#define MFC_REG_R2H_CMD_CACHE_FLUSH_RET 20 +#define MFC_REG_R2H_CMD_ERR_RET 32 + + +/* 0xF000: MFC_REG_FW_VERSION */ +#define MFC_REG_FW_VER_INFO_MASK 0xFF +#define MFC_REG_FW_VER_INFO_SHFT 24 +#define MFC_REG_FW_VER_YEAR_MASK 0xFF +#define MFC_REG_FW_VER_YEAR_SHFT 16 +#define MFC_REG_FW_VER_MONTH_MASK 0xFF +#define MFC_REG_FW_VER_MONTH_SHFT 8 +#define MFC_REG_FW_VER_DATE_MASK 0xFF +#define MFC_REG_FW_VER_DATE_SHFT 0 +#define MFC_REG_FW_VER_ALL_MASK 0xFFFFFF +#define MFC_REG_FW_VER_ALL_SHFT 0 + + +/* 0xF00C: MFC_REG_CODEC_TYPE */ #define MFC_FORMATS_NO_CODEC -1 /* Decoder */ -#define S5P_FIMV_CODEC_H264_DEC 0 -#define S5P_FIMV_CODEC_H264_MVC_DEC 1 -#define S5P_FIMV_CODEC_MPEG4_DEC 3 -#define S5P_FIMV_CODEC_FIMV1_DEC 4 -#define S5P_FIMV_CODEC_FIMV2_DEC 5 -#define S5P_FIMV_CODEC_FIMV3_DEC 6 -#define S5P_FIMV_CODEC_FIMV4_DEC 7 -#define S5P_FIMV_CODEC_H263_DEC 8 -#define S5P_FIMV_CODEC_VC1_RCV_DEC 9 -#define S5P_FIMV_CODEC_VC1_DEC 10 -#define S5P_FIMV_CODEC_MPEG2_DEC 13 -#define S5P_FIMV_CODEC_VP8_DEC 14 -#define S5P_FIMV_CODEC_HEVC_DEC 17 -#define S5P_FIMV_CODEC_VP9_DEC 18 +#define MFC_REG_CODEC_H264_DEC 0 +#define MFC_REG_CODEC_H264_MVC_DEC 1 +#define MFC_REG_CODEC_MPEG4_DEC 3 +#define MFC_REG_CODEC_FIMV1_DEC 4 +#define MFC_REG_CODEC_FIMV2_DEC 5 +#define MFC_REG_CODEC_FIMV3_DEC 6 +#define MFC_REG_CODEC_FIMV4_DEC 7 +#define MFC_REG_CODEC_H263_DEC 8 +#define MFC_REG_CODEC_VC1_RCV_DEC 9 +#define MFC_REG_CODEC_VC1_DEC 10 +#define MFC_REG_CODEC_MPEG2_DEC 13 +#define MFC_REG_CODEC_VP8_DEC 14 +#define MFC_REG_CODEC_HEVC_DEC 17 +#define MFC_REG_CODEC_VP9_DEC 18 /* Encoder */ -#define S5P_FIMV_CODEC_H264_ENC 20 -#define S5P_FIMV_CODEC_H264_MVC_ENC 21 -#define S5P_FIMV_CODEC_MPEG4_ENC 23 -#define S5P_FIMV_CODEC_H263_ENC 24 -#define S5P_FIMV_CODEC_VP8_ENC 25 -#define S5P_FIMV_CODEC_HEVC_ENC 26 -#define S5P_FIMV_CODEC_VP9_ENC 27 - -#define S5P_FIMV_CODEC_BPG_DEC 32 -#define S5P_FIMV_CODEC_BPG_ENC 33 - -/* 0xF028: S5P_FIMV_MFC_VERSION */ -#define S5P_FIMV_MFC_VER_MASK 0xFFFFFFFF -#define S5P_FIMV_MFC_VER_SHFT 0 - - -/* 0xF074: S5P_FIMV_ERROR_CODE */ -#define S5P_FIMV_ERR_STATUS_MASK 0xFFFF -#define S5P_FIMV_ERR_STATUS_SHIFT 0 -#define S5P_FIMV_WARN_STATUS_MASK 0xFFFF -#define S5P_FIMV_WARN_STATUS_SHIFT 16 +#define MFC_REG_CODEC_H264_ENC 20 +#define MFC_REG_CODEC_H264_MVC_ENC 21 +#define MFC_REG_CODEC_MPEG4_ENC 23 +#define MFC_REG_CODEC_H263_ENC 24 +#define MFC_REG_CODEC_VP8_ENC 25 +#define MFC_REG_CODEC_HEVC_ENC 26 +#define MFC_REG_CODEC_VP9_ENC 27 + +#define MFC_REG_CODEC_BPG_DEC 32 +#define MFC_REG_CODEC_BPG_ENC 33 + +/* 0xF028: MFC_REG_MFC_VERSION */ +#define MFC_REG_MFC_VER_MASK 0xFFFFFFFF +#define MFC_REG_MFC_VER_SHFT 0 + + +/* 0xF074: MFC_REG_ERROR_CODE */ +#define MFC_REG_ERR_STATUS_MASK 0xFFFF +#define MFC_REG_ERR_STATUS_SHIFT 0 +#define MFC_REG_WARN_STATUS_MASK 0xFFFF +#define MFC_REG_WARN_STATUS_SHIFT 16 /* Error number */ -#define S5P_FIMV_ERR_BUFFER_FULL 18 -#define S5P_FIMV_ERR_NO_AVAILABLE_DPB 33 -#define S5P_FIMV_ERR_NO_KEY_FRAME 34 -#define S5P_FIMV_ERR_VPS_ONLY_ERROR 42 -#define S5P_FIMV_ERR_INSUFFICIENT_DPB_SIZE 57 -#define S5P_FIMV_ERR_INSUFFICIENT_NUM_DPB 58 -#define S5P_FIMV_ERR_INSUFFICIENT_MV_BUF_SIZE 60 -#define S5P_FIMV_ERR_NULL_SCRATCH 61 -#define S5P_FIMV_ERR_INSUFFICIENT_SCRATCH_BUF_SIZE 62 - -#define S5P_FIMV_ERR_UNSUPPORTED_FEATURE 100 -#define S5P_FIMV_ERR_UNSUPPORTED_RESOLUTION 101 -#define S5P_FIMV_ERR_HEADER_NOT_FOUND 102 -#define S5P_FIMV_ERR_INVAILD_NAL_TYPE 103 -#define S5P_FIMV_ERR_SEQUENCE_HEADER 104 -#define S5P_FIMV_ERR_MFC_TIMEOUT 140 -#define S5P_FIMV_ERR_TS_MUX_TIMEOUT 141 -#define S5P_FIMV_ERR_G2D_TIMEOUT 142 -#define S5P_FIMV_ERR_FRAME_CONCEAL 150 -#define S5P_FIMV_ERR_WARNINGS_START 160 -#define S5P_FIMV_ERR_BROKEN_LINK 161 -#define S5P_FIMV_ERR_SYNC_POINT_NOT_RECEIVED 190 -#define S5P_FIMV_ERR_NON_PAIRED_FIELD 191 -#define S5P_FIMV_ERR_WARNINGS_END 222 - - -/* 0xF0B4: S5P_FIMV_D_DEC_OPTIONS */ -#define S5P_FIMV_D_DEC_OPT_DISPLAY_DELAY_EN_SHIFT 3 -#define S5P_FIMV_D_DEC_OPT_FMO_ASO_CTRL_MASK 0x1 -#define S5P_FIMV_D_DEC_OPT_FMO_ASO_CTRL_SHIFT 4 -#define S5P_FIMV_D_DEC_OPT_IDR_DECODING_MASK 0x1 -#define S5P_FIMV_D_DEC_OPT_IDR_DECODING_SHIFT 6 -#define S5P_FIMV_D_DEC_OPT_DISCARD_RCV_HEADER_SHIFT 7 -#define S5P_FIMV_D_DEC_OPT_CONCEAL_CONTROL_SHIFT 8 -#define S5P_FIMV_D_DEC_OPT_PARALLEL_DISABLE_SHIFT 11 -#define S5P_FIMV_D_DEC_OPT_REALLOC_CONTROL_SHIFT 13 -#define S5P_FIMV_D_DEC_OPT_SPECIAL_PARSING_SHIFT 15 -#define S5P_FIMV_D_DEC_OPT_THUMBNAIL_DECODING 16 - - -/* 0xF0C4: S5P_FIMV_D_SEI_ENABLE */ -#define S5P_FIMV_D_SEI_ENABLE_NEED_INIT_BUFFER_SHIFT 1 -#define S5P_FIMV_D_SEI_ENABLE_RECOVERY_PARSING_SHIFT 2 -#define S5P_FIMV_D_SEI_ENABLE_CONTENT_LIGHT_SHIFT 4 -#define S5P_FIMV_D_SEI_ENABLE_MASTERING_DISPLAY_SHIFT 5 - - -/* 0xF154: S5P_FIMV_D_INIT_BUFFER_OPTIONS */ -#define S5P_FIMV_D_INIT_BUF_OPT_LF_CTRL_MASK 0x3 -#define S5P_FIMV_D_INIT_BUF_OPT_LF_CTRL_SHIFT 1 -#define S5P_FIMV_D_INIT_BUF_OPT_DYNAMIC_DPB_SET_SHIFT 3 -#define S5P_FIMV_D_INIT_BUF_OPT_COPY_NOT_CODED_SHIFT 4 -#define S5P_FIMV_D_INIT_BUF_OPT_DITHERING_EN_SHIFT 6 -#define S5P_FIMV_D_INIT_BUF_OPT_STRIDE_SIZE_ALIGN 7 - - -/* 0xF5AC: S5P_FIMV_D_NAL_START_OPTIONS */ -#define S5P_FIMV_D_NAL_START_OPT_BLACK_BAR_SHIFT 3 - - -/* 0xF608: S5P_FIMV_D_DISPLAY_STATUS */ -#define S5P_FIMV_DISP_STATUS_DISPLAY_STATUS_MASK 0x7 -#define S5P_FIMV_DISP_STATUS_INTERLACE_MASK 0x1 -#define S5P_FIMV_DISP_STATUS_INTERLACE_SHIFT 3 -#define S5P_FIMV_DISP_STATUS_RES_CHANGE_MASK 0x3 -#define S5P_FIMV_DISP_STATUS_RES_CHANGE_SHIFT 4 -#define S5P_FIMV_DISP_STATUS_NEED_DPB_CHANGE_MASK 0x1 -#define S5P_FIMV_DISP_STATUS_NEED_DPB_CHANGE_SHIFT 9 -#define S5P_FIMV_DISP_STATUS_NEED_SCRATCH_CHANGE_MASK 0x1 -#define S5P_FIMV_DISP_STATUS_NEED_SCRATCH_CHANGE_SHIFT 10 -#define S5P_FIMV_DISP_STATUS_NEED_EMPTY_DPB_MASK 0x1 -#define S5P_FIMV_DISP_STATUS_NEED_EMPTY_DPB_SHIFT 12 -#define S5P_FIMV_DISP_STATUS_BLACK_BAR_DETECT_MASK 0x3 -#define S5P_FIMV_DISP_STATUS_BLACK_BAR_DETECT_SHIFT 13 -#define S5P_FIMV_DISP_STATUS_NOT_DETECTED 0x0 -#define S5P_FIMV_DISP_STATUS_BLACK_BAR 0x1 -#define S5P_FIMV_DISP_STATUS_BLACK_SCREEN 0x2 - - -/* 0xF618: S5P_FIMV_D_DISPLAY_FRAME_TYPE */ -#define S5P_FIMV_DISPLAY_FRAME_MASK 0x7 -#define S5P_FIMV_DISPLAY_TEMP_INFO_MASK 0x1 -#define S5P_FIMV_DISPLAY_TEMP_INFO_SHIFT 7 -#define S5P_FIMV_DISPLAY_FRAME_NOT_CODED 0 -#define S5P_FIMV_DISPLAY_FRAME_I 1 -#define S5P_FIMV_DISPLAY_FRAME_P 2 -#define S5P_FIMV_DISPLAY_FRAME_B 3 - - -/* 0xF61C: S5P_FIMV_D_DISPLAY_CROP_INFO1 */ -#define S5P_FIMV_D_SHARED_CROP_LEFT_MASK 0xFFFF -#define S5P_FIMV_D_SHARED_CROP_RIGHT_SHIFT 16 - - -/* 0xF620: S5P_FIMV_D_DISPLAY_CROP_INFO2 */ -#define S5P_FIMV_D_SHARED_CROP_TOP_MASK 0xFFFF -#define S5P_FIMV_D_SHARED_CROP_BOTTOM_SHIFT 16 - - -/* 0xF644: S5P_FIMV_D_DECODED_STATUS */ -#define S5P_FIMV_DEC_STATUS_DECODED_STATUS_MASK 0x7 -#define S5P_FIMV_DEC_STATUS_DECODING_ONLY 0 -#define S5P_FIMV_DEC_STATUS_DECODING_DISPLAY 1 -#define S5P_FIMV_DEC_STATUS_DISPLAY_ONLY 2 -#define S5P_FIMV_DEC_STATUS_DECODING_EMPTY 3 -#define S5P_FIMV_DEC_STATUS_NUM_OF_TILE_MASK 0xF -#define S5P_FIMV_DEC_STATUS_NUM_OF_TILE_SHIFT 15 - - -/* 0xF654: S5P_FIMV_D_DECODED_FRAME_TYPE */ -#define S5P_FIMV_DECODED_FRAME_MASK 0x7 -#define S5P_FIMV_DECODED_FRAME_NOT_CODED 0 -#define S5P_FIMV_DECODED_FRAME_I 1 -#define S5P_FIMV_DECODED_FRAME_P 2 -#define S5P_FIMV_DECODED_FRAME_B 3 - - -/* 0xF660: S5P_FIMV_D_DECODED_PICTURE_PROFILE */ -#define S5P_FIMV_D_DECODED_PIC_PROFILE_MASK 0x1F -#define S5P_FIMV_D_BIT_DEPTH_CHROMA_MINUS8_MASK 0x7 -#define S5P_FIMV_D_BIT_DEPTH_CHROMA_MINUS8_SHIFT 19 -#define S5P_FIMV_D_BIT_DEPTH_LUMA_MINUS8_MASK 0x7 -#define S5P_FIMV_D_BIT_DEPTH_LUMA_MINUS8_SHIFT 16 -#define S5P_FIMV_D_PROFILE_HEVC_MAIN 1 -#define S5P_FIMV_D_PROFILE_HEVC_MAIN_10 2 -#define S5P_FIMV_D_PROFILE_HEVC_RANGE_EXT 4 - - -/* 0xF684: S5P_FIMV_D_CHROMA_FORMAT */ -#define S5P_FIMV_D_CHROMA_FORMAT_MASK 0x3 -#define S5P_FIMV_D_COLOR_RANGE_MASK 0x1 -#define S5P_FIMV_D_COLOR_RANGE_SHIFT 3 -#define S5P_FIMV_D_COLOR_SPACE_MASK 0xF -#define S5P_FIMV_D_COLOR_SPACE_SHIFT 4 -#define S5P_FIMV_D_COLOR_UNKNOWN 0 -#define S5P_FIMV_D_CHROMA_400 0 -#define S5P_FIMV_D_CHROMA_420 1 -#define S5P_FIMV_D_CHROMA_422 2 -#define S5P_FIMV_D_CHROMA_444 3 - - -/* 0xF690: S5P_FIMV_D_H264_INFO */ -#define S5P_FIMV_D_H264_INFO_MBAFF_FRAME_FLAG_SHIFT 9 -#define S5P_FIMV_D_H264_INFO_MBAFF_FRAME_FLAG_MASK 0x1 - - -/* 0xF6D8: S5P_FIMV_D_MVC_VIEW_ID */ -#define S5P_FIMV_D_MVC_VIEW_ID_DISP_MASK 0xFFFF - - -/* 0xF6DC: S5P_FIMV_D_SEI_AVAIL */ -#define S5P_FIMV_D_SEI_AVAIL_FRAME_PACK_MASK 0x1 -#define S5P_FIMV_D_SEI_AVAIL_CONTENT_LIGHT_MASK 0x1 -#define S5P_FIMV_D_SEI_AVAIL_CONTENT_LIGHT_SHIFT 1 -#define S5P_FIMV_D_SEI_AVAIL_MASTERING_DISPLAY_MASK 0x1 -#define S5P_FIMV_D_SEI_AVAIL_MASTERING_DISPLAY_SHIFT 2 - - -/* 0xF70C: S5P_FIMV_D_VIDEO_SIGNAL_TYPE */ -#define S5P_FIMV_D_VIDEO_SIGNAL_TYPE_FLAG_MASK 0x1 -#define S5P_FIMV_D_VIDEO_SIGNAL_TYPE_FLAG_SHIFT 29 -#define S5P_FIMV_D_COLOUR_DESCRIPTION_FLAG_MASK 0x1 -#define S5P_FIMV_D_COLOUR_DESCRIPTION_FLAG_SHIFT 24 - - -/* 0xF738: S5P_FIMV_D_BLACK_BAR_START_POS */ -#define S5P_FIMV_D_BLACK_BAR_START_X_SHIFT 0 -#define S5P_FIMV_D_BLACK_BAR_START_X_MASK 0xFFFF -#define S5P_FIMV_D_BLACK_BAR_START_Y_SHIFT 16 -#define S5P_FIMV_D_BLACK_BAR_START_Y_MASK 0xFFFF - - -/* 0xF73C: S5P_FIMV_D_BLACK_BAR_IMAGE_SIZE */ -#define S5P_FIMV_D_BLACK_BAR_IMAGE_W_SHIFT 0 -#define S5P_FIMV_D_BLACK_BAR_IMAGE_W_MASK 0xFFFF -#define S5P_FIMV_D_BLACK_BAR_IMAGE_H_SHIFT 16 -#define S5P_FIMV_D_BLACK_BAR_IMAGE_H_MASK 0xFFFF - - -/* 0xF780: S5P_FIMV_E_FRAME_CROP_OFFSET */ -#define S5P_FIMV_E_FRAME_CROP_OFFSET_TOP 16 -#define S5P_FIMV_E_FRAME_CROP_OFFSET_LEFT 0 -#define S5P_FIMV_E_FRAME_CROP_OFFSET_MASK 0x3FFF +#define MFC_REG_ERR_BUFFER_FULL 18 +#define MFC_REG_ERR_NO_AVAILABLE_DPB 33 +#define MFC_REG_ERR_NO_KEY_FRAME 34 +#define MFC_REG_ERR_VPS_ONLY_ERROR 42 +#define MFC_REG_ERR_INSUFFICIENT_DPB_SIZE 57 +#define MFC_REG_ERR_INSUFFICIENT_NUM_DPB 58 +#define MFC_REG_ERR_INSUFFICIENT_MV_BUF_SIZE 60 +#define MFC_REG_ERR_NULL_SCRATCH 61 +#define MFC_REG_ERR_INSUFFICIENT_SCRATCH_BUF_SIZE 62 + +#define MFC_REG_ERR_UNSUPPORTED_FEATURE 100 +#define MFC_REG_ERR_UNSUPPORTED_RESOLUTION 101 +#define MFC_REG_ERR_HEADER_NOT_FOUND 102 +#define MFC_REG_ERR_INVAILD_NAL_TYPE 103 +#define MFC_REG_ERR_SEQUENCE_HEADER 104 +#define MFC_REG_ERR_MFC_TIMEOUT 140 +#define MFC_REG_ERR_TS_MUX_TIMEOUT 141 +#define MFC_REG_ERR_G2D_TIMEOUT 142 +#define MFC_REG_ERR_FRAME_CONCEAL 150 +#define MFC_REG_ERR_WARNINGS_START 160 +#define MFC_REG_ERR_BROKEN_LINK 161 +#define MFC_REG_ERR_SYNC_POINT_NOT_RECEIVED 190 +#define MFC_REG_ERR_NON_PAIRED_FIELD 191 +#define MFC_REG_ERR_WARNINGS_END 222 + + +/* 0xF0B4: MFC_REG_D_DEC_OPTIONS */ +#define MFC_REG_D_DEC_OPT_DISPLAY_DELAY_EN_SHIFT 3 +#define MFC_REG_D_DEC_OPT_FMO_ASO_CTRL_MASK 0x1 +#define MFC_REG_D_DEC_OPT_FMO_ASO_CTRL_SHIFT 4 +#define MFC_REG_D_DEC_OPT_IDR_DECODING_MASK 0x1 +#define MFC_REG_D_DEC_OPT_IDR_DECODING_SHIFT 6 +#define MFC_REG_D_DEC_OPT_DISCARD_RCV_HEADER_SHIFT 7 +#define MFC_REG_D_DEC_OPT_CONCEAL_CONTROL_SHIFT 8 +#define MFC_REG_D_DEC_OPT_PARALLEL_DISABLE_SHIFT 11 +#define MFC_REG_D_DEC_OPT_REALLOC_CONTROL_SHIFT 13 +#define MFC_REG_D_DEC_OPT_SPECIAL_PARSING_SHIFT 15 +#define MFC_REG_D_DEC_OPT_THUMBNAIL_DECODING 16 + + +/* 0xF0C4: MFC_REG_D_SEI_ENABLE */ +#define MFC_REG_D_SEI_ENABLE_NEED_INIT_BUFFER_SHIFT 1 +#define MFC_REG_D_SEI_ENABLE_RECOVERY_PARSING_SHIFT 2 +#define MFC_REG_D_SEI_ENABLE_CONTENT_LIGHT_SHIFT 4 +#define MFC_REG_D_SEI_ENABLE_MASTERING_DISPLAY_SHIFT 5 + + +/* 0xF154: MFC_REG_D_INIT_BUFFER_OPTIONS */ +#define MFC_REG_D_INIT_BUF_OPT_LF_CTRL_MASK 0x3 +#define MFC_REG_D_INIT_BUF_OPT_LF_CTRL_SHIFT 1 +#define MFC_REG_D_INIT_BUF_OPT_DYNAMIC_DPB_SET_SHIFT 3 +#define MFC_REG_D_INIT_BUF_OPT_COPY_NOT_CODED_SHIFT 4 +#define MFC_REG_D_INIT_BUF_OPT_DITHERING_EN_SHIFT 6 +#define MFC_REG_D_INIT_BUF_OPT_STRIDE_SIZE_ALIGN 7 + + +/* 0xF5AC: MFC_REG_D_NAL_START_OPTIONS */ +#define MFC_REG_D_NAL_START_OPT_BLACK_BAR_SHIFT 3 + + +/* 0xF608: MFC_REG_D_DISPLAY_STATUS */ +#define MFC_REG_DISP_STATUS_DISPLAY_STATUS_MASK 0x7 +#define MFC_REG_DISP_STATUS_INTERLACE_MASK 0x1 +#define MFC_REG_DISP_STATUS_INTERLACE_SHIFT 3 +#define MFC_REG_DISP_STATUS_RES_CHANGE_MASK 0x3 +#define MFC_REG_DISP_STATUS_RES_CHANGE_SHIFT 4 +#define MFC_REG_DISP_STATUS_NEED_DPB_CHANGE_MASK 0x1 +#define MFC_REG_DISP_STATUS_NEED_DPB_CHANGE_SHIFT 9 +#define MFC_REG_DISP_STATUS_NEED_SCRATCH_CHANGE_MASK 0x1 +#define MFC_REG_DISP_STATUS_NEED_SCRATCH_CHANGE_SHIFT 10 +#define MFC_REG_DISP_STATUS_NEED_EMPTY_DPB_MASK 0x1 +#define MFC_REG_DISP_STATUS_NEED_EMPTY_DPB_SHIFT 12 +#define MFC_REG_DISP_STATUS_BLACK_BAR_DETECT_MASK 0x3 +#define MFC_REG_DISP_STATUS_BLACK_BAR_DETECT_SHIFT 13 +#define MFC_REG_DISP_STATUS_NOT_DETECTED 0x0 +#define MFC_REG_DISP_STATUS_BLACK_BAR 0x1 +#define MFC_REG_DISP_STATUS_BLACK_SCREEN 0x2 + + +/* 0xF618: MFC_REG_D_DISPLAY_FRAME_TYPE */ +#define MFC_REG_DISPLAY_FRAME_MASK 0x7 +#define MFC_REG_DISPLAY_TEMP_INFO_MASK 0x1 +#define MFC_REG_DISPLAY_TEMP_INFO_SHIFT 7 +#define MFC_REG_DISPLAY_FRAME_NOT_CODED 0 +#define MFC_REG_DISPLAY_FRAME_I 1 +#define MFC_REG_DISPLAY_FRAME_P 2 +#define MFC_REG_DISPLAY_FRAME_B 3 + + +/* 0xF61C: MFC_REG_D_DISPLAY_CROP_INFO1 */ +#define MFC_REG_D_SHARED_CROP_LEFT_MASK 0xFFFF +#define MFC_REG_D_SHARED_CROP_RIGHT_SHIFT 16 + + +/* 0xF620: MFC_REG_D_DISPLAY_CROP_INFO2 */ +#define MFC_REG_D_SHARED_CROP_TOP_MASK 0xFFFF +#define MFC_REG_D_SHARED_CROP_BOTTOM_SHIFT 16 + + +/* 0xF644: MFC_REG_D_DECODED_STATUS */ +#define MFC_REG_DEC_STATUS_DECODED_STATUS_MASK 0x7 +#define MFC_REG_DEC_STATUS_DECODING_ONLY 0 +#define MFC_REG_DEC_STATUS_DECODING_DISPLAY 1 +#define MFC_REG_DEC_STATUS_DISPLAY_ONLY 2 +#define MFC_REG_DEC_STATUS_DECODING_EMPTY 3 +#define MFC_REG_DEC_STATUS_NUM_OF_TILE_MASK 0xF +#define MFC_REG_DEC_STATUS_NUM_OF_TILE_SHIFT 15 + + +/* 0xF654: MFC_REG_D_DECODED_FRAME_TYPE */ +#define MFC_REG_DECODED_FRAME_MASK 0x7 +#define MFC_REG_DECODED_FRAME_NOT_CODED 0 +#define MFC_REG_DECODED_FRAME_I 1 +#define MFC_REG_DECODED_FRAME_P 2 +#define MFC_REG_DECODED_FRAME_B 3 + + +/* 0xF660: MFC_REG_D_DECODED_PICTURE_PROFILE */ +#define MFC_REG_D_DECODED_PIC_PROFILE_MASK 0x1F +#define MFC_REG_D_BIT_DEPTH_CHROMA_MINUS8_MASK 0x7 +#define MFC_REG_D_BIT_DEPTH_CHROMA_MINUS8_SHIFT 19 +#define MFC_REG_D_BIT_DEPTH_LUMA_MINUS8_MASK 0x7 +#define MFC_REG_D_BIT_DEPTH_LUMA_MINUS8_SHIFT 16 +#define MFC_REG_D_PROFILE_HEVC_MAIN 1 +#define MFC_REG_D_PROFILE_HEVC_MAIN_10 2 +#define MFC_REG_D_PROFILE_HEVC_RANGE_EXT 4 + + +/* 0xF684: MFC_REG_D_CHROMA_FORMAT */ +#define MFC_REG_D_CHROMA_FORMAT_MASK 0x3 +#define MFC_REG_D_COLOR_RANGE_MASK 0x1 +#define MFC_REG_D_COLOR_RANGE_SHIFT 3 +#define MFC_REG_D_COLOR_SPACE_MASK 0xF +#define MFC_REG_D_COLOR_SPACE_SHIFT 4 +#define MFC_REG_D_COLOR_UNKNOWN 0 +#define MFC_REG_D_CHROMA_400 0 +#define MFC_REG_D_CHROMA_420 1 +#define MFC_REG_D_CHROMA_422 2 +#define MFC_REG_D_CHROMA_444 3 + + +/* 0xF690: MFC_REG_D_H264_INFO */ +#define MFC_REG_D_H264_INFO_MBAFF_FRAME_FLAG_SHIFT 9 +#define MFC_REG_D_H264_INFO_MBAFF_FRAME_FLAG_MASK 0x1 + + +/* 0xF6D8: MFC_REG_D_MVC_VIEW_ID */ +#define MFC_REG_D_MVC_VIEW_ID_DISP_MASK 0xFFFF + + +/* 0xF6DC: MFC_REG_D_SEI_AVAIL */ +#define MFC_REG_D_SEI_AVAIL_FRAME_PACK_MASK 0x1 +#define MFC_REG_D_SEI_AVAIL_CONTENT_LIGHT_MASK 0x1 +#define MFC_REG_D_SEI_AVAIL_CONTENT_LIGHT_SHIFT 1 +#define MFC_REG_D_SEI_AVAIL_MASTERING_DISPLAY_MASK 0x1 +#define MFC_REG_D_SEI_AVAIL_MASTERING_DISPLAY_SHIFT 2 + + +/* 0xF70C: MFC_REG_D_VIDEO_SIGNAL_TYPE */ +#define MFC_REG_D_VIDEO_SIGNAL_TYPE_FLAG_MASK 0x1 +#define MFC_REG_D_VIDEO_SIGNAL_TYPE_FLAG_SHIFT 29 +#define MFC_REG_D_COLOUR_DESCRIPTION_FLAG_MASK 0x1 +#define MFC_REG_D_COLOUR_DESCRIPTION_FLAG_SHIFT 24 + + +/* 0xF738: MFC_REG_D_BLACK_BAR_START_POS */ +#define MFC_REG_D_BLACK_BAR_START_X_SHIFT 0 +#define MFC_REG_D_BLACK_BAR_START_X_MASK 0xFFFF +#define MFC_REG_D_BLACK_BAR_START_Y_SHIFT 16 +#define MFC_REG_D_BLACK_BAR_START_Y_MASK 0xFFFF + + +/* 0xF73C: MFC_REG_D_BLACK_BAR_IMAGE_SIZE */ +#define MFC_REG_D_BLACK_BAR_IMAGE_W_SHIFT 0 +#define MFC_REG_D_BLACK_BAR_IMAGE_W_MASK 0xFFFF +#define MFC_REG_D_BLACK_BAR_IMAGE_H_SHIFT 16 +#define MFC_REG_D_BLACK_BAR_IMAGE_H_MASK 0xFFFF + + +/* 0xF780: MFC_REG_E_FRAME_CROP_OFFSET */ +#define MFC_REG_E_FRAME_CROP_OFFSET_TOP 16 +#define MFC_REG_E_FRAME_CROP_OFFSET_LEFT 0 +#define MFC_REG_E_FRAME_CROP_OFFSET_MASK 0x3FFF -/* 0xF788: S5P_FIMV_E_PICTURE_PROFILE */ -#define S5P_FIMV_E_PROFILE_H264_BASELINE 0 -#define S5P_FIMV_E_PROFILE_H264_MAIN 1 -#define S5P_FIMV_E_PROFILE_H264_HIGH 2 -#define S5P_FIMV_E_PROFILE_H264_CONSTRAINED_BASELINE 3 -#define S5P_FIMV_E_PROFILE_H264_CONSTRAINED_HIGH 5 -#define S5P_FIMV_E_PROFILE_MPEG4_SIMPLE 0 -#define S5P_FIMV_E_PROFILE_MPEG4_ADVANCED_SIMPLE 1 -#define S5P_FIMV_E_PROFILE_HEVC_MAIN_422_10_INTRA 2 -#define S5P_FIMV_E_PROFILE_HEVC_MAIN_10 3 -#define S5P_FIMV_E_PROFILE_HEVC_MAIN_422_10 4 -#define S5P_FIMV_E_PROFILE_VP9_PROFILE0 0 -#define S5P_FIMV_E_PROFILE_VP9_PROFILE1 1 -#define S5P_FIMV_E_PROFILE_VP9_PROFILE2 2 -#define S5P_FIMV_E_PROFILE_VP9_PROFILE3 3 - - -/* 0xF7A4: S5P_FIMV_E_RC_MODE */ -#define S5P_FIMV_E_RC_CBR_FIX 0 -#define S5P_FIMV_E_RC_CBR_VAR 1 -#define S5P_FIMV_E_RC_VBR 2 -#define S5P_FIMV_E_RC_CBR_I_LIMIT 3 - - -/* 0xFA84: S5P_FIMV_E_SLICE_TYPE */ -#define S5P_FIMV_E_SLICE_TYPE_NOT_CODED 0 -#define S5P_FIMV_E_SLICE_TYPE_I 1 -#define S5P_FIMV_E_SLICE_TYPE_P 2 -#define S5P_FIMV_E_SLICE_TYPE_B 3 -#define S5P_FIMV_E_SLICE_TYPE_SKIPPED 4 +/* 0xF788: MFC_REG_E_PICTURE_PROFILE */ +#define MFC_REG_E_PROFILE_H264_BASELINE 0 +#define MFC_REG_E_PROFILE_H264_MAIN 1 +#define MFC_REG_E_PROFILE_H264_HIGH 2 +#define MFC_REG_E_PROFILE_H264_CONSTRAINED_BASELINE 3 +#define MFC_REG_E_PROFILE_H264_CONSTRAINED_HIGH 5 +#define MFC_REG_E_PROFILE_MPEG4_SIMPLE 0 +#define MFC_REG_E_PROFILE_MPEG4_ADVANCED_SIMPLE 1 +#define MFC_REG_E_PROFILE_HEVC_MAIN_422_10_INTRA 2 +#define MFC_REG_E_PROFILE_HEVC_MAIN_10 3 +#define MFC_REG_E_PROFILE_HEVC_MAIN_422_10 4 +#define MFC_REG_E_PROFILE_VP9_PROFILE0 0 +#define MFC_REG_E_PROFILE_VP9_PROFILE1 1 +#define MFC_REG_E_PROFILE_VP9_PROFILE2 2 +#define MFC_REG_E_PROFILE_VP9_PROFILE3 3 + + +/* 0xF7A4: MFC_REG_E_RC_MODE */ +#define MFC_REG_E_RC_CBR_FIX 0 +#define MFC_REG_E_RC_CBR_VAR 1 +#define MFC_REG_E_RC_VBR 2 +#define MFC_REG_E_RC_CBR_I_LIMIT 3 + + +/* 0xFA84: MFC_REG_E_SLICE_TYPE */ +#define MFC_REG_E_SLICE_TYPE_NOT_CODED 0 +#define MFC_REG_E_SLICE_TYPE_I 1 +#define MFC_REG_E_SLICE_TYPE_P 2 +#define MFC_REG_E_SLICE_TYPE_B 3 +#define MFC_REG_E_SLICE_TYPE_SKIPPED 4 #endif /* __REGS_MFC_V10_H */ diff --git a/drivers/media/platform/exynos/mfc/mfc_sync.c b/drivers/media/platform/exynos/mfc/mfc_sync.c index bc7b192a42d6..0a7669b053b6 100644 --- a/drivers/media/platform/exynos/mfc/mfc_sync.c +++ b/drivers/media/platform/exynos/mfc/mfc_sync.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_intr.c + * drivers/media/platform/exynos/mfc/mfc_intr.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -19,35 +19,35 @@ #define R2H_BIT(x) (((x) > 0) ? (1 << ((x) - 1)) : 0) -static inline unsigned int mfc_r2h_bit_mask(int cmd) +static inline unsigned int __mfc_r2h_bit_mask(int cmd) { unsigned int mask = R2H_BIT(cmd); - if (cmd == S5P_FIMV_R2H_CMD_FRAME_DONE_RET) - mask |= (R2H_BIT(S5P_FIMV_R2H_CMD_FIELD_DONE_RET) | - R2H_BIT(S5P_FIMV_R2H_CMD_COMPLETE_SEQ_RET) | - R2H_BIT(S5P_FIMV_R2H_CMD_SLICE_DONE_RET) | - R2H_BIT(S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET) | - R2H_BIT(S5P_FIMV_R2H_CMD_ENC_BUFFER_FULL_RET)); + if (cmd == MFC_REG_R2H_CMD_FRAME_DONE_RET) + mask |= (R2H_BIT(MFC_REG_R2H_CMD_FIELD_DONE_RET) | + R2H_BIT(MFC_REG_R2H_CMD_COMPLETE_SEQ_RET) | + R2H_BIT(MFC_REG_R2H_CMD_SLICE_DONE_RET) | + R2H_BIT(MFC_REG_R2H_CMD_INIT_BUFFERS_RET) | + R2H_BIT(MFC_REG_R2H_CMD_ENC_BUFFER_FULL_RET)); /* FIXME: Temporal mask for S3D SEI processing */ - else if (cmd == S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET) - mask |= (R2H_BIT(S5P_FIMV_R2H_CMD_FIELD_DONE_RET) | - R2H_BIT(S5P_FIMV_R2H_CMD_SLICE_DONE_RET) | - R2H_BIT(S5P_FIMV_R2H_CMD_FRAME_DONE_RET)); + else if (cmd == MFC_REG_R2H_CMD_INIT_BUFFERS_RET) + mask |= (R2H_BIT(MFC_REG_R2H_CMD_FIELD_DONE_RET) | + R2H_BIT(MFC_REG_R2H_CMD_SLICE_DONE_RET) | + R2H_BIT(MFC_REG_R2H_CMD_FRAME_DONE_RET)); - return (mask |= R2H_BIT(S5P_FIMV_R2H_CMD_ERR_RET)); + return (mask |= R2H_BIT(MFC_REG_R2H_CMD_ERR_RET)); } #define wait_condition(x, c) (x->int_condition && \ - (R2H_BIT(x->int_reason) & mfc_r2h_bit_mask(c))) -#define is_err_cond(x) ((x->int_condition) && (x->int_reason == S5P_FIMV_R2H_CMD_ERR_RET)) + (R2H_BIT(x->int_reason) & __mfc_r2h_bit_mask(c))) +#define is_err_cond(x) ((x->int_condition) && (x->int_reason == MFC_REG_R2H_CMD_ERR_RET)) /* * Return value description * 0: waked up before timeout * 1: failed to get the response for the command before timeout */ -int s5p_mfc_wait_for_done_dev(struct s5p_mfc_dev *dev, int command) +int mfc_wait_for_done_dev(struct mfc_dev *dev, int command) { int ret; @@ -57,7 +57,7 @@ int s5p_mfc_wait_for_done_dev(struct s5p_mfc_dev *dev, int command) if (ret == 0) { mfc_err_dev("Interrupt (dev->int_reason:%d, command:%d) timed out\n", dev->int_reason, command); - if (s5p_mfc_check_risc2host(dev)) { + if (mfc_check_risc2host(dev)) { ret = wait_event_timeout(dev->cmd_wq, wait_condition(dev, command), msecs_to_jiffies(MFC_INT_TIMEOUT * MFC_INT_TIMEOUT_CNT)); @@ -84,13 +84,13 @@ wait_done: * 1: failed to get the response for the command before timeout * -1: got the error response for the command before timeout */ -int s5p_mfc_wait_for_done_ctx(struct s5p_mfc_ctx *ctx, int command) +int mfc_wait_for_done_ctx(struct mfc_ctx *ctx, int command) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; int ret; unsigned int timeout = MFC_INT_TIMEOUT; - if (command == S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET) + if (command == MFC_REG_R2H_CMD_CLOSE_INSTANCE_RET) timeout = MFC_INT_SHORT_TIMEOUT; ret = wait_event_timeout(ctx->cmd_wq, @@ -99,7 +99,7 @@ int s5p_mfc_wait_for_done_ctx(struct s5p_mfc_ctx *ctx, int command) if (ret == 0) { mfc_err_ctx("Interrupt (ctx->int_reason:%d, command:%d) timed out\n", ctx->int_reason, command); - if (s5p_mfc_check_risc2host(dev)) { + if (mfc_check_risc2host(dev)) { ret = wait_event_timeout(ctx->cmd_wq, wait_condition(ctx, command), msecs_to_jiffies(MFC_INT_TIMEOUT * MFC_INT_TIMEOUT_CNT)); @@ -129,7 +129,7 @@ wait_done: } /* Wake up device wait_queue */ -void s5p_mfc_wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason, +void mfc_wake_up_dev(struct mfc_dev *dev, unsigned int reason, unsigned int err) { if (!dev) { @@ -144,7 +144,7 @@ void s5p_mfc_wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason, } /* Wake up context wait_queue */ -void s5p_mfc_wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason, +void mfc_wake_up_ctx(struct mfc_ctx *ctx, unsigned int reason, unsigned int err) { if (!ctx) { @@ -158,7 +158,7 @@ void s5p_mfc_wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason, wake_up(&ctx->cmd_wq); } -int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev) +int mfc_get_new_ctx(struct mfc_dev *dev) { unsigned long wflags; int new_ctx_index = 0; @@ -206,28 +206,28 @@ int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev) } /* Check whether a context should be run on hardware */ -int s5p_mfc_dec_ctx_ready(struct s5p_mfc_ctx *ctx) +int mfc_dec_ctx_ready(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; int src_buf_queue_greater_than_0 = 0; int dst_buf_queue_greater_than_0 = 0; int ref_buf_queue_same_dpb_count_plus_5 = 0; mfc_debug(1, "[c:%d] src = %d, dst = %d, src_nal = %d, dst_nal = %d, ref = %d, state = %d, capstat = %d\n", - ctx->num, s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_queue), - s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_queue), - s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_nal_queue), - s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_nal_queue), - s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->ref_buf_queue), + ctx->num, mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_nal_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_nal_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->ref_buf_queue), ctx->state, ctx->capture_state); mfc_debug(2, "wait_state = %d\n", ctx->wait_state); src_buf_queue_greater_than_0 - = s5p_mfc_is_queue_count_greater(&ctx->buf_queue_lock, &ctx->src_buf_queue, 0); + = mfc_is_queue_count_greater(&ctx->buf_queue_lock, &ctx->src_buf_queue, 0); dst_buf_queue_greater_than_0 - = s5p_mfc_is_queue_count_greater(&ctx->buf_queue_lock, &ctx->dst_buf_queue, 0); + = mfc_is_queue_count_greater(&ctx->buf_queue_lock, &ctx->dst_buf_queue, 0); ref_buf_queue_same_dpb_count_plus_5 - = s5p_mfc_is_queue_count_same(&ctx->buf_queue_lock, &ctx->ref_buf_queue, (ctx->dpb_count + 5)); + = mfc_is_queue_count_same(&ctx->buf_queue_lock, &ctx->ref_buf_queue, (ctx->dpb_count + 5)); /* If shutdown is called, do not try any cmd */ if (dev->shutdown) @@ -263,32 +263,32 @@ int s5p_mfc_dec_ctx_ready(struct s5p_mfc_ctx *ctx) src_buf_queue_greater_than_0) return 1; - s5p_mfc_perf_cancel_drv_margin(dev); + mfc_perf_cancel_drv_margin(dev); mfc_debug(2, "ctx is not ready\n"); return 0; } -int s5p_mfc_enc_ctx_ready(struct s5p_mfc_ctx *ctx) +int mfc_enc_ctx_ready(struct mfc_ctx *ctx) { - struct s5p_mfc_enc *enc = ctx->enc_priv; - struct s5p_mfc_dev *dev = ctx->dev; - struct s5p_mfc_enc_params *p = &enc->params; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_dev *dev = ctx->dev; + struct mfc_enc_params *p = &enc->params; int src_buf_queue_greater_than_0 = 0; int dst_buf_queue_greater_than_0 = 0; mfc_debug(1, "[c:%d] src = %d, dst = %d, src_nal = %d, dst_nal = %d, ref = %d, state = %d\n", - ctx->num, s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_queue), - s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_queue), - s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_nal_queue), - s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_nal_queue), - s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->ref_buf_queue), + ctx->num, mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_nal_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_nal_queue), + mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->ref_buf_queue), ctx->state); src_buf_queue_greater_than_0 - = s5p_mfc_is_queue_count_greater(&ctx->buf_queue_lock, &ctx->src_buf_queue, 0); + = mfc_is_queue_count_greater(&ctx->buf_queue_lock, &ctx->src_buf_queue, 0); dst_buf_queue_greater_than_0 - = s5p_mfc_is_queue_count_greater(&ctx->buf_queue_lock, &ctx->dst_buf_queue, 0); + = mfc_is_queue_count_greater(&ctx->buf_queue_lock, &ctx->dst_buf_queue, 0); /* If shutdown is called, do not try any cmd */ if (dev->shutdown) @@ -325,18 +325,18 @@ int s5p_mfc_enc_ctx_ready(struct s5p_mfc_ctx *ctx) src_buf_queue_greater_than_0 && dst_buf_queue_greater_than_0) return 1; - s5p_mfc_perf_cancel_drv_margin(dev); + mfc_perf_cancel_drv_margin(dev); mfc_debug(2, "ctx is not ready\n"); return 0; } -int s5p_mfc_ctx_ready(struct s5p_mfc_ctx *ctx) +int mfc_ctx_ready(struct mfc_ctx *ctx) { if (ctx->type == MFCINST_DECODER) - return s5p_mfc_dec_ctx_ready(ctx); + return mfc_dec_ctx_ready(ctx); else if (ctx->type == MFCINST_ENCODER) - return s5p_mfc_enc_ctx_ready(ctx); + return mfc_enc_ctx_ready(ctx); return 0; } diff --git a/drivers/media/platform/exynos/mfc/mfc_sync.h b/drivers/media/platform/exynos/mfc/mfc_sync.h index 5c99de6e9d1c..21f333dd4c0e 100644 --- a/drivers/media/platform/exynos/mfc/mfc_sync.h +++ b/drivers/media/platform/exynos/mfc/mfc_sync.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_intr.h + * drivers/media/platform/exynos/mfc/mfc_intr.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -36,20 +36,20 @@ (ctx->state == MFCINST_RUNNING) || \ (ctx->state == MFCINST_FINISHING)) -int s5p_mfc_wait_for_done_dev(struct s5p_mfc_dev *dev, int command); -int s5p_mfc_wait_for_done_ctx(struct s5p_mfc_ctx *ctx, int command); -void s5p_mfc_wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason, +int mfc_wait_for_done_dev(struct mfc_dev *dev, int command); +int mfc_wait_for_done_ctx(struct mfc_ctx *ctx, int command); +void mfc_wake_up_dev(struct mfc_dev *dev, unsigned int reason, unsigned int err); -void s5p_mfc_wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason, +void mfc_wake_up_ctx(struct mfc_ctx *ctx, unsigned int reason, unsigned int err); -int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev); -int s5p_mfc_dec_ctx_ready(struct s5p_mfc_ctx *ctx); -int s5p_mfc_enc_ctx_ready(struct s5p_mfc_ctx *ctx); -int s5p_mfc_ctx_ready(struct s5p_mfc_ctx *ctx); +int mfc_get_new_ctx(struct mfc_dev *dev); +int mfc_dec_ctx_ready(struct mfc_ctx *ctx); +int mfc_enc_ctx_ready(struct mfc_ctx *ctx); +int mfc_ctx_ready(struct mfc_ctx *ctx); -static inline void s5p_mfc_set_bit(int num, struct s5p_mfc_bits *data) +static inline void mfc_set_bit(int num, struct mfc_bits *data) { unsigned long flags; spin_lock_irqsave(&data->lock, flags); @@ -57,7 +57,7 @@ static inline void s5p_mfc_set_bit(int num, struct s5p_mfc_bits *data) spin_unlock_irqrestore(&data->lock, flags); } -static inline void s5p_mfc_clear_bit(int num, struct s5p_mfc_bits *data) +static inline void mfc_clear_bit(int num, struct mfc_bits *data) { unsigned long flags; spin_lock_irqsave(&data->lock, flags); @@ -65,7 +65,7 @@ static inline void s5p_mfc_clear_bit(int num, struct s5p_mfc_bits *data) spin_unlock_irqrestore(&data->lock, flags); } -static inline int s5p_mfc_test_bit(int num, struct s5p_mfc_bits *data) +static inline int mfc_test_bit(int num, struct mfc_bits *data) { unsigned long flags; int ret; @@ -75,7 +75,7 @@ static inline int s5p_mfc_test_bit(int num, struct s5p_mfc_bits *data) return ret; } -static inline int s5p_mfc_is_all_bits_cleared(struct s5p_mfc_bits *data) +static inline int mfc_is_all_bits_cleared(struct mfc_bits *data) { unsigned long flags; int ret; @@ -85,7 +85,7 @@ static inline int s5p_mfc_is_all_bits_cleared(struct s5p_mfc_bits *data) return ret; } -static inline void s5p_mfc_clear_all_bits(struct s5p_mfc_bits *data) +static inline void mfc_clear_all_bits(struct mfc_bits *data) { unsigned long flags; spin_lock_irqsave(&data->lock, flags); @@ -93,7 +93,7 @@ static inline void s5p_mfc_clear_all_bits(struct s5p_mfc_bits *data) spin_unlock_irqrestore(&data->lock, flags); } -static inline unsigned long s5p_mfc_get_bits(struct s5p_mfc_bits *data) +static inline unsigned long mfc_get_bits(struct mfc_bits *data) { unsigned long flags; unsigned long ret; @@ -103,20 +103,20 @@ static inline unsigned long s5p_mfc_get_bits(struct s5p_mfc_bits *data) return ret; } -static inline void s5p_mfc_create_bits(struct s5p_mfc_bits *data) +static inline void mfc_create_bits(struct mfc_bits *data) { spin_lock_init(&data->lock); - s5p_mfc_clear_all_bits(data); + mfc_clear_all_bits(data); } -static inline void s5p_mfc_delete_bits(struct s5p_mfc_bits *data) +static inline void mfc_delete_bits(struct mfc_bits *data) { - s5p_mfc_clear_all_bits(data); + mfc_clear_all_bits(data); } -static inline int s5p_mfc_is_work_to_do(struct s5p_mfc_dev *dev) +static inline int mfc_is_work_to_do(struct mfc_dev *dev) { - return (!s5p_mfc_is_all_bits_cleared(&dev->work_bits)); + return (!mfc_is_all_bits_cleared(&dev->work_bits)); } #endif /* __MFC_INTR_H */ diff --git a/drivers/media/platform/exynos/mfc/mfc_utils.c b/drivers/media/platform/exynos/mfc/mfc_utils.c index 226147764353..838e322e2310 100644 --- a/drivers/media/platform/exynos/mfc/mfc_utils.c +++ b/drivers/media/platform/exynos/mfc/mfc_utils.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_utils.c + * drivers/media/platform/exynos/mfc/mfc_utils.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -14,7 +14,7 @@ #include "mfc_utils.h" -int s5p_mfc_check_vb_with_fmt(struct s5p_mfc_fmt *fmt, struct vb2_buffer *vb) +int mfc_check_vb_with_fmt(struct mfc_fmt *fmt, struct vb2_buffer *vb) { if (!fmt) return -EINVAL; @@ -28,23 +28,23 @@ int s5p_mfc_check_vb_with_fmt(struct s5p_mfc_fmt *fmt, struct vb2_buffer *vb) return 0; } -int mfc_stream_buf_prot(struct s5p_mfc_ctx *ctx, - struct s5p_mfc_buf *buf, bool en) +int __mfc_stream_buf_prot(struct mfc_ctx *ctx, + struct mfc_buf *buf, bool en) { return 0; } -int mfc_raw_buf_prot(struct s5p_mfc_ctx *ctx, - struct s5p_mfc_buf *buf, bool en) +int __mfc_raw_buf_prot(struct mfc_ctx *ctx, + struct mfc_buf *buf, bool en) { return 0; } -void s5p_mfc_raw_protect(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *mfc_buf, +void mfc_raw_protect(struct mfc_ctx *ctx, struct mfc_buf *mfc_buf, int index) { if (!test_bit(index, &ctx->raw_protect_flag)) { - if (mfc_raw_buf_prot(ctx, mfc_buf, true)) { + if (__mfc_raw_buf_prot(ctx, mfc_buf, true)) { mfc_err_ctx("failed to CFW_PROT\n"); } else { set_bit(index, &ctx->raw_protect_flag); @@ -54,11 +54,11 @@ void s5p_mfc_raw_protect(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *mfc_buf, } } -void s5p_mfc_raw_unprotect(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *mfc_buf, +void mfc_raw_unprotect(struct mfc_ctx *ctx, struct mfc_buf *mfc_buf, int index) { if (test_bit(index, &ctx->raw_protect_flag)) { - if (mfc_raw_buf_prot(ctx, mfc_buf, false)) { + if (__mfc_raw_buf_prot(ctx, mfc_buf, false)) { mfc_err_ctx("failed to CFW_UNPROT\n"); } else { clear_bit(index, &ctx->raw_protect_flag); @@ -68,11 +68,11 @@ void s5p_mfc_raw_unprotect(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *mfc_buf, } } -void s5p_mfc_stream_protect(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *mfc_buf, +void mfc_stream_protect(struct mfc_ctx *ctx, struct mfc_buf *mfc_buf, int index) { if (!test_bit(index, &ctx->stream_protect_flag)) { - if (mfc_stream_buf_prot(ctx, mfc_buf, true)) { + if (__mfc_stream_buf_prot(ctx, mfc_buf, true)) { mfc_err_ctx("failed to CFW_PROT\n"); } else { set_bit(index, &ctx->stream_protect_flag); @@ -82,11 +82,11 @@ void s5p_mfc_stream_protect(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *mfc_buf } } -void s5p_mfc_stream_unprotect(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *mfc_buf, +void mfc_stream_unprotect(struct mfc_ctx *ctx, struct mfc_buf *mfc_buf, int index) { if (test_bit(index, &ctx->stream_protect_flag)) { - if (mfc_stream_buf_prot(ctx, mfc_buf, false)) { + if (__mfc_stream_buf_prot(ctx, mfc_buf, false)) { mfc_err_ctx("failed to CFW_UNPROT\n"); } else { clear_bit(index, &ctx->stream_protect_flag); @@ -96,7 +96,7 @@ void s5p_mfc_stream_unprotect(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *mfc_b } } -static int mfc_calc_plane(int width, int height, int is_tiled) +static int __mfc_calc_plane(int width, int height, int is_tiled) { int mbX, mbY; @@ -110,10 +110,10 @@ static int mfc_calc_plane(int width, int height, int is_tiled) return (mbX * 16) * (mbY * 16); } -static void mfc_set_linear_stride_size(struct s5p_mfc_ctx *ctx, - struct s5p_mfc_fmt *fmt) +static void __mfc_set_linear_stride_size(struct mfc_ctx *ctx, + struct mfc_fmt *fmt) { - struct s5p_mfc_raw_info *raw; + struct mfc_raw_info *raw; int i; raw = &ctx->raw_buf; @@ -190,11 +190,11 @@ static void mfc_set_linear_stride_size(struct s5p_mfc_ctx *ctx, } } -void s5p_mfc_dec_calc_dpb_size(struct s5p_mfc_ctx *ctx) +void mfc_dec_calc_dpb_size(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev; - struct s5p_mfc_dec *dec; - struct s5p_mfc_raw_info *raw; + struct mfc_dev *dev; + struct mfc_dec *dec; + struct mfc_raw_info *raw; int i; int extra = MFC_LINEAR_BUF_SIZE; @@ -224,19 +224,19 @@ void s5p_mfc_dec_calc_dpb_size(struct s5p_mfc_ctx *ctx) break; case V4L2_PIX_FMT_NV12M: case V4L2_PIX_FMT_NV21M: - raw->plane_size[0] = mfc_calc_plane(ctx->img_width, ctx->img_height, 0) + extra; - raw->plane_size[1] = mfc_calc_plane(ctx->img_width, ctx->img_height, 0) / 2 + extra; + raw->plane_size[0] = __mfc_calc_plane(ctx->img_width, ctx->img_height, 0) + extra; + raw->plane_size[1] = __mfc_calc_plane(ctx->img_width, ctx->img_height, 0) / 2 + extra; break; case V4L2_PIX_FMT_NV12M_P010: case V4L2_PIX_FMT_NV21M_P010: - raw->plane_size[0] = mfc_calc_plane(ctx->img_width, ctx->img_height, 0) * 2 + extra; - raw->plane_size[1] = mfc_calc_plane(ctx->img_width, ctx->img_height, 0) + extra; + raw->plane_size[0] = __mfc_calc_plane(ctx->img_width, ctx->img_height, 0) * 2 + extra; + raw->plane_size[1] = __mfc_calc_plane(ctx->img_width, ctx->img_height, 0) + extra; break; case V4L2_PIX_FMT_YUV420M: case V4L2_PIX_FMT_YVU420M: - raw->plane_size[0] = mfc_calc_plane(ctx->img_width, ctx->img_height, 0) + extra; - raw->plane_size[1] = mfc_calc_plane(ctx->img_width, ctx->img_height, 0) / 2 + extra; - raw->plane_size[2] = mfc_calc_plane(ctx->img_width, ctx->img_height, 0) / 2 + extra; + raw->plane_size[0] = __mfc_calc_plane(ctx->img_width, ctx->img_height, 0) + extra; + raw->plane_size[1] = __mfc_calc_plane(ctx->img_width, ctx->img_height, 0) / 2 + extra; + raw->plane_size[2] = __mfc_calc_plane(ctx->img_width, ctx->img_height, 0) / 2 + extra; break; case V4L2_PIX_FMT_NV16M_S10B: case V4L2_PIX_FMT_NV61M_S10B: @@ -247,13 +247,13 @@ void s5p_mfc_dec_calc_dpb_size(struct s5p_mfc_ctx *ctx) break; case V4L2_PIX_FMT_NV16M: case V4L2_PIX_FMT_NV61M: - raw->plane_size[0] = mfc_calc_plane(ctx->img_width, ctx->img_height, 0) + extra; - raw->plane_size[1] = mfc_calc_plane(ctx->img_width, ctx->img_height, 0) + extra; + raw->plane_size[0] = __mfc_calc_plane(ctx->img_width, ctx->img_height, 0) + extra; + raw->plane_size[1] = __mfc_calc_plane(ctx->img_width, ctx->img_height, 0) + extra; break; case V4L2_PIX_FMT_NV16M_P210: case V4L2_PIX_FMT_NV61M_P210: - raw->plane_size[0] = mfc_calc_plane(ctx->img_width, ctx->img_height, 0) * 2 + extra; - raw->plane_size[1] = mfc_calc_plane(ctx->img_width, ctx->img_height, 0) * 2 + extra; + raw->plane_size[0] = __mfc_calc_plane(ctx->img_width, ctx->img_height, 0) * 2 + extra; + raw->plane_size[1] = __mfc_calc_plane(ctx->img_width, ctx->img_height, 0) * 2 + extra; break; /* non-contiguous single fd format */ case V4L2_PIX_FMT_NV12N_10B: @@ -276,7 +276,7 @@ void s5p_mfc_dec_calc_dpb_size(struct s5p_mfc_ctx *ctx) break; } - mfc_set_linear_stride_size(ctx, ctx->dst_fmt); + __mfc_set_linear_stride_size(ctx, ctx->dst_fmt); for (i = 0; i < raw->num_planes; i++) { if (raw->plane_size[i] < ctx->min_dpb_size[i]) { @@ -312,10 +312,10 @@ void s5p_mfc_dec_calc_dpb_size(struct s5p_mfc_ctx *ctx) } } -void s5p_mfc_enc_calc_src_size(struct s5p_mfc_ctx *ctx) +void mfc_enc_calc_src_size(struct mfc_ctx *ctx) { - struct s5p_mfc_dev *dev; - struct s5p_mfc_raw_info *raw; + struct mfc_dev *dev; + struct mfc_raw_info *raw; unsigned int mb_width, mb_height, default_size; int i, extra; @@ -386,7 +386,7 @@ void s5p_mfc_enc_calc_src_size(struct s5p_mfc_ctx *ctx) break; } - mfc_set_linear_stride_size(ctx, ctx->src_fmt); + __mfc_set_linear_stride_size(ctx, ctx->src_fmt); for (i = 0; i < raw->num_planes; i++) { raw->total_plane_size += raw->plane_size[i]; @@ -405,10 +405,10 @@ void s5p_mfc_enc_calc_src_size(struct s5p_mfc_ctx *ctx) mfc_debug(2, "[FRAME] total plane size: %d\n", raw->total_plane_size); } -void s5p_mfc_cleanup_assigned_dpb(struct s5p_mfc_ctx *ctx) +void mfc_cleanup_assigned_dpb(struct mfc_ctx *ctx) { - struct s5p_mfc_dec *dec; - struct s5p_mfc_buf *dst_mb; + struct mfc_dec *dec; + struct mfc_buf *dst_mb; int i; if (!ctx) { @@ -428,16 +428,16 @@ void s5p_mfc_cleanup_assigned_dpb(struct s5p_mfc_ctx *ctx) for (i = 0; i < MFC_MAX_DPBS; i++) { dst_mb = dec->assigned_dpb[i]; - s5p_mfc_raw_unprotect(ctx, dst_mb, i); + mfc_raw_unprotect(ctx, dst_mb, i); } - s5p_mfc_clear_assigned_dpb(ctx); + mfc_clear_assigned_dpb(ctx); } } -void s5p_mfc_unprotect_released_dpb(struct s5p_mfc_ctx *ctx, unsigned int released_flag) +void mfc_unprotect_released_dpb(struct mfc_ctx *ctx, unsigned int released_flag) { - struct s5p_mfc_dec *dec; - struct s5p_mfc_buf *dst_mb; + struct mfc_dec *dec; + struct mfc_buf *dst_mb; int i; if (!ctx) { @@ -455,16 +455,16 @@ void s5p_mfc_unprotect_released_dpb(struct s5p_mfc_ctx *ctx, unsigned int releas for (i = 0; i < MFC_MAX_DPBS; i++) { if (released_flag & (1 << i)) { dst_mb = dec->assigned_dpb[i]; - s5p_mfc_raw_unprotect(ctx, dst_mb, i); + mfc_raw_unprotect(ctx, dst_mb, i); } } } } -void s5p_mfc_protect_dpb(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *dst_mb) +void mfc_protect_dpb(struct mfc_ctx *ctx, struct mfc_buf *dst_mb) { - struct s5p_mfc_dec *dec; + struct mfc_dec *dec; int dst_index; if (!ctx) { @@ -482,13 +482,13 @@ void s5p_mfc_protect_dpb(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *dst_mb) if (ctx->is_drm) { dec->assigned_dpb[dst_index] = dst_mb; - s5p_mfc_raw_protect(ctx, dst_mb, dst_index); + mfc_raw_protect(ctx, dst_mb, dst_index); } } -void s5p_mfc_watchdog_tick(unsigned long arg) +void mfc_watchdog_tick(unsigned long arg) { - struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg; + struct mfc_dev *dev = (struct mfc_dev *)arg; if (!dev) { mfc_err_dev("no mfc device to run\n"); @@ -518,7 +518,7 @@ void s5p_mfc_watchdog_tick(unsigned long arg) add_timer(&dev->watchdog_timer); } -void s5p_mfc_watchdog_start_tick(struct s5p_mfc_dev *dev) +void mfc_watchdog_start_tick(struct mfc_dev *dev) { if (atomic_read(&dev->watchdog_tick_running)) { mfc_debug(2, "watchdog timer was already started!\n"); @@ -531,7 +531,7 @@ void s5p_mfc_watchdog_start_tick(struct s5p_mfc_dev *dev) atomic_set(&dev->watchdog_tick_cnt, 0); } -void s5p_mfc_watchdog_stop_tick(struct s5p_mfc_dev *dev) +void mfc_watchdog_stop_tick(struct mfc_dev *dev) { if (atomic_read(&dev->watchdog_tick_running)) { mfc_debug(2, "watchdog timer is now stopped!\n"); @@ -544,7 +544,7 @@ void s5p_mfc_watchdog_stop_tick(struct s5p_mfc_dev *dev) atomic_set(&dev->watchdog_tick_cnt, 0); } -void s5p_mfc_watchdog_reset_tick(struct s5p_mfc_dev *dev) +void mfc_watchdog_reset_tick(struct mfc_dev *dev) { mfc_debug(2, "watchdog timer reset!\n"); diff --git a/drivers/media/platform/exynos/mfc/mfc_utils.h b/drivers/media/platform/exynos/mfc/mfc_utils.h index 1a611a511612..f9d3266ad3a7 100644 --- a/drivers/media/platform/exynos/mfc/mfc_utils.h +++ b/drivers/media/platform/exynos/mfc/mfc_utils.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_utils.h + * drivers/media/platform/exynos/mfc/mfc_utils.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -15,32 +15,32 @@ #include "mfc_common.h" -static inline void s5p_mfc_clean_dev_int_flags(struct s5p_mfc_dev *dev) +static inline void mfc_clean_dev_int_flags(struct mfc_dev *dev) { dev->int_condition = 0; dev->int_reason = 0; dev->int_err = 0; } -static inline void s5p_mfc_clean_ctx_int_flags(struct s5p_mfc_ctx *ctx) +static inline void mfc_clean_ctx_int_flags(struct mfc_ctx *ctx) { ctx->int_condition = 0; ctx->int_reason = 0; ctx->int_err = 0; } -static inline void s5p_mfc_change_state(struct s5p_mfc_ctx *ctx, enum s5p_mfc_inst_state state) +static inline void mfc_change_state(struct mfc_ctx *ctx, enum mfc_inst_state state) { - struct s5p_mfc_dev *dev = ctx->dev; + struct mfc_dev *dev = ctx->dev; MFC_TRACE_CTX("** state : %d\n", state); ctx->state = state; } -static inline enum s5p_mfc_node_type s5p_mfc_get_node_type(struct file *file) +static inline enum mfc_node_type mfc_get_node_type(struct file *file) { struct video_device *vdev = video_devdata(file); - enum s5p_mfc_node_type node_type; + enum mfc_node_type node_type; if (!vdev) { mfc_err_dev("failed to get video_device\n"); @@ -76,7 +76,7 @@ static inline enum s5p_mfc_node_type s5p_mfc_get_node_type(struct file *file) return node_type; } -static inline int s5p_mfc_is_decoder_node(enum s5p_mfc_node_type node) +static inline int mfc_is_decoder_node(enum mfc_node_type node) { if (node == MFCNODE_DECODER || node == MFCNODE_DECODER_DRM) return 1; @@ -84,7 +84,7 @@ static inline int s5p_mfc_is_decoder_node(enum s5p_mfc_node_type node) return 0; } -static inline int s5p_mfc_is_drm_node(enum s5p_mfc_node_type node) +static inline int mfc_is_drm_node(enum mfc_node_type node) { if (node == MFCNODE_DECODER_DRM || node == MFCNODE_ENCODER_DRM || node == MFCNODE_ENCODER_OTF_DRM) @@ -93,7 +93,7 @@ static inline int s5p_mfc_is_drm_node(enum s5p_mfc_node_type node) return 0; } -static inline int s5p_mfc_is_encoder_otf_node(enum s5p_mfc_node_type node) +static inline int mfc_is_encoder_otf_node(enum mfc_node_type node) { if (node == MFCNODE_ENCODER_OTF || node == MFCNODE_ENCODER_OTF_DRM) return 1; @@ -101,23 +101,23 @@ static inline int s5p_mfc_is_encoder_otf_node(enum s5p_mfc_node_type node) return 0; } -int s5p_mfc_check_vb_with_fmt(struct s5p_mfc_fmt *fmt, struct vb2_buffer *vb); +int mfc_check_vb_with_fmt(struct mfc_fmt *fmt, struct vb2_buffer *vb); -void s5p_mfc_raw_protect(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *mfc_buf, +void mfc_raw_protect(struct mfc_ctx *ctx, struct mfc_buf *mfc_buf, int index); -void s5p_mfc_raw_unprotect(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *mfc_buf, +void mfc_raw_unprotect(struct mfc_ctx *ctx, struct mfc_buf *mfc_buf, int index); -void s5p_mfc_stream_protect(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *mfc_buf, +void mfc_stream_protect(struct mfc_ctx *ctx, struct mfc_buf *mfc_buf, int index); -void s5p_mfc_stream_unprotect(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *mfc_buf, +void mfc_stream_unprotect(struct mfc_ctx *ctx, struct mfc_buf *mfc_buf, int index); -void s5p_mfc_dec_calc_dpb_size(struct s5p_mfc_ctx *ctx); -void s5p_mfc_enc_calc_src_size(struct s5p_mfc_ctx *ctx); +void mfc_dec_calc_dpb_size(struct mfc_ctx *ctx); +void mfc_enc_calc_src_size(struct mfc_ctx *ctx); -static inline void s5p_mfc_cleanup_assigned_fd(struct s5p_mfc_ctx *ctx) +static inline void mfc_cleanup_assigned_fd(struct mfc_ctx *ctx) { - struct s5p_mfc_dec *dec; + struct mfc_dec *dec; int i; dec = ctx->dec_priv; @@ -126,9 +126,9 @@ static inline void s5p_mfc_cleanup_assigned_fd(struct s5p_mfc_ctx *ctx) dec->assigned_fd[i] = MFC_INFO_INIT_FD; } -static inline void s5p_mfc_clear_assigned_dpb(struct s5p_mfc_ctx *ctx) +static inline void mfc_clear_assigned_dpb(struct mfc_ctx *ctx) { - struct s5p_mfc_dec *dec; + struct mfc_dec *dec; int i; if (!ctx) { @@ -146,35 +146,35 @@ static inline void s5p_mfc_clear_assigned_dpb(struct s5p_mfc_ctx *ctx) dec->assigned_dpb[i] = NULL; } -static inline int s5p_mfc_dec_status_decoding(unsigned int dst_frame_status) +static inline int mfc_dec_status_decoding(unsigned int dst_frame_status) { - if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY || - dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_ONLY) + if (dst_frame_status == MFC_REG_DEC_STATUS_DECODING_DISPLAY || + dst_frame_status == MFC_REG_DEC_STATUS_DECODING_ONLY) return 1; return 0; } -static inline int s5p_mfc_dec_status_display(unsigned int dst_frame_status) +static inline int mfc_dec_status_display(unsigned int dst_frame_status) { - if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY || - dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) + if (dst_frame_status == MFC_REG_DEC_STATUS_DISPLAY_ONLY || + dst_frame_status == MFC_REG_DEC_STATUS_DECODING_DISPLAY) return 1; return 0; } -void s5p_mfc_cleanup_assigned_dpb(struct s5p_mfc_ctx *ctx); -void s5p_mfc_unprotect_released_dpb(struct s5p_mfc_ctx *ctx, unsigned int released_flag); -void s5p_mfc_protect_dpb(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *dst_mb); +void mfc_cleanup_assigned_dpb(struct mfc_ctx *ctx); +void mfc_unprotect_released_dpb(struct mfc_ctx *ctx, unsigned int released_flag); +void mfc_protect_dpb(struct mfc_ctx *ctx, struct mfc_buf *dst_mb); /* Watchdog interval */ #define WATCHDOG_TICK_INTERVAL 1000 /* After how many executions watchdog should assume lock up */ #define WATCHDOG_TICK_CNT_TO_START_WATCHDOG 5 -void s5p_mfc_watchdog_tick(unsigned long arg); -void s5p_mfc_watchdog_start_tick(struct s5p_mfc_dev *dev); -void s5p_mfc_watchdog_stop_tick(struct s5p_mfc_dev *dev); -void s5p_mfc_watchdog_reset_tick(struct s5p_mfc_dev *dev); +void mfc_watchdog_tick(unsigned long arg); +void mfc_watchdog_start_tick(struct mfc_dev *dev); +void mfc_watchdog_stop_tick(struct mfc_dev *dev); +void mfc_watchdog_reset_tick(struct mfc_dev *dev); #endif /* __MFC_UTILS_H */ diff --git a/drivers/media/platform/exynos/mfc/mfc_watchdog.c b/drivers/media/platform/exynos/mfc/mfc_watchdog.c index 51a905b4feea..0a10cfbf4d18 100644 --- a/drivers/media/platform/exynos/mfc/mfc_watchdog.c +++ b/drivers/media/platform/exynos/mfc/mfc_watchdog.c @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_watchdog.c + * drivers/media/platform/exynos/mfc/mfc_watchdog.c * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -26,10 +26,10 @@ #include "mfc_utils.h" #define MFC_SFR_AREA_COUNT 21 -static void mfc_dump_regs(struct s5p_mfc_dev *dev) +static void __mfc_dump_regs(struct mfc_dev *dev) { int i; - struct s5p_mfc_ctx_buf_size *buf_size = NULL; + struct mfc_ctx_buf_size *buf_size = NULL; int addr[MFC_SFR_AREA_COUNT][2] = { { 0x0, 0x80 }, { 0x1000, 0xCD0 }, @@ -57,7 +57,7 @@ static void mfc_dump_regs(struct s5p_mfc_dev *dev) pr_err("-----------dumping MFC registers (SFR base = 0x%p, dev = 0x%p)\n", dev->regs_base, dev); - s5p_mfc_enable_all_clocks(dev); + mfc_enable_all_clocks(dev); for (i = 0; i < MFC_SFR_AREA_COUNT; i++) { printk("[%04X .. %04X]\n", addr[i][0], addr[i][0] + addr[i][1]); @@ -75,11 +75,11 @@ static void mfc_dump_regs(struct s5p_mfc_dev *dev) } } -const u32 s5p_mfc_logging_sfr_set1[MFC_SFR_LOGGING_COUNT_SET1] = { +const u32 mfc_logging_sfr_set1[MFC_SFR_LOGGING_COUNT_SET1] = { 0x1000, 0x1004, 0x100C, 0x1010 }; -const u32 s5p_mfc_logging_sfr_set2[MFC_SFR_LOGGING_COUNT_SET2] = { +const u32 mfc_logging_sfr_set2[MFC_SFR_LOGGING_COUNT_SET2] = { 0x0070, 0x10B4, 0x2020, 0x2028, 0x204C, 0x20B4, 0x3000, 0x3004, 0x3010, 0x301C, 0x3110, 0x5A54, @@ -88,7 +88,7 @@ const u32 s5p_mfc_logging_sfr_set2[MFC_SFR_LOGGING_COUNT_SET2] = { 0x7114, 0xF088, 0xFFD0 }; -int mfc_change_hex_to_ascii(u32 hex, u32 byte, char *ascii, int idx) +int __mfc_change_hex_to_ascii(u32 hex, u32 byte, char *ascii, int idx) { int i; char tmp; @@ -114,7 +114,7 @@ int mfc_change_hex_to_ascii(u32 hex, u32 byte, char *ascii, int idx) return ++idx; } -static void mfc_save_logging_sfr(struct s5p_mfc_dev *dev) +static void __mfc_save_logging_sfr(struct mfc_dev *dev) { char *errorinfo; int i, idx = 0; @@ -122,18 +122,18 @@ static void mfc_save_logging_sfr(struct s5p_mfc_dev *dev) pr_err("-----------logging MFC error info-----------\n"); errorinfo = dev->logging_data->errorinfo; for (i = 0; i < MFC_SFR_LOGGING_COUNT_SET1; i++) - dev->logging_data->SFRs_set1[i] = MFC_READL(s5p_mfc_logging_sfr_set1[i]); + dev->logging_data->SFRs_set1[i] = MFC_READL(mfc_logging_sfr_set1[i]); for (i = 0; i < MFC_SFR_LOGGING_COUNT_SET2; i++) - dev->logging_data->SFRs_set2[i] = MFC_READL(s5p_mfc_logging_sfr_set2[i]); + dev->logging_data->SFRs_set2[i] = MFC_READL(mfc_logging_sfr_set2[i]); - idx = mfc_change_hex_to_ascii(dev->logging_data->cause, 8, errorinfo, idx); - idx = mfc_change_hex_to_ascii(dev->logging_data->fault_status, 2, errorinfo, idx); - idx = mfc_change_hex_to_ascii(dev->logging_data->fault_trans_info, 8, errorinfo, idx); - idx = mfc_change_hex_to_ascii(dev->logging_data->fault_addr, 8, errorinfo, idx); + idx = __mfc_change_hex_to_ascii(dev->logging_data->cause, 8, errorinfo, idx); + idx = __mfc_change_hex_to_ascii(dev->logging_data->fault_status, 2, errorinfo, idx); + idx = __mfc_change_hex_to_ascii(dev->logging_data->fault_trans_info, 8, errorinfo, idx); + idx = __mfc_change_hex_to_ascii(dev->logging_data->fault_addr, 8, errorinfo, idx); for (i = 0; i < MFC_SFR_LOGGING_COUNT_SET1; i++) - idx = mfc_change_hex_to_ascii(dev->logging_data->SFRs_set1[i], 2, errorinfo, idx); + idx = __mfc_change_hex_to_ascii(dev->logging_data->SFRs_set1[i], 2, errorinfo, idx); for (i = 0; i < MFC_SFR_LOGGING_COUNT_SET2; i++) - idx = mfc_change_hex_to_ascii(dev->logging_data->SFRs_set2[i], 8, errorinfo, idx); + idx = __mfc_change_hex_to_ascii(dev->logging_data->SFRs_set2[i], 8, errorinfo, idx); pr_err("%s\n", errorinfo); @@ -142,20 +142,20 @@ static void mfc_save_logging_sfr(struct s5p_mfc_dev *dev) #endif } -static void mfc_display_state(struct s5p_mfc_dev *dev) +static void __mfc_display_state(struct mfc_dev *dev) { nal_queue_handle *nal_q_handle = dev->nal_q_handle; int i; pr_err("-----------dumping MFC device info-----------\n"); pr_err("power:%d, clock:%d, num_inst:%d, num_drm_inst:%d, fw_status:%d\n", - s5p_mfc_pm_get_pwr_ref_cnt(dev), s5p_mfc_pm_get_clk_ref_cnt(dev), + mfc_pm_get_pwr_ref_cnt(dev), mfc_pm_get_clk_ref_cnt(dev), dev->num_inst, dev->num_drm_inst, dev->fw.status); pr_err("hwlock bits:%#lx / dev:%#lx, curr_ctx:%d (is_drm:%d)," " preempt_ctx:%d, work_bits:%#lx\n", dev->hwlock.bits, dev->hwlock.dev, dev->curr_ctx, dev->curr_ctx_is_drm, - dev->preempt_ctx, s5p_mfc_get_bits(&dev->work_bits)); + dev->preempt_ctx, mfc_get_bits(&dev->work_bits)); pr_err("options debug_level:%d, debug_mode:%d, mmcache:%d, perf_boost:%d\n", debug_level, dev->pdata->debug_mode, dev->mmcache.is_on_status, perf_boost_mode); pr_err("NAL-Q state:%d, exception:%d, in_exe_cnt: %d, out_exe_cnt: %d\n", @@ -170,16 +170,16 @@ static void mfc_display_state(struct s5p_mfc_dev *dev) dev->ctx[i]->num, dev->ctx[i]->type == MFCINST_DECODER ? "DEC" : "ENC", dev->ctx[i]->codec_mode, dev->ctx[i]->state, - s5p_mfc_get_queue_count(&dev->ctx[i]->buf_queue_lock, &dev->ctx[i]->src_buf_queue), - s5p_mfc_get_queue_count(&dev->ctx[i]->buf_queue_lock, &dev->ctx[i]->dst_buf_queue), - s5p_mfc_get_queue_count(&dev->ctx[i]->buf_queue_lock, &dev->ctx[i]->ref_buf_queue), - s5p_mfc_get_queue_count(&dev->ctx[i]->buf_queue_lock, &dev->ctx[i]->src_buf_nal_queue), - s5p_mfc_get_queue_count(&dev->ctx[i]->buf_queue_lock, &dev->ctx[i]->dst_buf_nal_queue), + mfc_get_queue_count(&dev->ctx[i]->buf_queue_lock, &dev->ctx[i]->src_buf_queue), + mfc_get_queue_count(&dev->ctx[i]->buf_queue_lock, &dev->ctx[i]->dst_buf_queue), + mfc_get_queue_count(&dev->ctx[i]->buf_queue_lock, &dev->ctx[i]->ref_buf_queue), + mfc_get_queue_count(&dev->ctx[i]->buf_queue_lock, &dev->ctx[i]->src_buf_nal_queue), + mfc_get_queue_count(&dev->ctx[i]->buf_queue_lock, &dev->ctx[i]->dst_buf_nal_queue), dev->ctx[i]->int_condition, dev->ctx[i]->int_reason, dev->ctx[i]->int_err); } -static void mfc_print_trace(struct s5p_mfc_dev *dev) +static void __mfc_print_trace(struct mfc_dev *dev) { int i, cnt, trace_cnt; @@ -193,9 +193,9 @@ static void mfc_print_trace(struct s5p_mfc_dev *dev) } } -void mfc_dump_buffer_info(struct s5p_mfc_dev *dev) +void __mfc_dump_buffer_info(struct mfc_dev *dev) { - struct s5p_mfc_ctx *ctx; + struct mfc_ctx *ctx; ctx = dev->ctx[dev->curr_ctx]; if (ctx) { @@ -210,56 +210,56 @@ void mfc_dump_buffer_info(struct s5p_mfc_dev *dev) ctx->codec_buf.daddr + ctx->codec_buf.size); if (ctx->type == MFCINST_DECODER) { pr_err("Decoder CPB:%#x++%#x, scratch:%#x++%#x, static(vp9):%#x++%#x\n", - MFC_READL(S5P_FIMV_D_CPB_BUFFER_ADDR), - MFC_READL(S5P_FIMV_D_CPB_BUFFER_SIZE), - MFC_READL(S5P_FIMV_D_SCRATCH_BUFFER_ADDR), - MFC_READL(S5P_FIMV_D_SCRATCH_BUFFER_SIZE), - MFC_READL(S5P_FIMV_D_STATIC_BUFFER_ADDR), - MFC_READL(S5P_FIMV_D_STATIC_BUFFER_SIZE)); + MFC_READL(MFC_REG_D_CPB_BUFFER_ADDR), + MFC_READL(MFC_REG_D_CPB_BUFFER_SIZE), + MFC_READL(MFC_REG_D_SCRATCH_BUFFER_ADDR), + MFC_READL(MFC_REG_D_SCRATCH_BUFFER_SIZE), + MFC_READL(MFC_REG_D_STATIC_BUFFER_ADDR), + MFC_READL(MFC_REG_D_STATIC_BUFFER_SIZE)); pr_err("DPB [0]plane:++%#x, [1]plane:++%#x, [2]plane:++%#x, MV buffer:++%#lx\n", ctx->raw_buf.plane_size[0], ctx->raw_buf.plane_size[1], ctx->raw_buf.plane_size[2], ctx->mv_size); print_hex_dump(KERN_ERR, "[0] plane ", DUMP_PREFIX_ADDRESS, 32, 4, - dev->regs_base + S5P_FIMV_D_FIRST_PLANE_DPB0, + dev->regs_base + MFC_REG_D_FIRST_PLANE_DPB0, 0x100, false); print_hex_dump(KERN_ERR, "[1] plane ", DUMP_PREFIX_ADDRESS, 32, 4, - dev->regs_base + S5P_FIMV_D_SECOND_PLANE_DPB0, + dev->regs_base + MFC_REG_D_SECOND_PLANE_DPB0, 0x100, false); if (ctx->dst_fmt->num_planes == 3) print_hex_dump(KERN_ERR, "[2] plane ", DUMP_PREFIX_ADDRESS, 32, 4, - dev->regs_base + S5P_FIMV_D_THIRD_PLANE_DPB0, + dev->regs_base + MFC_REG_D_THIRD_PLANE_DPB0, 0x100, false); print_hex_dump(KERN_ERR, "MV buffer ", DUMP_PREFIX_ADDRESS, 32, 4, - dev->regs_base + S5P_FIMV_D_MV_BUFFER0, + dev->regs_base + MFC_REG_D_MV_BUFFER0, 0x100, false); } else if (ctx->type == MFCINST_ENCODER) { pr_err("Encoder SRC %dplane, [0]:%#x++%#x, [1]:%#x++%#x, [2]:%#x++%#x\n", ctx->src_fmt->num_planes, - MFC_READL(S5P_FIMV_E_SOURCE_FIRST_ADDR), + MFC_READL(MFC_REG_E_SOURCE_FIRST_ADDR), ctx->raw_buf.plane_size[0], - MFC_READL(S5P_FIMV_E_SOURCE_SECOND_ADDR), + MFC_READL(MFC_REG_E_SOURCE_SECOND_ADDR), ctx->raw_buf.plane_size[1], - MFC_READL(S5P_FIMV_E_SOURCE_THIRD_ADDR), + MFC_READL(MFC_REG_E_SOURCE_THIRD_ADDR), ctx->raw_buf.plane_size[2]); pr_err("DST:%#x++%#x, scratch:%#x++%#x\n", - MFC_READL(S5P_FIMV_E_STREAM_BUFFER_ADDR), - MFC_READL(S5P_FIMV_E_STREAM_BUFFER_SIZE), - MFC_READL(S5P_FIMV_E_SCRATCH_BUFFER_ADDR), - MFC_READL(S5P_FIMV_E_SCRATCH_BUFFER_SIZE)); + MFC_READL(MFC_REG_E_STREAM_BUFFER_ADDR), + MFC_READL(MFC_REG_E_STREAM_BUFFER_SIZE), + MFC_READL(MFC_REG_E_SCRATCH_BUFFER_ADDR), + MFC_READL(MFC_REG_E_SCRATCH_BUFFER_SIZE)); pr_err("DPB [0] plane:++%#lx, [1] plane:++%#lx, ME buffer:++%#lx\n", ctx->enc_priv->luma_dpb_size, ctx->enc_priv->chroma_dpb_size, ctx->enc_priv->me_buffer_size); print_hex_dump(KERN_ERR, "[0] plane ", DUMP_PREFIX_ADDRESS, 32, 4, - dev->regs_base + S5P_FIMV_E_LUMA_DPB, + dev->regs_base + MFC_REG_E_LUMA_DPB, 0x44, false); print_hex_dump(KERN_ERR, "[1] plane ", DUMP_PREFIX_ADDRESS, 32, 4, - dev->regs_base + S5P_FIMV_E_CHROMA_DPB, + dev->regs_base + MFC_REG_E_CHROMA_DPB, 0x44, false); print_hex_dump(KERN_ERR, "ME buffer ", DUMP_PREFIX_ADDRESS, 32, 4, - dev->regs_base + S5P_FIMV_E_ME_BUFFER, + dev->regs_base + MFC_REG_E_ME_BUFFER, 0x44, false); } else { pr_err("invalid MFC instnace type(%d)\n", ctx->type); @@ -267,44 +267,44 @@ void mfc_dump_buffer_info(struct s5p_mfc_dev *dev) } } -static void mfc_dump_info_without_regs(struct s5p_mfc_dev *dev) +static void __mfc_dump_info_without_regs(struct mfc_dev *dev) { - mfc_display_state(dev); - mfc_print_trace(dev); + __mfc_display_state(dev); + __mfc_print_trace(dev); } -static void mfc_dump_info(struct s5p_mfc_dev *dev) +static void __mfc_dump_info(struct mfc_dev *dev) { - mfc_dump_info_without_regs(dev); - mfc_save_logging_sfr(dev); - mfc_dump_buffer_info(dev); - mfc_dump_regs(dev); + __mfc_dump_info_without_regs(dev); + __mfc_save_logging_sfr(dev); + __mfc_dump_buffer_info(dev); + __mfc_dump_regs(dev); exynos_sysmmu_show_status(dev->device); } -static void mfc_dump_info_and_stop_hw(struct s5p_mfc_dev *dev) +static void __mfc_dump_info_and_stop_hw(struct mfc_dev *dev) { MFC_TRACE_DEV("** mfc will stop!!!\n"); - mfc_dump_info(dev); + __mfc_dump_info(dev); BUG(); } -static void mfc_dump_info_and_stop_hw_debug(struct s5p_mfc_dev *dev) +static void __mfc_dump_info_and_stop_hw_debug(struct mfc_dev *dev) { if (!dev->pdata->debug_mode) return; MFC_TRACE_DEV("** mfc will stop!!!\n"); - mfc_dump_info(dev); + __mfc_dump_info(dev); BUG(); } -void s5p_mfc_watchdog_worker(struct work_struct *work) +void mfc_watchdog_worker(struct work_struct *work) { - struct s5p_mfc_dev *dev; + struct mfc_dev *dev; int cmd; - dev = container_of(work, struct s5p_mfc_dev, watchdog_work); + dev = container_of(work, struct mfc_dev, watchdog_work); if (atomic_read(&dev->watchdog_run)) { mfc_err_dev("watchdog already running???\n"); @@ -316,7 +316,7 @@ void s5p_mfc_watchdog_worker(struct work_struct *work) return; } - cmd = s5p_mfc_check_risc2host(dev); + cmd = mfc_check_risc2host(dev); if (cmd) { if (atomic_read(&dev->watchdog_tick_cnt) == (3 * WATCHDOG_TICK_CNT_TO_START_WATCHDOG)) { mfc_err_dev("MFC driver waited for upward of %dsec\n", @@ -338,13 +338,13 @@ void s5p_mfc_watchdog_worker(struct work_struct *work) atomic_set(&dev->watchdog_tick_cnt, 0); /* Stop after dumping information */ - mfc_dump_info_and_stop_hw(dev); + __mfc_dump_info_and_stop_hw(dev); } -struct s5p_mfc_dump_ops mfc_dump_ops = { - .dump_regs = mfc_dump_regs, - .dump_info = mfc_dump_info, - .dump_info_without_regs = mfc_dump_info_without_regs, - .dump_and_stop_always = mfc_dump_info_and_stop_hw, - .dump_and_stop_debug_mode = mfc_dump_info_and_stop_hw_debug, +struct mfc_dump_ops mfc_dump_ops = { + .dump_regs = __mfc_dump_regs, + .dump_info = __mfc_dump_info, + .dump_info_without_regs = __mfc_dump_info_without_regs, + .dump_and_stop_always = __mfc_dump_info_and_stop_hw, + .dump_and_stop_debug_mode = __mfc_dump_info_and_stop_hw_debug, }; diff --git a/drivers/media/platform/exynos/mfc/mfc_watchdog.h b/drivers/media/platform/exynos/mfc/mfc_watchdog.h index 4d01e1628401..ed30b6946f9b 100644 --- a/drivers/media/platform/exynos/mfc/mfc_watchdog.h +++ b/drivers/media/platform/exynos/mfc/mfc_watchdog.h @@ -1,5 +1,5 @@ /* - * drivers/media/platform/exynos/mfc/s5p_mfc_watchdog.h + * drivers/media/platform/exynos/mfc/mfc_watchdog.h * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -15,6 +15,6 @@ #include "mfc_common.h" -void s5p_mfc_watchdog_worker(struct work_struct *work); +void mfc_watchdog_worker(struct work_struct *work); #endif /* __MFC_WATCHDOG_H */