From: Xing Zheng Date: Wed, 25 May 2016 08:51:56 +0000 (+0800) Subject: clk: rockchip: add a dummy clock for the watchdog pclk on rk3399 X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=26e0ee1c62a08ee7dd39e9c38f53b5bcfe8b70b7;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git clk: rockchip: add a dummy clock for the watchdog pclk on rk3399 Like rk3288, the pclk supplying the watchdog is controlled via the SGRF register area. Additionally the SGRF isn't even writable in every boot mode. But still the clock control is available and in the future someone might want to use it. Therefore define a simple clock for the time being so that the watchdog driver can read its rate. Signed-off-by: Xing Zheng Reviewed-by: Stephen Barber Signed-off-by: Heiko Stuebner --- diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index 291543f52caa..b6742fad3f8d 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -1498,6 +1498,7 @@ static void __init rk3399_clk_init(struct device_node *np) { struct rockchip_clk_provider *ctx; void __iomem *reg_base; + struct clk *clk; reg_base = of_iomap(np, 0); if (!reg_base) { @@ -1511,6 +1512,14 @@ static void __init rk3399_clk_init(struct device_node *np) return; } + /* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */ + clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_alive", 0, 1, 1); + if (IS_ERR(clk)) + pr_warn("%s: could not register clock pclk_wdt: %ld\n", + __func__, PTR_ERR(clk)); + else + rockchip_clk_add_lookup(ctx, clk, PCLK_WDT); + rockchip_clk_register_plls(ctx, rk3399_pll_clks, ARRAY_SIZE(rk3399_pll_clks), -1);