From: Zhenyu Wang Date: Tue, 30 Oct 2012 11:16:34 +0000 (+0800) Subject: drm/i915: Fix HSW power well control state read X-Git-Tag: MMI-PSA29.97-13-9~15304^2~193^2~88 X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=263b30d4b1a52432075069070328cfa641179f92;p=GitHub%2FMotorolaMobilityLLC%2Fkernel-slsi.git drm/i915: Fix HSW power well control state read Fix power well control state by reading real register offset. Signed-off-by: Zhenyu Wang Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f85043ca41b5..59c31f6238c1 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3842,7 +3842,7 @@ void intel_init_power_wells(struct drm_device *dev) if ((well & HSW_PWR_WELL_STATE) == 0) { I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE); - if (wait_for(I915_READ(power_wells[i] & HSW_PWR_WELL_STATE), 20)) + if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20)) DRM_ERROR("Error enabling power well %lx\n", power_wells[i]); } }