From: Eunseok Choi <es10.choi@samsung.com>
Date: Sat, 3 Jun 2017 06:36:54 +0000 (+0900)
Subject: [9810] thermal: samsung: add TMU TRIM0 configuration
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=243848be9db82d0848dba6a6d3ea03fc9758f27a;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

[9810] thermal: samsung: add TMU TRIM0 configuration

Change-Id: I7280a4c8a6c175d1dcc8e36e9ecb753c606694e8
Signed-off-by: Eunseok Choi <es10.choi@samsung.com>
---

diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index 81ed6cebe47e..4215d6a8b032 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -136,6 +136,16 @@
 #define EXYNOS_TMU_T_BUF_SLOPE_SEL_MASK		(0xF)
 #define EXYNOS_TMU_T_BUF_CONT_MASK		(0xF)
 
+#define EXYNOS_TMU_REG_TRIM0			(0x3C)
+#define EXYNOS_TMU_T_TRIM0_SHIFT		(18)
+#define EXYNOS_TMU_T_TRIM0_MASK			(0xF)
+#define EXYNOS_TMU_BGRI_TRIM_SHIFT		(20)
+#define EXYNOS_TMU_BGRI_TRIM_MASK		(0xF)
+#define EXYNOS_TMU_VREF_TRIM_SHIFT		(12)
+#define EXYNOS_TMU_VREF_TRIM_MASK		(0xF)
+#define EXYNOS_TMU_VBEI_TRIM_SHIFT		(8)
+#define EXYNOS_TMU_VBEI_TRIM_MASK		(0xF)
+
 #define EXYNOS_TMU_REG_INTPEND0			(0x118)
 #define EXYNOS_TMU_REG_INTPEND5			(0x318)
 #define EXYNOS_TMU_REG_INTPEND8			(0x658)
@@ -202,6 +212,10 @@ static LIST_HEAD(dtm_dev_list);
 
 static u32 global_avg_con;
 
+static u32 t_bgri_trim;
+static u32 t_vref_trim;
+static u32 t_vbei_trim;
+
 static void exynos_report_trigger(struct exynos_tmu_data *p)
 {
 	struct thermal_zone_device *tz = p->tzd;
@@ -1198,6 +1212,17 @@ static void exynos9810_tmu_control(struct platform_device *pdev, bool on)
 	counter_value |= EXYNOS_TMU_TEM1051X_SENSE_VALUE << EXYNOS_TMU_CLK_SENSE_ON_SHIFT;
 	writel(counter_value, data->base + EXYNOS_TMU_REG_COUNTER_VALUE1);
 
+	/* set TRIM0 BGR_I/VREF/VBE_I */
+	/* write TRIM0 values read from TMU_TOP to each TMU_TOP and TMU_SUB */
+	ctrl = readl(data->base + EXYNOS_TMU_REG_TRIM0);
+	ctrl &= ~(EXYNOS_TMU_BGRI_TRIM_MASK << EXYNOS_TMU_BGRI_TRIM_SHIFT);
+	ctrl &= ~(EXYNOS_TMU_VREF_TRIM_MASK << EXYNOS_TMU_VREF_TRIM_SHIFT);
+	ctrl &= ~(EXYNOS_TMU_VBEI_TRIM_MASK << EXYNOS_TMU_VBEI_TRIM_SHIFT);
+	ctrl |= (t_bgri_trim << EXYNOS_TMU_BGRI_TRIM_SHIFT);
+	ctrl |= (t_vref_trim << EXYNOS_TMU_VREF_TRIM_SHIFT);
+	ctrl |= (t_vbei_trim << EXYNOS_TMU_VBEI_TRIM_SHIFT);
+	writel(ctrl, data->base + EXYNOS_TMU_REG_TRIM0);
+
 	tmu_irqs_enable(pdev);
 	tmu_core_enable(pdev);
 }
@@ -2145,6 +2170,7 @@ struct exynos_tmu_data *gpu_thermal_data;
 static int exynos_tmu_probe(struct platform_device *pdev)
 {
 	struct exynos_tmu_data *data;
+	unsigned int ctrl;
 	int ret;
 
 	data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
@@ -2187,6 +2213,17 @@ static int exynos_tmu_probe(struct platform_device *pdev)
 	data->num_probe = (readl(data->base + EXYNOS_TMU_REG_CONTROL1) >> EXYNOS_TMU_NUM_PROBE_SHIFT)
 				& EXYNOS_TMU_NUM_PROBE_MASK;
 
+#if defined(CONFIG_SOC_EXYNOS9810)
+	if (data->id == 0) {
+		ctrl = readl(data->base + EXYNOS_TMU_REG_TRIMINFO(3));
+		t_bgri_trim = (ctrl >> EXYNOS_TMU_T_TRIM0_SHIFT) & EXYNOS_TMU_T_TRIM0_MASK;
+		ctrl = readl(data->base + EXYNOS_TMU_REG_TRIMINFO(4));
+		t_vref_trim = (ctrl >> EXYNOS_TMU_T_TRIM0_SHIFT) & EXYNOS_TMU_T_TRIM0_MASK;
+		ctrl = readl(data->base + EXYNOS_TMU_REG_TRIMINFO(5));
+		t_vbei_trim = (ctrl >> EXYNOS_TMU_T_TRIM0_SHIFT) & EXYNOS_TMU_T_TRIM0_MASK;
+	}
+#endif
+
 	ret = exynos_tmu_initialize(pdev);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed to initialize TMU\n");