From: Alex Deucher <alexander.deucher@amd.com>
Date: Thu, 15 Sep 2016 16:04:45 +0000 (-0400)
Subject: drm/amdgpu/si: fix ring size for compute
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=2255e8c1092fedbd3db9940e37ef44524f86a3d9;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git

drm/amdgpu/si: fix ring size for compute

We switched the other asics, but missed this.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index a1484b8f7eb2..9697994d3fff 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -2779,7 +2779,7 @@ static int gfx_v6_0_sw_init(void *handle)
 		ring->queue = i;
 		sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
 		irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
-		r = amdgpu_ring_init(adev, ring, 1024 * 1024,
+		r = amdgpu_ring_init(adev, ring, 1024,
 				     0x80000000, 0xf,
 				     &adev->gfx.eop_irq, irq_type,
 				     AMDGPU_RING_TYPE_COMPUTE);