From: Brian Norris Date: Thu, 19 Aug 2010 15:11:02 +0000 (-0700) Subject: mtd: nand: spansion S30MLxxxP support X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=2173bae81e17b710328bc877e7b9ade7f4b90064;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git mtd: nand: spansion S30MLxxxP support Some Spansion chips have a method for determining eraseblock size that is incompatible with similar ID chips of other sizes. This implements some heuristic detection of these differences. This patch checks for a 5-byte ID with trailing zeros as well as a 512-byte page size to ensure that chips are not misdetected as the S30MLxxxP ORNAND series. [Tweaked by Artem a bit] Signed-off-by: Brian Norris Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 0fd22cce0ecc..b0f091aca097 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2900,6 +2900,19 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, mtd->writesize = type->pagesize; mtd->oobsize = mtd->writesize / 32; busw = type->options & NAND_BUSWIDTH_16; + + /* + * Check for Spansion/AMD ID + repeating 5th, 6th byte since + * some Spansion chips have erasesize that conflicts with size + * listed in nand_ids table + * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) + */ + if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && + id_data[5] == 0x00 && id_data[6] == 0x00 && + id_data[7] == 0x00 && mtd->writesize == 512) { + mtd->erasesize = 128 * 1024; + mtd->erasesize <<= ((id_data[3] & 0x03) << 1); + } } /* Try to identify manufacturer */