From: Rex Zhu <Rex.Zhu@amd.com>
Date: Tue, 15 Mar 2016 11:30:00 +0000 (+0800)
Subject: drm/amd/powerplay: enable set lowest mclk clock on baffin.
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=2043f43e4b176de5c67ee25f863db7fd3835b968;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

drm/amd/powerplay: enable set lowest mclk clock on baffin.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index 446ed72feb02..b77d7aa0f412 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -3136,7 +3136,7 @@ static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
 							    (1 << level));
 
 	}
-/* uvd is enabled, can't set mclk low right now
+
 	if (!data->mclk_dpm_key_disabled) {
 		if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
 			level = phm_get_lowest_enabled_level(hwmgr,
@@ -3146,7 +3146,7 @@ static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
 							    (1 << level));
 		}
 	}
-*/
+
 	if (!data->pcie_dpm_key_disabled) {
 		if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
 			level = phm_get_lowest_enabled_level(hwmgr,