From: Bjorn Helgaas <bhelgaas@google.com>
Date: Fri, 14 Aug 2015 13:16:29 +0000 (-0500)
Subject: Merge branches 'pci/hotplug', 'pci/iommu', 'pci/irq' and 'pci/virtualization' into... 
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=1f408d57437e53ae9aa6edb335ff9fe7ba7aba2c;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git

Merge branches 'pci/hotplug', 'pci/iommu', 'pci/irq' and 'pci/virtualization' into next

* pci/hotplug:
  PCI: pciehp: Remove ignored MRL sensor interrupt events
  PCI: pciehp: Remove unused interrupt events
  PCI: pciehp: Handle invalid data when reading from non-existent devices
  PCI: Hold pci_slot_mutex while searching bus->slots list
  PCI: Protect pci_bus->slots with pci_slot_mutex, not pci_bus_sem
  PCI: pciehp: Simplify pcie_poll_cmd()
  PCI: Use "slot" and "pci_slot" for struct hotplug_slot and struct pci_slot

* pci/iommu:
  PCI: Remove pci_ats_enabled()
  PCI: Stop caching ATS Invalidate Queue Depth
  PCI: Move ATS declarations to linux/pci.h so they're all together
  PCI: Clean up ATS error handling
  PCI: Use pci_physfn() rather than looking up physfn by hand
  PCI: Inline the ATS setup code into pci_ats_init()
  PCI: Rationalize pci_ats_queue_depth() error checking
  PCI: Reduce size of ATS structure elements
  PCI: Embed ATS info directly into struct pci_dev
  PCI: Allocate ATS struct during enumeration
  iommu/vt-d: Cache PCI ATS state and Invalidate Queue Depth

* pci/irq:
  PCI: Kill off set_irq_flags() usage

* pci/virtualization:
  PCI: Add ACS quirks for Intel I219-LM/V
---

1f408d57437e53ae9aa6edb335ff9fe7ba7aba2c
diff --cc drivers/pci/host/pcie-xilinx.c
index dcb9b57ed7ea,f1a06a091ccb,f1a06a091ccb,7201511972ad,f1a06a091ccb..0e1f480b9db4
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@@@@@ -449,17 -449,14 -449,14 -447,14 -449,14 +447,17 @@@@@@ static irqreturn_t xilinx_pcie_intr_han
     			return IRQ_HANDLED;
     		}
     
 ----		/* Clear interrupt FIFO register 1 */
 ----		pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
 ----			   XILINX_PCIE_REG_RPIFR1);
   - 
   - 		/* Handle INTx Interrupt */
   - 		val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
   - 			XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1;
   - 		generic_handle_irq(irq_find_mapping(port->irq_domain, val));
 ++++		if (!(val & XILINX_PCIE_RPIFR1_MSI_INTR)) {
 ++++			/* Clear interrupt FIFO register 1 */
 ++++			pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
 ++++				   XILINX_PCIE_REG_RPIFR1);
   + 
 -- -		/* Handle INTx Interrupt */
 -- -		val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
 -- -			XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1;
 -- -		generic_handle_irq(irq_find_mapping(port->irq_domain, val));
 ++++			/* Handle INTx Interrupt */
 ++++			val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
 ++++				XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1;
 ++++			generic_handle_irq(irq_find_mapping(port->irq_domain,
 ++++							    val));
 ++++		}
     	}
     
     	if (status & XILINX_PCIE_INTR_MSI) {