From: Geert Uytterhoeven Date: Mon, 16 Jul 2007 16:35:38 +0000 (+1000) Subject: [POWERPC] cell: CONFIG_SPE_BASE is a typo X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=1e57ba8dddcbb384b293f948cba190c5199cf945;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git [POWERPC] cell: CONFIG_SPE_BASE is a typo The config symbol for SPE support is called CONFIG_SPU_BASE, not CONFIG_SPE_BASE. Signed-off-by: Geert Uytterhoeven Acked-by: Benjamin Herrenschmidt Signed-off-by: Paul Mackerras --- diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c index 2ce9491b48d4..bc7b0cedae5e 100644 --- a/arch/powerpc/mm/hash_utils_64.c +++ b/arch/powerpc/mm/hash_utils_64.c @@ -609,7 +609,7 @@ static void demote_segment_4k(struct mm_struct *mm, unsigned long addr) mm->context.sllp = SLB_VSID_USER | mmu_psize_defs[MMU_PAGE_4K].sllp; #endif /* CONFIG_PPC_MM_SLICES */ -#ifdef CONFIG_SPE_BASE +#ifdef CONFIG_SPU_BASE spu_flush_all_slbs(mm); #endif } @@ -744,7 +744,7 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap) "to 4kB pages because of " "non-cacheable mapping\n"); psize = mmu_vmalloc_psize = MMU_PAGE_4K; -#ifdef CONFIG_SPE_BASE +#ifdef CONFIG_SPU_BASE spu_flush_all_slbs(mm); #endif }