From: Michael Neuling Date: Tue, 30 Apr 2013 20:17:03 +0000 (+0000) Subject: powerpc: Turn on the EBB H/FSCR bits X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=1ddf499e1a49e67c02b89e6565d091a0bda29a91;p=GitHub%2Fexynos8895%2Fandroid_kernel_samsung_universal8895.git powerpc: Turn on the EBB H/FSCR bits This turns Event Based Branching (EBB) on in the Hypervisor Facility Status and Control Register (HFSCR) and Facility Status and Control Register (FSCR). Signed-off-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt --- diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 178a85844462..93be5fb20394 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -267,9 +267,11 @@ #define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */ #define SPRN_FSCR 0x099 /* Facility Status & Control Register */ #define FSCR_TAR (1 << (63-55)) /* Enable Target Address Register */ +#define FSCR_EBB (1 << (63-56)) /* Enable Event Based Branching */ #define FSCR_DSCR (1 << (63-61)) /* Enable Data Stream Control Register */ #define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */ #define HFSCR_TAR (1 << (63-55)) /* Enable Target Address Register */ +#define HFSCR_EBB (1 << (63-56)) /* Enable Event Based Branching */ #define HFSCR_TM (1 << (63-58)) /* Enable Transactional Memory */ #define HFSCR_PM (1 << (63-60)) /* Enable prob/priv access to PMU SPRs */ #define HFSCR_BHRB (1 << (63-59)) /* Enable Branch History Rolling Buffer*/ diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S index 7b4db965b592..a283b6442b26 100644 --- a/arch/powerpc/kernel/cpu_setup_power.S +++ b/arch/powerpc/kernel/cpu_setup_power.S @@ -123,14 +123,14 @@ __init_LPCR: __init_FSCR: mfspr r3,SPRN_FSCR - ori r3,r3,FSCR_TAR|FSCR_DSCR + ori r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB mtspr SPRN_FSCR,r3 blr __init_HFSCR: mfspr r3,SPRN_HFSCR ori r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\ - HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP + HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB mtspr SPRN_HFSCR,r3 blr