From: Ville Syrjälä Date: Wed, 4 Sep 2013 15:30:05 +0000 (+0300) Subject: drm/i915: pipe_src_w must be even in LVDS dual channel, DVO ganged, and double wide... X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=1d1d0e277ee706413e2a3b3c671e3cf29c8d0dd2;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git drm/i915: pipe_src_w must be even in LVDS dual channel, DVO ganged, and double wide mode Pipe horizontal source size must be even when either LVDS dual channel mode, DVO ganged mode, or pipe double wide mode is used. We must round it down since we can never increase the user specified viewport size. The actual error from an odd pipe source width looks like a diagonal shift, like you might get from a bad stride. v2: s/ganaged/ganged/ Signed-off-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 91631bf354e6..9bbb6ea34d06 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4166,6 +4166,16 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, return -EINVAL; } + /* + * Pipe horizontal size must be even in: + * - DVO ganged mode + * - LVDS dual channel mode + * - Double wide pipe + */ + if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && + intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) + pipe_config->pipe_src_w &= ~1; + /* Cantiga+ cannot handle modes with a hsync front porch of 0. * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. */