From: Martyn Welch Date: Fri, 30 Jun 2017 13:43:37 +0000 (+0200) Subject: ARM: dts: imx: Correct B850v3 clock assignment X-Git-Tag: MMI-PSA29.97-13-9~4755^2~19^2~37 X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=1d0c7bb20c083a6e810d2142545b5606f8131080;p=GitHub%2FMotorolaMobilityLLC%2Fkernel-slsi.git ARM: dts: imx: Correct B850v3 clock assignment The IPU that drives HDMI must have its pre_sel set to pll2_pfd_396m to avoid stepping on the LVDS output's toes, as the PLL can't be clocked to the pixel clock and to the LVDS serial clock (3.5*pixel clock) at the same time. As we are using ipu1_di0 and ipu2_di0, ensure both are switched to to pll2_pfd2_396m to avoid issues. The LDB driver will switch the required IPU to ldb_di1 when it uses it to drive LVDS. Signed-off-by: Martyn Welch Signed-off-by: Romain Perier Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/imx6q-b850v3.dts index 2c1e98e0cf7b..46bdc6722715 100644 --- a/arch/arm/boot/dts/imx6q-b850v3.dts +++ b/arch/arm/boot/dts/imx6q-b850v3.dts @@ -57,7 +57,7 @@ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, - <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>; + <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,