From: Kyungmin Park Date: Thu, 21 Oct 2010 06:22:36 +0000 (+0900) Subject: ARM: S5PV310: Add L2 cache init function in cpu.c X-Git-Tag: MMI-PSA29.97-13-9~21870^2^2~2^2~8 X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=1cf0eb799759b24199374955976fee8469835203;p=GitHub%2FMotorolaMobilityLLC%2Fkernel-slsi.git ARM: S5PV310: Add L2 cache init function in cpu.c This patch adds L2 cache initialization code in cpu.c of ARCH_S5PV310. It includes TAG and Data latency, Prefetch, and Power configurations. Signed-off-by: Kyungmin Park Signed-off-by: Changhwan Youn Signed-off-by: Kukjin Kim --- diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c index 5b9790054421..4e3f5be264ef 100644 --- a/arch/arm/mach-s5pv310/cpu.c +++ b/arch/arm/mach-s5pv310/cpu.c @@ -15,6 +15,7 @@ #include #include +#include #include #include @@ -148,6 +149,28 @@ static int __init s5pv310_core_init(void) core_initcall(s5pv310_core_init); +#ifdef CONFIG_CACHE_L2X0 +static int __init s5pv310_l2x0_cache_init(void) +{ + /* TAG, Data Latency Control: 2cycle */ + __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); + __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); + + /* L2X0 Prefetch Control */ + __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL); + + /* L2X0 Power Control */ + __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, + S5P_VA_L2CC + L2X0_POWER_CTRL); + + l2x0_init(S5P_VA_L2CC, 0x7C070001, 0xC200ffff); + + return 0; +} + +early_initcall(s5pv310_l2x0_cache_init); +#endif + int __init s5pv310_init(void) { printk(KERN_INFO "S5PV310: Initializing architecture\n");