From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Tue, 17 May 2016 01:44:39 +0000 (-0700)
Subject: Merge tag 'edac_for_4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp
X-Git-Tag: MMI-PSA29.97-13-9~7957
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=1cc3880a3c99f1be73f9024bd9db6248ffdcec70;p=GitHub%2FMotorolaMobilityLLC%2Fkernel-slsi.git

Merge tag 'edac_for_4.7' of git://git./linux/kernel/git/bp/bp

Pull EDAC updates from Borislav Petkov:
 "It was pretty busy in EDAC land this time:

   - Altera Arria10 L2 cache and On-Chip RAM ECC handling (Thor Thayer)

   - Remove ad-hoc buffering of MCE records in sb_edac and i7core_edac
     (Tony Luck)

   - Do not register sb_edac with pci_register_driver() (Tony Luck)

   - Add support for Skylake to ie31200_edac (Jason Baron)

   - Do not register amd64_edac with pci_register_driver() (Borislav
     Petkov)

  ... plus the usual round of cleanups and fixes all over the place"

* tag 'edac_for_4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp: (25 commits)
  EDAC, amd64_edac: Drop pci_register_driver() use
  EDAC, ie31200_edac: Add Skylake support
  EDAC, sb_edac: Use cpu family/model in driver detection
  EDAC, i7core: Remove double buffering of error records
  EDAC, amd64_edac: Issue driver banner only on success
  ARM: socfpga: Initialize Arria10 OCRAM ECC on startup
  EDAC: Increment correct counter in edac_inc_ue_error()
  EDAC, sb_edac: Remove double buffering of error records
  EDAC: Fix used after kfree() error in edac_unregister_sysfs()
  EDAC, altera: Avoid unused function warnings
  EDAC, altera: Remove useless casts
  ARM: socfpga: Enable Arria10 OCRAM ECC on startup
  EDAC, altera: Add Arria10 OCRAM ECC support
  Documentation: dt: socfpga: Add Altera Arria10 OCRAM binding
  EDAC, altera: Make OCRAM ECC dependency check generic
  EDAC, altera: Add register offset for ECC Enable
  EDAC, altera: Extract error inject operations to a struct fops
  ARM: socfpga: Enable Arria10 L2 cache ECC on startup
  EDAC, altera: Add Arria10 L2 Cache ECC handling
  Documentation, dt, socfpga: Add Altera Arria10 L2 cache binding
  ...
---

1cc3880a3c99f1be73f9024bd9db6248ffdcec70
diff --cc drivers/edac/sb_edac.c
index 8bf745d2da7e,be398e0cf08a..b4d0bf6534cf
--- a/drivers/edac/sb_edac.c
+++ b/drivers/edac/sb_edac.c
@@@ -362,18 -362,7 +362,8 @@@ struct sbridge_pvt 
  
  	/* Memory type detection */
  	bool			is_mirrored, is_lockstep, is_close_pg;
 +	bool			is_chan_hash;
  
- 	/* Fifo double buffers */
- 	struct mce		mce_entry[MCE_LOG_LEN];
- 	struct mce		mce_outentry[MCE_LOG_LEN];
- 
- 	/* Fifo in/out counters */
- 	unsigned		mce_in, mce_out;
- 
- 	/* Count indicator to show errors not got */
- 	unsigned		mce_overrun;
- 
  	/* Memory description */
  	u64			tolm, tohm;
  	struct knl_pvt knl;