From: Takashi Iwai <tiwai@suse.de>
Date: Fri, 4 Jul 2014 05:48:57 +0000 (+0200)
Subject: Merge branch 'for-linus' into for-next
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=1a0e3f9639ebe7f0f17b40eb96d03c05ec067979;p=GitHub%2FLineageOS%2FG12%2Fandroid_kernel_amlogic_linux-4.9.git

Merge branch 'for-linus' into for-next

Conflicts:
	sound/pci/hda/hda_intel.c
---

1a0e3f9639ebe7f0f17b40eb96d03c05ec067979
diff --cc sound/pci/hda/hda_i915.c
index e9e8a4a4a9a1,8b4940ba33d6..d4d0375ac181
--- a/sound/pci/hda/hda_i915.c
+++ b/sound/pci/hda/hda_i915.c
@@@ -20,10 -20,20 +20,20 @@@
  #include <linux/module.h>
  #include <sound/core.h>
  #include <drm/i915_powerwell.h>
+ #include "hda_priv.h"
  #include "hda_i915.h"
  
+ /* Intel HSW/BDW display HDA controller Extended Mode registers.
+  * EM4 (M value) and EM5 (N Value) are used to convert CDClk (Core Display
+  * Clock) to 24MHz BCLK: BCLK = CDCLK * M / N
+  * The values will be lost when the display power well is disabled.
+  */
 -#define ICH6_REG_EM4			0x100c
 -#define ICH6_REG_EM5			0x1010
++#define AZX_REG_EM4			0x100c
++#define AZX_REG_EM5			0x1010
+ 
  static int (*get_power)(void);
  static int (*put_power)(void);
+ static int (*get_cdclk)(void);
  
  int hda_display_power(bool enable)
  {
diff --cc sound/pci/hda/hda_intel.c
index dc0c8dac1900,b6b4e71a0b0b..75b52c4cd70d
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@@ -61,56 -62,10 +61,56 @@@
  #include <linux/vga_switcheroo.h>
  #include <linux/firmware.h>
  #include "hda_codec.h"
- #include "hda_i915.h"
  #include "hda_controller.h"
  #include "hda_priv.h"
+ #include "hda_i915.h"
  
 +/* position fix mode */
 +enum {
 +	POS_FIX_AUTO,
 +	POS_FIX_LPIB,
 +	POS_FIX_POSBUF,
 +	POS_FIX_VIACOMBO,
 +	POS_FIX_COMBO,
 +};
 +
 +/* Defines for ATI HD Audio support in SB450 south bridge */
 +#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 +#define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 +
 +/* Defines for Nvidia HDA support */
 +#define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 +#define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 +#define NVIDIA_HDA_ISTRM_COH          0x4d
 +#define NVIDIA_HDA_OSTRM_COH          0x4c
 +#define NVIDIA_HDA_ENABLE_COHBIT      0x01
 +
 +/* Defines for Intel SCH HDA snoop control */
 +#define INTEL_SCH_HDA_DEVC      0x78
 +#define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 +
 +/* Define IN stream 0 FIFO size offset in VIA controller */
 +#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET	0x90
 +/* Define VIA HD Audio Device ID*/
 +#define VIA_HDAC_DEVICE_ID		0x3288
 +
 +/* max number of SDs */
 +/* ICH, ATI and VIA have 4 playback and 4 capture */
 +#define ICH6_NUM_CAPTURE	4
 +#define ICH6_NUM_PLAYBACK	4
 +
 +/* ULI has 6 playback and 5 capture */
 +#define ULI_NUM_CAPTURE		5
 +#define ULI_NUM_PLAYBACK	6
 +
 +/* ATI HDMI may have up to 8 playbacks and 0 capture */
 +#define ATIHDMI_NUM_CAPTURE	0
 +#define ATIHDMI_NUM_PLAYBACK	8
 +
 +/* TERA has 4 playback and 3 capture */
 +#define TERA_NUM_CAPTURE	3
 +#define TERA_NUM_PLAYBACK	4
 +
  
  static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
@@@ -333,43 -288,10 +333,30 @@@ static char *driver_short_names[] = 
  	[AZX_DRIVER_GENERIC] = "HD-Audio Generic",
  };
  
- 
- /* Intel HSW/BDW display HDA controller Extended Mode registers.
-  * EM4 (M value) and EM5 (N Value) are used to convert CDClk (Core Display
-  * Clock) to 24MHz BCLK: BCLK = CDCLK * M / N
-  * The values will be lost when the display power well is disabled.
-  */
- #define AZX_REG_EM4			0x100c
- #define AZX_REG_EM5			0x1010
- 
  struct hda_intel {
  	struct azx chip;
 -};
  
- 	/* HSW/BDW display HDA controller to restore BCLK from CDCLK */
- 	unsigned int bclk_m;
- 	unsigned int bclk_n;
- 
 +	/* for pending irqs */
 +	struct work_struct irq_pending_work;
 +
 +	/* sync probing */
 +	struct completion probe_wait;
 +	struct work_struct probe_work;
 +
 +	/* card list (for power_save trigger) */
 +	struct list_head list;
 +
 +	/* extra flags */
 +	unsigned int irq_pending_warned:1;
 +
 +	/* VGA-switcheroo setup */
 +	unsigned int use_vga_switcheroo:1;
 +	unsigned int vga_switcheroo_registered:1;
 +	unsigned int init_failed:1; /* delayed init failed */
 +
 +	/* secondary power domain for hdmi audio under vga device */
 +	struct dev_pm_domain hdmi_pm_domain;
 +};
  
  #ifdef CONFIG_X86
  static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)