From: Felipe Balbi <balbi@ti.com>
Date: Tue, 25 Feb 2014 20:08:51 +0000 (-0600)
Subject: usb: dwc3: core: define bit 10 of GCTL register
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=183ca11179f6d3b99e0431bae6acb84350b82dea;p=GitHub%2Fexynos8895%2Fandroid_kernel_samsung_universal8895.git

usb: dwc3: core: define bit 10 of GCTL register

This bit is necessary for implemeting workaround
for known issue with some revisions of this core.

Signed-off-by: Felipe Balbi <balbi@ti.com>
---

diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 69c4583933d1..f2693b63b710 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -157,6 +157,7 @@
 #define DWC3_GCTL_PRTCAP_OTG	3
 
 #define DWC3_GCTL_CORESOFTRESET		(1 << 11)
+#define DWC3_GCTL_SOFITPSYNC		(1 << 10)
 #define DWC3_GCTL_SCALEDOWN(n)		((n) << 4)
 #define DWC3_GCTL_SCALEDOWN_MASK	DWC3_GCTL_SCALEDOWN(3)
 #define DWC3_GCTL_DISSCRAMBLE		(1 << 3)