From: Huacai Chen <chenhc@lemote.com>
Date: Thu, 16 Mar 2017 13:00:28 +0000 (+0800)
Subject: MIPS: Loongson-3: Select MIPS_L1_CACHE_SHIFT_6
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=17c99d9421695a0e0de18bf1e7091d859e20ec1d;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git

MIPS: Loongson-3: Select MIPS_L1_CACHE_SHIFT_6

Some newer Loongson-3 have 64 bytes cache lines, so select
MIPS_L1_CACHE_SHIFT_6.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J . Hill <Steven.Hill@caviumnetworks.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/15755/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index f4dd2c322d4b..2afb41c52ba0 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1374,6 +1374,7 @@ config CPU_LOONGSON3
 	select WEAK_ORDERING
 	select WEAK_REORDERING_BEYOND_LLSC
 	select MIPS_PGD_C0_CONTEXT
+	select MIPS_L1_CACHE_SHIFT_6
 	select GPIOLIB
 	help
 		The Loongson 3 processor implements the MIPS64R2 instruction