From: Changbin Du <changbin.du@intel.com>
Date: Tue, 6 Jun 2017 07:56:14 +0000 (+0800)
Subject: drm/i915/gvt: Tuning the size of MMIO hash lookup table to 2048
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=178cd160c6652f57571ba3dc0a9091a1f41d9bc8;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

drm/i915/gvt: Tuning the size of MMIO hash lookup table to 2048

On Skylake platform, The traced virtual mmio registers are up to 2039.
So tuning the hash table size to improve lookup performance.

Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
---

diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index ffb9ebbbcf5a..3a74e79eac2f 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -195,7 +195,7 @@ struct intel_gvt_fence {
 	unsigned long vgpu_allocated_fence_num;
 };
 
-#define INTEL_GVT_MMIO_HASH_BITS 9
+#define INTEL_GVT_MMIO_HASH_BITS 11
 
 struct intel_gvt_mmio {
 	u8 *mmio_attribute;