From: Michal Simek <monstr@monstr.eu>
Date: Wed, 9 Nov 2011 14:39:58 +0000 (+0100)
Subject: microblaze: Clear all MSR flags on the first kernel instruction
X-Git-Tag: MMI-PSA29.97-13-9~17072^2~11
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=173701d7745d07888a929bf08d77d29996ca13dc;p=GitHub%2FMotorolaMobilityLLC%2Fkernel-slsi.git

microblaze: Clear all MSR flags on the first kernel instruction

The main reason is bug because of dynamic TLB allocation.
U-BOOT didn't disable dcache and then writing to physical address
from ASM wan't visible for reading through MMU.
Disabling caches and clearing all flags from previous code
is good to do so.

Signed-off-by: Michal Simek <monstr@monstr.eu>
---

diff --git a/arch/microblaze/kernel/head.S b/arch/microblaze/kernel/head.S
index 77320b8fc16a..a5ba9925ae89 100644
--- a/arch/microblaze/kernel/head.S
+++ b/arch/microblaze/kernel/head.S
@@ -63,9 +63,7 @@ ENTRY(_start)
 real_start:
 #endif
 
-	mfs	r1, rmsr
-	andi	r1, r1, ~2
-	mts	rmsr, r1
+	mts	rmsr, r0
 /*
  * According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc'
  * if the msrclr instruction is not enabled. We use this to detect
@@ -73,6 +71,7 @@ real_start:
  * r8 == 0 - msr instructions are implemented
  * r8 != 0 - msr instructions are not implemented
  */
+	mfs	r1, rmsr
 	msrclr	r8, 0 /* clear nothing - just read msr for test */
 	cmpu	r8, r8, r1 /* r1 must contain msr reg content */