From: Vijay Kumar B <vijaykumar@bravegnu.org>
Date: Mon, 21 Sep 2009 05:53:54 +0000 (+0530)
Subject: Staging: poch: Parameter to enable synthetic counter
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=16fbf4cba0880c31445d6414abbd7a1c51466b1f;p=GitHub%2FLineageOS%2FG12%2Fandroid_kernel_amlogic_linux-4.9.git

Staging: poch: Parameter to enable synthetic counter

Adds a parameter that causes the hardware to synthesize Rx values
using a counter.

Signed-off-by: Vijay Kumar B. <vijaykumar@bravegnu.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
---

diff --git a/drivers/staging/poch/poch.c b/drivers/staging/poch/poch.c
index 2eb8e3d43c4d..1308c7bada8a 100644
--- a/drivers/staging/poch/poch.c
+++ b/drivers/staging/poch/poch.c
@@ -245,6 +245,11 @@ struct poch_dev {
 	struct device *dev;
 };
 
+static int synth_rx;
+module_param(synth_rx, bool, 0600);
+MODULE_PARM_DESC(synth_rx,
+		"Synthesize received values using a counter. Default: No");
+
 static dev_t poch_first_dev;
 static struct class *poch_cls;
 static DEFINE_IDR(poch_ids);
@@ -827,9 +832,11 @@ static int poch_open(struct inode *inode, struct file *filp)
 			  fpga + FPGA_TX_CTL_REG);
 	} else {
 		/* Flush RX FIFO and output data to cardbus. */
-		iowrite32(FPGA_RX_CTL_CONT_CAP
-			  | FPGA_RX_CTL_FIFO_FLUSH,
-			  fpga + FPGA_RX_CTL_REG);
+		u32 ctl_val = FPGA_RX_CTL_CONT_CAP | FPGA_RX_CTL_FIFO_FLUSH;
+		if (synth_rx)
+			ctl_val |= FPGA_RX_CTL_SYNTH_DATA;
+
+		iowrite32(ctl_val, fpga + FPGA_RX_CTL_REG);
 	}
 
 	atomic_inc(&channel->inited);