From: Nick Hoath <nicholas.hoath@intel.com>
Date: Thu, 7 May 2015 13:15:37 +0000 (+0100)
Subject: drm/i915/bxt: Mark WaCcsTlbPrefetchDisable as for Broxton also.
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=16be17af2ae9fd1544b5d0c58b4facf198031cb8;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

drm/i915/bxt: Mark WaCcsTlbPrefetchDisable as for Broxton also.

Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e74feedd6bee..9b96ed7de9bb 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -957,7 +957,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 	/* WaDisablePartialResolveInVc:skl,bxt */
 	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
 
-	/* WaCcsTlbPrefetchDisable:skl */
+	/* WaCcsTlbPrefetchDisable:skl,bxt */
 	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 			  GEN9_CCS_TLB_PREFETCH_ENABLE);