From: ChiHun Won <chihun.won@samsung.com>
Date: Wed, 4 Jul 2018 05:42:44 +0000 (+0900)
Subject: [9610] arm64: dts: parse DPU count and HW limitation
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=15da067070487e154eb2bc3a79e59b320ce9b7b2;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

[9610] arm64: dts: parse DPU count and HW limitation

Change-Id: Iba607dcb247c0a81265278fb8991a567e097dfe6
Signed-off-by: ChiHun Won <chihun.won@samsung.com>
---

diff --git a/arch/arm64/boot/dts/exynos/exynos9610.dtsi b/arch/arm64/boot/dts/exynos/exynos9610.dtsi
index 130b025dadde..9ed71d1cb47a 100644
--- a/arch/arm64/boot/dts/exynos/exynos9610.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos9610.dtsi
@@ -2387,6 +2387,25 @@
 		interrupts = <0 210 0>, <0 214 0>;
 		attr = <0x50087>; /* DPP/IDMA/HDR10/FLIP/BLOCK/AFBC */
 		port = <0>; /* AXI port number */
+
+		/* HW restriction */
+		src_f_w = <16 65534 1>;
+		src_f_h = <16 8190 1>;
+		src_w = <16 4096 1>;
+		src_h = <16 4096 1>;
+		src_xy_align = <1 1>;
+
+		dst_f_w = <16 8190 1>;
+		dst_f_h = <16 8190 1>;
+		dst_w = <16 4096 1>;
+		dst_h = <16 4096 1>;
+		dst_xy_align = <1 1>;
+
+		blk_w = <4 4096 1>;
+		blk_h = <1 4096 1>;
+		blk_xy_align = <1 1>;
+
+		src_h_rot_max = <2160>;
 	};
 
 	dpp_1: dpp@0x14883000 { /* VG0 */
@@ -2482,6 +2501,12 @@
 		/* pixel per clock */
 		ppc = <2>;
 
+		chip_ver = <9610>;
+
+		dpp_cnt = <4>;
+		dsim_cnt = <2>;
+		decon_cnt = <3>;
+
 		#address-cells = <2>;
 		#size-cells = <1>;
 		ranges;