From: Michael Hennerich <michael.hennerich@analog.com>
Date: Thu, 12 Jul 2007 08:20:21 +0000 (+0800)
Subject: Blackfin arch: Disable CACHELINE_ALIGNED_L1 for BF54x by default
X-Git-Tag: MMI-PSA29.97-13-9~42300^2~12
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=157cc5aad94fb7025c41a60788c1bfb5299010aa;p=GitHub%2FMotorolaMobilityLLC%2Fkernel-slsi.git

Blackfin arch: Disable CACHELINE_ALIGNED_L1 for BF54x by default

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
---

diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 6d23bcc61940..2372b0382a6e 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -540,7 +540,8 @@ config IP_CHECKSUM_L1
 
 config CACHELINE_ALIGNED_L1
 	bool "Locate cacheline_aligned data to L1 Data Memory"
-	default y
+	default y if !BF54x
+	default n if BF54x
 	depends on !BF531
 	help
 	  If enabled cacheline_anligned data is linked