From: Felix Fietkau <nbd@openwrt.org>
Date: Mon, 26 Apr 2010 19:04:30 +0000 (-0400)
Subject: ath9k_hw: fix pll clock setting for 5ghz on AR9003
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=14bc110463bafc1aa4a51d4443e9dc1a88b58c40;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git

ath9k_hw: fix pll clock setting for 5ghz on AR9003

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
---

diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index 137543b2d739..bf8ec687f9e0 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -375,16 +375,7 @@ static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
 	else if (chan && IS_CHAN_QUARTER_RATE(chan))
 		pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
 
-	if (chan && IS_CHAN_5GHZ(chan)) {
-		pll |= SM(0x28, AR_RTC_9300_PLL_DIV);
-
-		/*
-		 * When doing fast clock, set PLL to 0x142c
-		 */
-		if (IS_CHAN_A_5MHZ_SPACED(chan))
-			pll = 0x142c;
-	} else
-		pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
+	pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
 
 	return pll;
 }