From: Kumar Gala Date: Wed, 27 Jul 2005 18:44:10 +0000 (-0700) Subject: [PATCH] ppc32: Fix typo in setup of 2nd PCI bus on 85xx X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=127384524b31d99bc3f9e2d2e7af4a5fad572235;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git [PATCH] ppc32: Fix typo in setup of 2nd PCI bus on 85xx Typo bug that was using PCI1 defines instead of PCI2 when setting up the second PCI bus controller on 85xx based systems. This hasn't been a real issue since currently the PCI2 sizes are the same as the PCI1 sizes for currently supported boards. Thanks to Andrew Klossner @ Xerox for point this out. Signed-off-by: Kumar Gala Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- diff --git a/arch/ppc/syslib/ppc85xx_setup.c b/arch/ppc/syslib/ppc85xx_setup.c index ca95d79a704e..b7242f1bd931 100644 --- a/arch/ppc/syslib/ppc85xx_setup.c +++ b/arch/ppc/syslib/ppc85xx_setup.c @@ -233,14 +233,14 @@ mpc85xx_setup_pci2(struct pci_controller *hose) pci->powbar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff; /* Enable, Mem R/W */ pci->powar1 = 0x80044000 | - (__ilog2(MPC85XX_PCI1_UPPER_MEM - MPC85XX_PCI1_LOWER_MEM + 1) - 1); + (__ilog2(MPC85XX_PCI2_UPPER_MEM - MPC85XX_PCI2_LOWER_MEM + 1) - 1); /* Setup outboud IO windows @ MPC85XX_PCI2_IO_BASE */ pci->potar2 = 0x00000000; pci->potear2 = 0x00000000; pci->powbar2 = (MPC85XX_PCI2_IO_BASE >> 12) & 0x000fffff; /* Enable, IO R/W */ - pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI1_IO_SIZE) - 1); + pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI2_IO_SIZE) - 1); /* Setup 2G inbound Memory Window @ 0 */ pci->pitar1 = 0x00000000;