From: Linus Torvalds Date: Thu, 29 Mar 2012 23:53:48 +0000 (-0700) Subject: Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-arm X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=12679a2d7e3bfbdc7586e3e86d1ca90c46659363;p=GitHub%2FLineageOS%2FG12%2Fandroid_kernel_amlogic_linux-4.9.git Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-arm Pull more ARM updates from Russell King. This got a fair number of conflicts with the split, but also with some other sparse-irq and header file include cleanups. They all looked pretty trivial, though. * 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (59 commits) ARM: fix Kconfig warning for HAVE_BPF_JIT ARM: 7361/1: provide XIP_VIRT_ADDR for no-MMU builds ARM: 7349/1: integrator: convert to sparse irqs ARM: 7259/3: net: JIT compiler for packet filters ARM: 7334/1: add jump label support ARM: 7333/2: jump label: detect %c support for ARM ARM: 7338/1: add support for early console output via semihosting ARM: use set_current_blocked() and block_sigmask() ARM: exec: remove redundant set_fs(USER_DS) ARM: 7332/1: extract out code patch function from kprobes ARM: 7331/1: extract out insn generation code from ftrace ARM: 7330/1: ftrace: use canonical Thumb-2 wide instruction format ARM: 7351/1: ftrace: remove useless memory checks ARM: 7316/1: kexec: EOI active and mask all interrupts in kexec crash path ARM: Versatile Express: add NO_IOPORT ARM: get rid of asm/irq.h in asm/prom.h ARM: 7319/1: Print debug info for SIGBUS in user faults ARM: 7318/1: gic: refactor irq_start assignment ARM: 7317/1: irq: avoid NULL check in for_each_irq_desc loop ARM: 7315/1: perf: add support for the Cortex-A7 PMU ... --- 12679a2d7e3bfbdc7586e3e86d1ca90c46659363 diff --cc arch/arm/Kconfig index 5098564d5879,1c0a6bb6f922..242f3a33d741 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@@ -847,9 -836,9 +841,8 @@@ config ARCH_S5PV21 select HAVE_CLK select CLKDEV_LOOKUP select CLKSRC_MMIO - select ARM_L1_CACHE_SHIFT_6 select ARCH_HAS_CPUFREQ select GENERIC_CLOCKEVENTS - select HAVE_SCHED_CLOCK select HAVE_S3C2410_I2C if I2C select HAVE_S3C_RTC if RTC_CLASS select HAVE_S3C2410_WATCHDOG if WATCHDOG diff --cc arch/arm/common/gic.c index f0783be17352,a3bc86fa3156..aa5269984187 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@@ -686,13 -697,12 +686,12 @@@ void __init gic_init_bases(unsigned in * For primary GICs, skip over SGIs. * For secondary GICs, skip over PPIs, too. */ - hwirq_base = 32; - if (gic_nr == 0) { - if ((irq_start & 31) > 0) { - hwirq_base = 16; - if (irq_start != -1) - irq_start = (irq_start & ~31) + 16; - } + if (gic_nr == 0 && (irq_start & 31) > 0) { - domain->hwirq_base = 16; ++ hwirq_base = 16; + if (irq_start != -1) + irq_start = (irq_start & ~31) + 16; + } else { - domain->hwirq_base = 32; ++ hwirq_base = 32; } /* diff --cc arch/arm/kernel/perf_event_v7.c index 4d7095af2ab3,b2b764ec011b..00755d82e2f2 --- a/arch/arm/kernel/perf_event_v7.c +++ b/arch/arm/kernel/perf_event_v7.c @@@ -593,22 -579,132 +593,146 @@@ static const unsigned armv7_a15_perf_ca [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, }, }, + [C(NODE)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, }; + /* + * Cortex-A7 HW events mapping + */ + static const unsigned armv7_a7_perf_map[PERF_COUNT_HW_MAX] = { + [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, + [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, + [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, + [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, + [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, + [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES, + [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED, + [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED, + }; + + static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] = { + [C(L1D)] = { + /* + * The performance counters don't differentiate between read + * and write accesses/misses so this isn't strictly correct, + * but it's the best we can do. Writes and reads get + * combined. + */ + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, + [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, + [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(L1I)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, + [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, + [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(LL)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS, + [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS, + [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(DTLB)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(ITLB)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(BPU)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, + [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, + [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + [C(NODE)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, + [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, + }, + }, + }; + /* * Perf Events' indices */ diff --cc arch/arm/kernel/process.c index 7b9cddef6e53,1531480aab48..2b7b017a20cd --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@@ -528,17 -531,36 +528,35 @@@ unsigned long arch_randomize_brk(struc #ifdef CONFIG_MMU /* * The vectors page is always readable from user space for the - * atomic helpers and the signal restart code. Let's declare a mapping - * for it so it is visible through ptrace and /proc//mem. + * atomic helpers and the signal restart code. Insert it into the + * gate_vma so that it is visible through ptrace and /proc//mem. */ + static struct vm_area_struct gate_vma; - int vectors_user_mapping(void) + static int __init gate_vma_init(void) { - struct mm_struct *mm = current->mm; - return install_special_mapping(mm, 0xffff0000, PAGE_SIZE, - VM_READ | VM_EXEC | - VM_MAYREAD | VM_MAYEXEC | VM_RESERVED, - NULL); + gate_vma.vm_start = 0xffff0000; + gate_vma.vm_end = 0xffff0000 + PAGE_SIZE; + gate_vma.vm_page_prot = PAGE_READONLY_EXEC; + gate_vma.vm_flags = VM_READ | VM_EXEC | - VM_MAYREAD | VM_MAYEXEC | - VM_ALWAYSDUMP; ++ VM_MAYREAD | VM_MAYEXEC; + return 0; + } + arch_initcall(gate_vma_init); + + struct vm_area_struct *get_gate_vma(struct mm_struct *mm) + { + return &gate_vma; + } + + int in_gate_area(struct mm_struct *mm, unsigned long addr) + { + return (addr >= gate_vma.vm_start) && (addr < gate_vma.vm_end); + } + + int in_gate_area_no_mm(unsigned long addr) + { + return in_gate_area(NULL, addr); } const char *arch_vma_name(struct vm_area_struct *vma) diff --cc arch/arm/mach-integrator/core.c index 1a65d77bd55d,304dfb2b346a..eaf6c6366ffa --- a/arch/arm/mach-integrator/core.c +++ b/arch/arm/mach-integrator/core.c @@@ -25,8 -25,10 +25,9 @@@ #include #include - #include #include + #include + -#include #include #include #include diff --cc arch/arm/mach-integrator/pci.c index 36068f438f2b,e15aa43cfd27..f1ca9c122861 --- a/arch/arm/mach-integrator/pci.c +++ b/arch/arm/mach-integrator/pci.c @@@ -26,7 -26,7 +26,6 @@@ #include #include - #include -#include #include #include diff --cc arch/arm/mach-integrator/pci_v3.c index 4be172c3cbe0,65e5896630e4..67e6f9a9d1a0 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c @@@ -30,8 -30,10 +30,9 @@@ #include #include - #include + #include + #include -#include #include #include diff --cc arch/arm/mach-msm/timer.c index 75f4be40b3e5,61983daa7bba..812808254936 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@@ -127,45 -128,11 +128,50 @@@ static struct clocksource msm_clocksour .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; +#ifdef CONFIG_LOCAL_TIMERS +static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt) +{ + /* Use existing clock_event for cpu 0 */ + if (!smp_processor_id()) + return 0; + + writel_relaxed(0, event_base + TIMER_ENABLE); + writel_relaxed(0, event_base + TIMER_CLEAR); + writel_relaxed(~0, event_base + TIMER_MATCH_VAL); + evt->irq = msm_clockevent.irq; + evt->name = "local_timer"; + evt->features = msm_clockevent.features; + evt->rating = msm_clockevent.rating; + evt->set_mode = msm_timer_set_mode; + evt->set_next_event = msm_timer_set_next_event; + evt->shift = msm_clockevent.shift; + evt->mult = div_sc(GPT_HZ, NSEC_PER_SEC, evt->shift); + evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt); + evt->min_delta_ns = clockevent_delta2ns(4, evt); + + *__this_cpu_ptr(msm_evt.percpu_evt) = evt; + clockevents_register_device(evt); + enable_percpu_irq(evt->irq, 0); + return 0; +} + +static void msm_local_timer_stop(struct clock_event_device *evt) +{ + evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt); + disable_percpu_irq(evt->irq); +} + +static struct local_timer_ops msm_local_timer_ops __cpuinitdata = { + .setup = msm_local_timer_setup, + .stop = msm_local_timer_stop, +}; +#endif /* CONFIG_LOCAL_TIMERS */ + + static notrace u32 msm_sched_clock_read(void) + { + return msm_clocksource.read(&msm_clocksource); + } + static void __init msm_timer_init(void) { struct clock_event_device *ce = &msm_clockevent; @@@ -232,8 -195,44 +238,10 @@@ err res = clocksource_register_hz(cs, dgt_hz); if (res) pr_err("clocksource_register failed\n"); + setup_sched_clock(msm_sched_clock_read, + cpu_is_msm7x01() ? 32 - MSM_DGT_SHIFT : 32, dgt_hz); } -#ifdef CONFIG_LOCAL_TIMERS -int __cpuinit local_timer_setup(struct clock_event_device *evt) -{ - /* Use existing clock_event for cpu 0 */ - if (!smp_processor_id()) - return 0; - - writel_relaxed(0, event_base + TIMER_ENABLE); - writel_relaxed(0, event_base + TIMER_CLEAR); - writel_relaxed(~0, event_base + TIMER_MATCH_VAL); - evt->irq = msm_clockevent.irq; - evt->name = "local_timer"; - evt->features = msm_clockevent.features; - evt->rating = msm_clockevent.rating; - evt->set_mode = msm_timer_set_mode; - evt->set_next_event = msm_timer_set_next_event; - evt->shift = msm_clockevent.shift; - evt->mult = div_sc(GPT_HZ, NSEC_PER_SEC, evt->shift); - evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt); - evt->min_delta_ns = clockevent_delta2ns(4, evt); - - *__this_cpu_ptr(msm_evt.percpu_evt) = evt; - clockevents_register_device(evt); - enable_percpu_irq(evt->irq, 0); - return 0; -} - -void local_timer_stop(struct clock_event_device *evt) -{ - evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt); - disable_percpu_irq(evt->irq); -} -#endif /* CONFIG_LOCAL_TIMERS */ - struct sys_timer msm_timer = { .init = msm_timer_init }; diff --cc arch/arm/mach-shmobile/board-marzen.c index cbd5e4cd06d2,3b2e88ae26be..ef0e13bf0b3a --- a/arch/arm/mach-shmobile/board-marzen.c +++ b/arch/arm/mach-shmobile/board-marzen.c @@@ -31,8 -31,11 +31,9 @@@ #include #include #include + #include #include #include -#include -#include #include #include diff --cc arch/arm/mach-shmobile/setup-r8a7740.c index 74e52341dd1b,fa15d81267ef..14edb5cffa7f --- a/arch/arm/mach-shmobile/setup-r8a7740.c +++ b/arch/arm/mach-shmobile/setup-r8a7740.c @@@ -25,41 -25,9 +25,42 @@@ #include #include #include +#include + #include #include +#include #include +#include + +static struct map_desc r8a7740_io_desc[] __initdata = { + /* + * for CPGA/INTC/PFC + * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff + */ + { + .virtual = 0xe6000000, + .pfn = __phys_to_pfn(0xe6000000), + .length = 160 << 20, + .type = MT_DEVICE_NONSHARED + }, +#ifdef CONFIG_CACHE_L2X0 + /* + * for l2x0_init() + * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000 + */ + { + .virtual = 0xf0002000, + .pfn = __phys_to_pfn(0xf0100000), + .length = PAGE_SIZE, + .type = MT_DEVICE_NONSHARED + }, +#endif +}; + +void __init r8a7740_map_io(void) +{ + iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc)); +} /* SCIFA0 */ static struct plat_sci_port scif0_platform_data = { diff --cc arch/arm/mach-shmobile/setup-sh7367.c index a51e1a1e6996,8e84819833a8..2e3074ab75b3 --- a/arch/arm/mach-shmobile/setup-sh7367.c +++ b/arch/arm/mach-shmobile/setup-sh7367.c @@@ -29,28 -29,9 +29,29 @@@ #include #include #include +#include + #include #include #include +#include +#include + +static struct map_desc sh7367_io_desc[] __initdata = { + /* create a 1:1 entity map for 0xe6xxxxxx + * used by CPGA, INTC and PFC. + */ + { + .virtual = 0xe6000000, + .pfn = __phys_to_pfn(0xe6000000), + .length = 256 << 20, + .type = MT_DEVICE_NONSHARED + }, +}; + +void __init sh7367_map_io(void) +{ + iotable_init(sh7367_io_desc, ARRAY_SIZE(sh7367_io_desc)); +} /* SCIFA0 */ static struct plat_sci_port scif0_platform_data = { diff --cc arch/arm/mach-shmobile/setup-sh7372.c index 4e818b7de781,420d25c0d742..2fe8f83ca124 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c @@@ -31,37 -31,11 +31,38 @@@ #include #include #include +#include #include + #include #include +#include +#include #include #include +#include + +static struct map_desc sh7372_io_desc[] __initdata = { + /* create a 1:1 entity map for 0xe6xxxxxx + * used by CPGA, INTC and PFC. + */ + { + .virtual = 0xe6000000, + .pfn = __phys_to_pfn(0xe6000000), + .length = 256 << 20, + .type = MT_DEVICE_NONSHARED + }, +}; + +void __init sh7372_map_io(void) +{ + iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc)); + + /* + * DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't + * enough to allocate the frame buffer memory. + */ + init_consistent_dma_size(12 << 20); +} /* SCIFA0 */ static struct plat_sci_port scif0_platform_data = { diff --cc arch/arm/mach-shmobile/setup-sh7377.c index 9f146095098b,747ed8ef84ef..d576a6abbade --- a/arch/arm/mach-shmobile/setup-sh7377.c +++ b/arch/arm/mach-shmobile/setup-sh7377.c @@@ -30,28 -30,9 +30,29 @@@ #include #include #include +#include +#include + #include #include #include +#include + +static struct map_desc sh7377_io_desc[] __initdata = { + /* create a 1:1 entity map for 0xe6xxxxxx + * used by CPGA, INTC and PFC. + */ + { + .virtual = 0xe6000000, + .pfn = __phys_to_pfn(0xe6000000), + .length = 256 << 20, + .type = MT_DEVICE_NONSHARED + }, +}; + +void __init sh7377_map_io(void) +{ + iotable_init(sh7377_io_desc, ARRAY_SIZE(sh7377_io_desc)); +} /* SCIFA0 */ static struct plat_sci_port scif0_platform_data = { diff --cc arch/arm/mach-shmobile/setup-sh73a0.c index b6a0734a738e,7bf740e29a3a..5bebffc10455 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@@ -31,29 -31,10 +31,30 @@@ #include #include #include + #include #include +#include #include +#include #include +#include + +static struct map_desc sh73a0_io_desc[] __initdata = { + /* create a 1:1 entity map for 0xe6xxxxxx + * used by CPGA, INTC and PFC. + */ + { + .virtual = 0xe6000000, + .pfn = __phys_to_pfn(0xe6000000), + .length = 256 << 20, + .type = MT_DEVICE_NONSHARED + }, +}; + +void __init sh73a0_map_io(void) +{ + iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc)); +} static struct plat_sci_port scif0_platform_data = { .mapbase = 0xe6c40000, diff --cc arch/c6x/Kconfig index 3c64b2894c13,2f58c61e2812..1c3ccd416d50 --- a/arch/c6x/Kconfig +++ b/arch/c6x/Kconfig @@@ -11,8 -11,7 +11,8 @@@ config TMS320C6 select HAVE_DMA_API_DEBUG select HAVE_GENERIC_HARDIRQS select HAVE_MEMBLOCK - select HAVE_SPARSE_IRQ + select SPARSE_IRQ + select IRQ_DOMAIN select OF select OF_EARLY_FLATTREE diff --cc arch/powerpc/Kconfig index eeaa5328b862,06c1cf0f24a6..feab3bad6d0f --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@@ -133,10 -133,8 +133,9 @@@ config PP select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_HW_BREAKPOINT if PERF_EVENTS && PPC_BOOK3S_64 select HAVE_GENERIC_HARDIRQS - select HAVE_SPARSE_IRQ - select MAY_HAVE_SPARSE_IRQ + select SPARSE_IRQ select IRQ_PER_CPU + select IRQ_DOMAIN select GENERIC_IRQ_SHOW select GENERIC_IRQ_SHOW_LEVEL select IRQ_FORCED_THREADING