From: Adam Jackson Date: Tue, 26 Jul 2011 19:39:45 +0000 (-0400) Subject: drm/i915/dp: Use auxch precharge value of 5 everywhere X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=092945e11c5b84f66dd08f0b87fb729715d377bc;p=GitHub%2Fexynos8895%2Fandroid_kernel_samsung_universal8895.git drm/i915/dp: Use auxch precharge value of 5 everywhere The default in the Sandybridge docs is 5, as on Ironlake, and I have no reason to believe 3 would work any better. Signed-off-by: Adam Jackson Acked-by: Jesse Barnes Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index add871911a63..2f4766385797 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -362,7 +362,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, int recv_bytes; uint32_t status; uint32_t aux_clock_divider; - int try, precharge; + int try, precharge = 5; intel_dp_check_edp(intel_dp); /* The clock divider is based off the hrawclk, @@ -382,11 +382,6 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, else aux_clock_divider = intel_hrawclk(dev) / 2; - if (IS_GEN6(dev)) - precharge = 3; - else - precharge = 5; - /* Try to wait for any previous AUX channel activity */ for (try = 0; try < 3; try++) { status = I915_READ(ch_ctl);