From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Tue, 4 Jul 2017 15:23:12 +0000 (+0200)
Subject: ARM: dts: r8a7743: Add Inter Connect RAM
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=06278baa1b08f2b2ae26d5b2394b779ed82f3dfa;p=GitHub%2FLineageOS%2Fandroid_kernel_motorola_exynos9610.git

ARM: dts: r8a7743: Add Inter Connect RAM

RZ/G1M has 3 regions of Inter Connect RAM (72 + 4 + 256 KiB).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 0c73fa8047b9..2cdb9a7115af 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -593,6 +593,21 @@
 			status = "disabled";
 		};
 
+		icram2:	sram@e6300000 {
+			compatible = "mmio-sram";
+			reg = <0 0xe6300000 0 0x40000>;
+		};
+
+		icram0:	sram@e63a0000 {
+			compatible = "mmio-sram";
+			reg = <0 0xe63a0000 0 0x12000>;
+		};
+
+		icram1:	sram@e63c0000 {
+			compatible = "mmio-sram";
+			reg = <0 0xe63c0000 0 0x1000>;
+		};
+
 		ether: ethernet@ee700000 {
 			compatible = "renesas,ether-r8a7743";
 			reg = <0 0xee700000 0 0x400>;