From: Jason Gaston Date: Fri, 21 Dec 2007 00:27:19 +0000 (+0100) Subject: x86: intel_cacheinfo.c: cpu cache info entry for Intel Tolapai X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=04fa11ea170afd147b5d1e1ec88ec359a766bf31;p=GitHub%2Fmt8127%2Fandroid_kernel_alcatel_ttab.git x86: intel_cacheinfo.c: cpu cache info entry for Intel Tolapai This patch adds a cpu cache info entry for the Intel Tolapai cpu. Signed-off-by: Jason Gaston Signed-off-by: Ingo Molnar Signed-off-by: Thomas Gleixner --- diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index 606fe4d55a91..9f530ff43c21 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c @@ -49,6 +49,7 @@ static struct _cache_table cache_table[] __cpuinitdata = { 0x3c, LVL_2, 256 }, /* 4-way set assoc, sectored cache, 64 byte line size */ { 0x3d, LVL_2, 384 }, /* 6-way set assoc, sectored cache, 64 byte line size */ { 0x3e, LVL_2, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */ + { 0x3f, LVL_2, 256 }, /* 2-way set assoc, 64 byte line size */ { 0x41, LVL_2, 128 }, /* 4-way set assoc, 32 byte line size */ { 0x42, LVL_2, 256 }, /* 4-way set assoc, 32 byte line size */ { 0x43, LVL_2, 512 }, /* 4-way set assoc, 32 byte line size */