From: Andi Kleen Date: Fri, 8 Aug 2014 00:08:54 +0000 (-0700) Subject: perf/x86: Fix :pp without LBR X-Git-Tag: MMI-PSA29.97-13-9~11369^2~36 X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=03de874aa76ac0adcf6f56ebf3de623d09a5dde3;p=GitHub%2FMotorolaMobilityLLC%2Fkernel-slsi.git perf/x86: Fix :pp without LBR This fixes a side effect of Kan's earlier patch to probe the LBRs at boot time. Normally when the LBRs are disabled cycles:pp is disabled too. So for example cycles:pp doesn't work. However this is not needed with PEBSv2 and later (Haswell) because it does not need LBRs to correct the IP-off-by-one. So add an extra check for PEBSv2 that also allows :pp Signed-off-by: Andi Kleen Signed-off-by: Peter Zijlstra Cc: kan.liang@intel.com Cc: Arnaldo Carvalho de Melo Link: http://lkml.kernel.org/r/1407456534-15747-1-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar --- diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index 2879ecdaac43..0646d3b63b9d 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c @@ -387,7 +387,7 @@ int x86_pmu_hw_config(struct perf_event *event) precise++; /* Support for IP fixup */ - if (x86_pmu.lbr_nr) + if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2) precise++; }