From: Peter De Schrijver <pdeschrijver@nvidia.com>
Date: Tue, 25 Jul 2017 10:34:04 +0000 (+0300)
Subject: clk: tegra: disable SSC for PLL_D2
X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=030999fe514d2d6dbabf0ed6727f4c493082d99d;p=GitHub%2Fmoto-9609%2Fandroid_kernel_motorola_exynos9610.git

clk: tegra: disable SSC for PLL_D2

PLLD2 is used for HDMI which does not allow Spread Spectrum clocking.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---

diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 1024e853ea65..facd6ee672dc 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -146,7 +146,7 @@
 #define PLLD_SDM_EN_MASK BIT(16)
 
 #define PLLD2_SDM_EN_MASK BIT(31)
-#define PLLD2_SSC_EN_MASK BIT(30)
+#define PLLD2_SSC_EN_MASK 0
 
 #define PLLDP_SS_CFG	0x598
 #define PLLDP_SDM_EN_MASK BIT(31)