From: Markos Chandras Date: Thu, 30 Jan 2014 17:21:29 +0000 (+0000) Subject: MIPS: mm: c-r4k: Detect instruction cache aliases X-Git-Tag: MMI-PSA29.97-13-9~12486^2~162 X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=02dc6bfb080e8205aacea5c4b4dd6a9bd4c9406e;p=GitHub%2FMotorolaMobilityLLC%2Fkernel-slsi.git MIPS: mm: c-r4k: Detect instruction cache aliases The *Aptiv cores can use the CONF7/IAR bit to detect if the core has hardware support to remove instruction cache aliasing. This also defines the CONF7/AR bit in order to avoid using the '16' magic number. Signed-off-by: Markos Chandras Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6499/ Signed-off-by: Ralf Baechle --- diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index bbc3dd4294bc..0c746176d31c 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -653,6 +653,9 @@ #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) +#define MIPS_CONF7_IAR (_ULCAST_(1) << 10) +#define MIPS_CONF7_AR (_ULCAST_(1) << 16) + /* EntryHI bit definition */ #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10) diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index c14259edd53f..8f1d549d5132 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1117,9 +1117,14 @@ static void probe_pcache(void) case CPU_PROAPTIV: if (current_cpu_type() == CPU_74K) alias_74k_erratum(c); - if ((read_c0_config7() & (1 << 16))) { - /* effectively physically indexed dcache, - thus no virtual aliases. */ + if (!(read_c0_config7() & MIPS_CONF7_IAR) && + (c->icache.waysize > PAGE_SIZE)) + c->icache.flags |= MIPS_CACHE_ALIASES; + if (read_c0_config7() & MIPS_CONF7_AR) { + /* + * Effectively physically indexed dcache, + * thus no virtual aliases. + */ c->dcache.flags |= MIPS_CACHE_PINDEX; break; }