From: Alexander Kochetkov Date: Sun, 6 Mar 2016 10:04:17 +0000 (+0300) Subject: spi/rockchip: fix endian mode for 16-bit transfers X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=0277e01aebc8895198a4717ccaf7e4fcf39ada78;p=GitHub%2FLineageOS%2FG12%2Fandroid_kernel_amlogic_linux-4.9.git spi/rockchip: fix endian mode for 16-bit transfers 16-bit transfers must be in big endian mode on wire. Signed-off-by: Alexander Kochetkov Signed-off-by: Mark Brown --- diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 6cdb4d81d66c..9a5c51764833 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -506,7 +506,8 @@ static void rockchip_spi_config(struct rockchip_spi *rs) int rsd = 0; u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET) - | (CR0_SSD_ONE << CR0_SSD_OFFSET); + | (CR0_SSD_ONE << CR0_SSD_OFFSET) + | (CR0_EM_BIG << CR0_EM_OFFSET); cr0 |= (rs->n_bytes << CR0_DFS_OFFSET); cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);