From: Linus Torvalds Date: Fri, 1 Aug 2008 17:53:43 +0000 (-0700) Subject: Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6 X-Git-Url: https://git.stricted.de/?a=commitdiff_plain;h=00e9028a95fb8a4d79f2fb695a853f33ea7d3b57;p=GitHub%2Fexynos8895%2Fandroid_kernel_samsung_universal8895.git Merge git://git./linux/kernel/git/lethal/sh-2.6 * git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (28 commits) mm/hugetlb.c must #include video: Fix up hp6xx driver build regressions. sh: defconfig updates. sh: Kill off stray mach-rsk7203 reference. serial: sh-sci: Fix up SH7760/SH7780/SH7785 early printk regression. sh: Move out individual boards without mach groups. sh: Make sure AT_SYSINFO_EHDR is exposed to userspace in asm/auxvec.h. sh: Allow SH-3 and SH-5 to use common headers. sh: Provide common CPU headers, prune the SH-2 and SH-2A directories. sh/maple: clean maple bus code sh: More header path fixups for mach dir refactoring. sh: Move out the solution engine headers to arch/sh/include/mach-se/ sh: I2C fix for AP325RXA and Migo-R sh: Shuffle the board directories in to mach groups. sh: dma-sh: Fix up dreamcast dma.h mach path. sh: Switch KBUILD_DEFCONFIG to shx3_defconfig. sh: Add ARCH_DEFCONFIG entries for sh and sh64. sh: Fix compile error of Solution Engine sh: Proper __put_user_asm() size mismatch fix. sh: Stub in a dummy ENTRY_OFFSET for uImage offset calculation. ... --- 00e9028a95fb8a4d79f2fb695a853f33ea7d3b57 diff --cc arch/sh/include/asm/dma-mapping.h index 000000000000,6c0b8a2de143..627315ecdb52 mode 000000,100644..100644 --- a/arch/sh/include/asm/dma-mapping.h +++ b/arch/sh/include/asm/dma-mapping.h @@@ -1,0 -1,192 +1,193 @@@ + #ifndef __ASM_SH_DMA_MAPPING_H + #define __ASM_SH_DMA_MAPPING_H + + #include + #include + #include + #include ++#include + + extern struct bus_type pci_bus_type; + + #define dma_supported(dev, mask) (1) + + static inline int dma_set_mask(struct device *dev, u64 mask) + { + if (!dev->dma_mask || !dma_supported(dev, mask)) + return -EIO; + + *dev->dma_mask = mask; + + return 0; + } + + void *dma_alloc_coherent(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t flag); + + void dma_free_coherent(struct device *dev, size_t size, + void *vaddr, dma_addr_t dma_handle); + + void dma_cache_sync(struct device *dev, void *vaddr, size_t size, + enum dma_data_direction dir); + + #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) + #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) + #define dma_is_consistent(d, h) (1) + + static inline dma_addr_t dma_map_single(struct device *dev, + void *ptr, size_t size, + enum dma_data_direction dir) + { + #if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT) + if (dev->bus == &pci_bus_type) + return virt_to_phys(ptr); + #endif + dma_cache_sync(dev, ptr, size, dir); + + return virt_to_phys(ptr); + } + + #define dma_unmap_single(dev, addr, size, dir) do { } while (0) + + static inline int dma_map_sg(struct device *dev, struct scatterlist *sg, + int nents, enum dma_data_direction dir) + { + int i; + + for (i = 0; i < nents; i++) { + #if !defined(CONFIG_PCI) || defined(CONFIG_SH_PCIDMA_NONCOHERENT) + dma_cache_sync(dev, sg_virt(&sg[i]), sg[i].length, dir); + #endif + sg[i].dma_address = sg_phys(&sg[i]); + } + + return nents; + } + + #define dma_unmap_sg(dev, sg, nents, dir) do { } while (0) + + static inline dma_addr_t dma_map_page(struct device *dev, struct page *page, + unsigned long offset, size_t size, + enum dma_data_direction dir) + { + return dma_map_single(dev, page_address(page) + offset, size, dir); + } + + static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address, + size_t size, enum dma_data_direction dir) + { + dma_unmap_single(dev, dma_address, size, dir); + } + + static inline void dma_sync_single(struct device *dev, dma_addr_t dma_handle, + size_t size, enum dma_data_direction dir) + { + #if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT) + if (dev->bus == &pci_bus_type) + return; + #endif + dma_cache_sync(dev, phys_to_virt(dma_handle), size, dir); + } + + static inline void dma_sync_single_range(struct device *dev, + dma_addr_t dma_handle, + unsigned long offset, size_t size, + enum dma_data_direction dir) + { + #if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT) + if (dev->bus == &pci_bus_type) + return; + #endif + dma_cache_sync(dev, phys_to_virt(dma_handle) + offset, size, dir); + } + + static inline void dma_sync_sg(struct device *dev, struct scatterlist *sg, + int nelems, enum dma_data_direction dir) + { + int i; + + for (i = 0; i < nelems; i++) { + #if !defined(CONFIG_PCI) || defined(CONFIG_SH_PCIDMA_NONCOHERENT) + dma_cache_sync(dev, sg_virt(&sg[i]), sg[i].length, dir); + #endif + sg[i].dma_address = sg_phys(&sg[i]); + } + } + + static inline void dma_sync_single_for_cpu(struct device *dev, + dma_addr_t dma_handle, size_t size, + enum dma_data_direction dir) + { + dma_sync_single(dev, dma_handle, size, dir); + } + + static inline void dma_sync_single_for_device(struct device *dev, + dma_addr_t dma_handle, + size_t size, + enum dma_data_direction dir) + { + dma_sync_single(dev, dma_handle, size, dir); + } + + static inline void dma_sync_single_range_for_cpu(struct device *dev, + dma_addr_t dma_handle, + unsigned long offset, + size_t size, + enum dma_data_direction direction) + { + dma_sync_single_for_cpu(dev, dma_handle+offset, size, direction); + } + + static inline void dma_sync_single_range_for_device(struct device *dev, + dma_addr_t dma_handle, + unsigned long offset, + size_t size, + enum dma_data_direction direction) + { + dma_sync_single_for_device(dev, dma_handle+offset, size, direction); + } + + + static inline void dma_sync_sg_for_cpu(struct device *dev, + struct scatterlist *sg, int nelems, + enum dma_data_direction dir) + { + dma_sync_sg(dev, sg, nelems, dir); + } + + static inline void dma_sync_sg_for_device(struct device *dev, + struct scatterlist *sg, int nelems, + enum dma_data_direction dir) + { + dma_sync_sg(dev, sg, nelems, dir); + } + + + static inline int dma_get_cache_alignment(void) + { + /* + * Each processor family will define its own L1_CACHE_SHIFT, + * L1_CACHE_BYTES wraps to this, so this is always safe. + */ + return L1_CACHE_BYTES; + } + + static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) + { + return dma_addr == 0; + } + + #define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY + + extern int + dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr, + dma_addr_t device_addr, size_t size, int flags); + + extern void + dma_release_declared_memory(struct device *dev); + + extern void * + dma_mark_declared_memory_occupied(struct device *dev, + dma_addr_t device_addr, size_t size); + + #endif /* __ASM_SH_DMA_MAPPING_H */ diff --cc mm/hugetlb.c index 254ce2b90158,b3c78640b629..d237a02eb228 --- a/mm/hugetlb.c +++ b/mm/hugetlb.c @@@ -17,10 -16,9 +17,10 @@@ #include #include #include - + #include #include #include +#include #include #include "internal.h"