drm: rcar-du: lvds: Fix LVDS startup on R-Car Gen2

[ Upstream commit 8525d04ba8a6a9ecfa4bd619c988ca873a5fc2a4 ]

According to the latest revision 2.00 of the R-Car Gen2 manual, the LVDS
and the bias circuit must be enabled after the LVDS I/O pins are
enabled, not before. Fix the Gen2 LVDS startup sequence accordingly.

While at it, also fix the comment preceding the first LVDCR0 write that
still talks about hardcoding the LVDS mode 0.

Fixes: 90374b5c25c9 ("drm/rcar-du: Add internal LVDS encoder support")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
index 97342240c74d9a6c9a8276674511de9d79b8e3e7..6a4b8c98a719d9bfee3427b290394d0a63c69f8e 100644 (file)
--- a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
@@ -59,11 +59,8 @@ static void rcar_du_lvdsenc_start_gen2(struct rcar_du_lvdsenc *lvds,
 
        rcar_lvds_write(lvds, LVDPLLCR, pllcr);
 
-       /*
-        * Select the input, hardcode mode 0, enable LVDS operation and turn
-        * bias circuitry on.
-        */
-       lvdcr0 = (lvds->mode << LVDCR0_LVMD_SHIFT) | LVDCR0_BEN | LVDCR0_LVEN;
+       /* Select the input and set the LVDS mode. */
+       lvdcr0 = lvds->mode << LVDCR0_LVMD_SHIFT;
        if (rcrtc->index == 2)
                lvdcr0 |= LVDCR0_DUSEL;
        rcar_lvds_write(lvds, LVDCR0, lvdcr0);
@@ -74,6 +71,10 @@ static void rcar_du_lvdsenc_start_gen2(struct rcar_du_lvdsenc *lvds,
                        LVDCR1_CHSTBY_GEN2(1) | LVDCR1_CHSTBY_GEN2(0) |
                        LVDCR1_CLKSTBY_GEN2);
 
+       /* Enable LVDS operation and turn bias circuitry on. */
+       lvdcr0 |= LVDCR0_BEN | LVDCR0_LVEN;
+       rcar_lvds_write(lvds, LVDCR0, lvdcr0);
+
        /*
         * Turn the PLL on, wait for the startup delay, and turn the output
         * on.