[KVM,ARM] Trap guest accesses to GICv3 group-1
system registers
+ kvm-arm.vgic_v3_common_trap=
+ [KVM,ARM] Trap guest accesses to GICv3 common
+ system registers
+
kvm-intel.ept= [KVM,Intel] Disable extended page tables
(virtualized MMU) support on capable Intel chips.
Default is 1 (enabled)
#define ICH_HCR_EN (1 << 0)
#define ICH_HCR_UIE (1 << 1)
+#define ICH_HCR_TC (1 << 10)
#define ICH_HCR_TALL0 (1 << 11)
#define ICH_HCR_TALL1 (1 << 12)
#define ICH_HCR_EOIcount_SHIFT 27
static bool group0_trap;
static bool group1_trap;
+static bool common_trap;
void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
{
vgic_v3->vgic_hcr |= ICH_HCR_TALL0;
if (group1_trap)
vgic_v3->vgic_hcr |= ICH_HCR_TALL1;
+ if (common_trap)
+ vgic_v3->vgic_hcr |= ICH_HCR_TC;
}
int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq)
}
early_param("kvm-arm.vgic_v3_group1_trap", early_group1_trap_cfg);
+static int __init early_common_trap_cfg(char *buf)
+{
+ return strtobool(buf, &common_trap);
+}
+early_param("kvm-arm.vgic_v3_common_trap", early_common_trap_cfg);
+
/**
* vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
* @node: pointer to the DT node
}
#endif
- if (group0_trap || group1_trap) {
+ if (group0_trap || group1_trap || common_trap) {
kvm_info("GICv3 sysreg trapping enabled (reduced performance)\n");
static_branch_enable(&vgic_v3_cpuif_trap);
}